# UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

Size: px
Start display at page:

Download "UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences"

Transcription

1 UNIVERSITY OF LIFORNI, ERKELEY ollege of Engineering Department of Electrical Engineering and omputer Sciences Elad lon Homework #3 EE141 Due Thursday, September 13 th, 5pm, box outside 125 ory PROLEM 1: MOS Logic a) Implement the logic function shown below with a static MOS gate. Out = + + Note that we can first simplify this expression implementing this logic gate. Out = + + = = = + = ( + ) The expression is now in a simplified form which is easily translated into a static MOS gate: Vdd Out 1

2 b) Someone claims they have implemented a static MOS gate with the circuit shown below. In order to find the problem with this gate, using the switch model, fill in a table showing the voltage (i.e., Vdd, Gnd, Vth, etc.) at Out for all possible combinations of the inputs,, and. In other words, you should fill out the truth table for the gate, but with voltages instead of ones and zeros. Vdd Out First, we should write out a truth table (with voltages at the output) for this circuit. Out Gnd Gnd Gnd Vdd-Vth Gnd 1 0 1??? Gnd Vdd-Vth y looking at the truth table, we see that there are several problematic input combinations. In particular, when the input combination -- equals either or 1-1-1, the output is not driven by Vdd via a low resistance path but instead gets stuck at Vdd-Vth, because NMOS transistors are poor at passing a logical 1. The input combination -- equals is an issue as well, but for a different reason. In this case, the output is not well defined, since the node connected to the PMOS driven by and the NMOS driven by isn t tied to either supply. ecause of these issues, this is not a static MOS gate. c) y adding just two more transistors to the circuit shown above, fix the circuit so that it will indeed implement a static gate, with the function shown below. Note 2

3 that you are free to use both the true and complement versions of the input signals (,, and ) to achieve this. Out = ( + ) In the solution to part b), we grouped the three problematic input combinations into two different groups. In the case of the first group, which consists input combinations and (in the form --), the problem stems from NMOS transistors doing a poor job at passing a logical 1. One way to fix this is to use a PMOS transistor in parallel, with the gate tied to. This way, when = 1, the input to the PMOS will be 0, and it will be able to cleanly pass Vdd to the output. For the last problematic input combination, we note that the NMOS which is driven by when = 0 is essentially half of an inverter. The drain of the NMOS is floating (ie, not connected to ground or supply via a low resistance path) when = 1. To fix this, we should add the other half of the inverter, and add a PMOS with the gate, drain connected to the same nets as the gate, drain of the NMOS, and with its source tied to Vdd. This revised schematic is shown below: Vdd Out To verify that this implements the desired function, let s write out the truth table : Out Gnd Gnd Gnd Vdd Gnd Vdd 3

4 1 1 0 Gnd Vdd We can write out the sum-of-products expression and simplify: Out = + + = = = + = ( + ) Now, we ve verified that this is a static MOS gate that implements the desired function PROLEM 2: Gate Sizing Recall that we have defined β as the ratio between the width of the PMOS transistor and NMOS transistor i.e., β = W p /W n. In this problem we will explore how to optimize β based on different design metrics by using HSPIE. For the following OI gate, we will use the same sizing for all PMOS transistors in the PUN. Similarly, all the NMOS transistors in the PDN are identically sized. You should make the NMOS transistor 1μm wide, and alter the width of the PMOS transistor to change the gate s β ratio. The channel lengths of both the NMOS and PMOS transistors should be fixed at 0.09μm. This is a good chance to explore HSPIE and use some of its built-in functionality to make this problem easier. (Hint: you ll want to sweep transistor parameters and use.mesure statements. Examples will be shown in discussion session.) a) Plot VIL and VIH of the OI gate shown below versus the β ratio, for the input. In order to measure VIL and VIH, you should assume that the, inputs are set to Vdd and GND, respectively, and then sweep the input from 0 to Vdd to trace out the VT. 4

5 Vdd β β β 1μm 1μm 1μm Out The plot of VIL (yellow) and VIH (green) vs β is shown below: * HW3, Problem 2a 5

6 .lib '/home/ff/ee141/models/gpdk090_mos.sp' TT_S1V ** Parameters **.param step =.001.param vdd_val = 1.2.param beta = 2 ** OI defintion **.subckt aoi out a b c gnd ** Power Supply ** vdd vdd gnd vdd_val ** Pull Up Network ** M0 pint a vdd vdd gpdk090_pmos1v L=90e-9 W='beta*1e-6' M1 pint b vdd vdd gpdk090_pmos1v L=90e-9 W='beta*1e-6' M2 out c pint vdd gpdk090_pmos1v L=90e-9 W='beta*1e-6' ** Pull Down Network ** M3 out a nint gnd gpdk090_nmos1v L=90e-9 W=1u M4 nint b gnd gnd gpdk090_nmos1v L=90e-9 W=1u M5 out c gnd gnd gpdk090_nmos1v L=90e-9 W=1u.ends ** Power Supplies ** vdd vdd gnd vdd_val vin in gnd vdd_val vind ind in step ** OI Gates for Vil, Vih ** X0 out in vdd gnd gnd aoi M=1 X0d outd ind vdd gnd gnd aoi M=1 ** Options **.options post=2 nomod.op ** D Sweep **.dc vin 0 vdd_val step beta ** Vil and Vil measurements vs beta **.measure dc vil find v(in) when par('(v(outd)-v(out))/step')=-1 cross=1.measure dc vih find v(in) when par('(v(outd)-v(out))/step')=-1 cross=2.end 6

7 b) Sweep β and plot the high-to-low transition delay and the low-to-high transition delay for the second OI gate in the fanout-of-4 chain shown below. t p Vdd M = 1 Vdd M = 4 Vdd M = 16 Vdd M = 64 Out The plot of high-to-low (green) and low-to-high (yellow) transition delays versus beta is shown below: * HW3, Problem 2b.lib '/home/ff/ee141/models/gpdk090_mos.sp' TT_S1V ** Parameters **.param step =.001.param vdd_val = 1.2.param beta = 2 ** OI defintion ** 7

8 .subckt aoi out a b c gnd ** Power Supply ** vdd vdd gnd vdd_val ** Pull Up Network ** M0 pint a vdd vdd gpdk090_pmos1v L=90e-9 W='beta*1e-6' M1 pint b vdd vdd gpdk090_pmos1v L=90e-9 W='beta*1e-6' M2 out c pint vdd gpdk090_pmos1v L=90e-9 W='beta*1e-6' ** Pull Down Network ** M3 out a nint gnd gpdk090_nmos1v L=90e-9 W=1u M4 nint b gnd gnd gpdk090_nmos1v L=90e-9 W=1u M5 out c gnd gnd gpdk090_nmos1v L=90e-9 W=1u.ends ** Power Supplies ** vdd vdd gnd vdd_val vin1 in1 gnd pulse 0 vdd_val 100ps 100ps 100ps.4ns 1ns ** OI Gates for delay measurements ** X1 in2 in1 vdd gnd gnd aoi M=1 X2 in3 in2 vdd gnd gnd aoi M=4 X3 in4 in3 vdd gnd gnd aoi M=16 X4 out_delay in4 vdd gnd gnd aoi M=64 ** Options **.options post=2 nomod.op ** Transient Simulation **.tran 100f 5n sweep beta ** Delay Measurements vs beta**.measure tran tplh trig v(in1) val='vdd_val/2' fall=2 targ v(in2) val='vdd_val/2' + rise=2.measure tran tphl trig v(in1) val='vdd_val/2' rise=2 targ v(in2) val='vdd_val/2' + fall=2 ** Worst case delay through 3 gates vs beta for part c **.measure tran delay_case1 param='tplh+2*tphl'.measure tran delay_case2 param='2*tplh+tphl'.measure tran delay_wc param='max(delay_case1, delay_case2)'.end 8

9 c) What β would you use to minimize the worst case delay of 3 fanout-of-4 OI gates? (Hint: The delay characteristics are the same as in part b you should be able to use the data extracted from there to answer this) In the netlist in part b), there were several lines included which used measure the worst case delay of a cascade of three of these OI gates, each with a fanout of 4. These lines are listed below:.measure tran delay_case1 param='tplh+2*tphl'.measure tran delay_case2 param='2*tplh+tphl'.measure tran delay_wc param='max(delay_case1, delay_case2)' s stated in the code, there are two delays for a cascade of three gates: one which involves 2 high-to-low and 1 low-to-high transitions, and one that involves 1 high-to-low and 2 low-to-high transitions. We take the max of these two to get the worst case. This generates a plot for the worst case delay of 3 fanout-of-4 OI gates, vs beta, as shown below: From this plot, we see that there is a shallow minimum for worst case delay for beta ranging from about 1.4 to 1.8. d) Sweep β and measure the energy and power of this same OI gate. In this simulation, you should make the input voltage source a 1GHz clock with a 50% 9

10 duty cycle and 100ps rise/fall time. (n example of how to measure average power and energy using HSPIE will be shown in the discussion session.) elow are the plots of energy, power vs beta, respectively: 10

11 The plots look roughly linear with beta. This fits with our intuition, as the by increasing beta, we re linearly increasing the drain capacitance of the PMOS transistors in this gate and the gate capacitance of the PMOS transistors in the next stage. Energy is proportional to capacitance, so it should scale linearly as capacitance scales. verage power should have the same shape, since it is just the energy in a cycle divided by the period of the cycle. The netlist for this portion is shown below: * HW3, Problem 2d.lib '/home/ff/ee141/models/gpdk090_mos.sp' TT_S1V ** Parameters **.param step =.001.param vdd_val = 1.2.param beta = 2 ** OI defintion **.subckt aoi out a b c gnd ** Power Supply ** vdd vdd gnd vdd_val 11

12 ** Pull Up Network ** M0 pint a vdd vdd gpdk090_pmos1v L=90e-9 W='beta*1e-6' M1 pint b vdd vdd gpdk090_pmos1v L=90e-9 W='beta*1e-6' M2 out c pint vdd gpdk090_pmos1v L=90e-9 W='beta*1e-6' ** Pull Down Network ** M3 out a nint gnd gpdk090_nmos1v L=90e-9 W=1u M4 nint b gnd gnd gpdk090_nmos1v L=90e-9 W=1u M5 out c gnd gnd gpdk090_nmos1v L=90e-9 W=1u.ends ** Power Supplies ** vdd vdd gnd vdd_val vin1 in1 gnd pulse 0 vdd_val 100ps 100ps 100ps.4ns 1ns ** OI Gates for delay measurements ** X1 in2 in1 vdd gnd gnd aoi M=1 X2 in3 in2 vdd gnd gnd aoi M=4 X3 in4 in3 vdd gnd gnd aoi M=16 X4 out_delay in4 vdd gnd gnd aoi M=64 ** Options **.options post=2 nomod.op ** Transient Simulation **.tran 100f 5n sweep beta ** Energy measurements vs beta **.measure tran tstart when v(in1)='vdd_val/2' rise=2.measure tran tstop when v(in1)='vdd_val/2' rise=3.measure tran i_avg avg i(x2.vdd) from='tstart' to='tstop'.measure tran energy param='-1 * i_avg * (tstop - tstart)'.measure tran p_avg param='-1 * i_avg * vdd_val'.end PROLEM 3: Decoder Warm-up In this problem, we will implement two decoders using NOR2 and NND2 gates and inverters and then analyze them to see the effect of the number of inputs on the energy and number of gates. You can use both true and complement forms of the address signals as inputs. 12

13 a) Implement a 2 to 4 decoder by using only NOR2 gates and inverters. Draw the complete schematic and label the inputs and outputs. The truth table for the 2:4 decoder is shown below: Decode 0 0 y0 0 1 y1 1 0 y2 1 1 y3 Where the decode column lists the output which should be high (all other outputs should be low) s discussed in discussion, these decoders are implemented by taking the and of every possible combination of the inputs. This means that if we have n inputs, we will have 2 n outputs. Then, we can see that y0 =, y1 =, etc. Using De Morgan s Law, we know that we know that + =, which states tells us that we can implement the ND2 function with a single NOR2 gate, provided we have access to inverted inputs, which is exactly the case we are presented with. possible implementation is shown below: y0 y2 y1 y3 b) Implement a 3 to 8 decoder by using only NOR2 and NND2 gates. Draw the complete schematic and label the inputs and outputs. The truth table for this 3:8 decoder is shown below: Decode y y y y3 13

14 1 0 0 y y y y7 The decoder, like in part a), is implemented by taking the and of various input combinations. Using De Morgan s Law, each output can be expressed in the form of Y = = = +. Looking at this, as long as we re given both the normal and complement version of each input, we can implement each output with a single NOR2 and NND2 gate. Note that there are a myriad of ways to correctly implement this decoder, but two fairly straightforward implementations will be shown below. Implementation 1: y0 y1 y2 y3 y4 y5 y6 y7 14

15 Implementation 2: nother possible implementation takes note of the fact that each input uses the results of the 2:4 decoder to create a 3:8 decoder, to create a precoder. y0 y1 y2 y3 y4 y5 y6 y7 c) For this part of the problem you should ignore all the junction capacitors from the transistors and assume that each NOR2 and NND2 gate has 5fF and 4fF of input capacitance, respectively. How much energy is consumed by the above decoder from part b) every time one of the address inputs changes? Note that you shouldn t forget to include the energy consumed by the address inputs. The energy pulled out of the supply depends on the implementation. Here, we ll analyze the energy consumption in the two possible implementations shown above. The main equation we will need for this part is E = t V 2 DD, where t is the total capacitance charged by the supply. Implementation 1: In this implementation, or transitioning will result in 4 NND2 gates at the first level each having an input charged from 0 to 1. This will also cause the output of 2 NND2 gates to go from 0 to 1. This results in 2 NOR2 gates at the second level of logic each having an input charged from 0 to 1. Therefore, the total energy consumed when or transitions is: E = (4 4fF + 2 5fF) V 2 2 DD = 26fF V DD 15

16 When input transitions, 4 NOR2 gates at the second level will each have an input charge from 0 to 1. Therefore, the total energy consumed when transitions is: E = (4 5fF) V 2 2 DD = 20fF V DD Implementation 2: In this implementation, or transitioning will result in 2 NND2 gates at the first level each having an input charged from 0 to 1. Now, only 1 NND2 gate has its output go from 0 to 1. However, since each NND2 drives 2 NOR2 gates, this transition results in 2 NOR2 gates each having an input charged from 0 to 1. Therefore, the total energy consumed is: E = (2 4fF + 2 5fF) V 2 2 DD = 18fF V DD When input transitions, 4 NOR2 gates at the second level will each have an input charge from 0 to 1. Therefore, the total energy consumed when transitions is: E = (4 5fF) V 2 2 DD = 20fF V DD d) Now let s compare the energy consumption of the 3:8 decoder from part b) to a design that uses only NND2 gates and inverters. What is the maximum input capacitance of the inverter for which the NND2 and inverter only implementation has lower energy consumption than your implementation in part b)? nswer this question for the worst case energy consumption in either design, and use the same input capacitance numbers for the NOR2 and NND2 gates as in part c). gain, there are many possible implementations, but two implementations in a similar style to those in part b) will be shown. 16

17 Implementation 1: y0 y1 y0 y1 y0 y1 y0 y1 This implementation is very much in the same style as implementation 1 in part b) so the comparison will be done here relative to that implementation. In this implementation, or transitioning will result in 4 NND2 gates at the first level each having an input charge from 0 to 1. t the second level, this transition causes the output of 2 NND2 gates to transition from 0 to 1, charging up the inputs of 2 inverters. t the third level, two NND2 gates each have an input charged from 0 to 1, and at the fourth level, one inverter has its input charged from 0 to 1. The total energy consumed then is: E = 4 4fF + 2 ginv + 2 4fF + ginv V 2 2 DD = (24 ff + 3 ginv ) V DD transitioning causes 4 NND2 gates at the third logic level to each have an input charge from 0 to 1, and 1 inverter s input charge from 0 to 1 at the fourth logic level. The total energy consumed is then: E = 4 4fF + ginv V 2 2 DD = (16 ff + ginv ) V DD For all positive values of ginv, the energy consumption is dominated by the, switching. Thus, we can safely assume that this is the worst case for this design, 17

18 and compare it to the worst case for the implementation with NOR2 and NND2 gates. This happens to also be the case where or switches. 24 ff + 3 ginv V 2 DD = (26fF) 2 V DD 3 ginv = 2fF ginv = 2 3 ff Thus, for these two implementations, we can see that we require ginv 2 ff for 3 this design to have lower power consumption than implementation 1 in part b). Implementation 2: y0 y1 y2 y3 y4 y5 y6 y7 Similarly to the last part, this implementation is in the same style as implementation 2 in part b), as it has a precoder structure. ecause of this, this solution will compare implementation 2 in part b) to this implementation. In this implementation, or transitioning will result in 2 NND2 gates at the first level each having an input charge from 0 to 1. t the second level, this transition causes the output of 1 NND2 gate to transition from 0 to 1, charging up the input of 1 inverter. t the third level, two NND2 gates each have an input charged from 0 to 1, and at the fourth level, one inverter has its input charged from 0 to 1. The total energy consumed then is: 18

19 E = 2 4fF + ginv + 2 4fF + ginv V 2 2 DD = (16 ff + 2 ginv ) V DD transitioning causes 4 NND2 gates at the third logic level to each have an input charge from 0 to 1, and 1 inverter s input charge from 0 to 1 at the fourth logic level. The total energy consumed is then: E = 4 4fF + ginv V 2 2 DD = (16 ff + ginv ) V DD gain, we see that the worst case, for positive ginv, occurs for or transitioning. With implementation 2 in part b), the worst case actually occurs when transitions. We can set the energies in these two cases equal to find the critical ginv for which this design consumes more power than that of implementation 2 in part b). 16 ff + 2 ginv V 2 DD = (20fF) 2 V DD 2 ginv = 4fF ginv = 2fF Thus, for these two implementations, we can see that we require ginv 2fF for this design to have lower power consumption than implementation 2 in part b). 19

### UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #2 - Solutions EECS141 Due Thursday, September 10, 5pm, box in 240

### Elad Alon Homework #2 EECS141 Due Thursday, September 9, 5pm, box in 240 Cory

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #2 EECS141 Due Thursday, September 9, 5pm, box in 240 Cory PROBLEM

### UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #7 Solutions EECS141 PROBLEM 1: Logical Effort with Velocity Saturated

### VLSI Circuit Design (EEC0056) Exam

Mestrado Integrado em Engenharia Eletrotécnica e de omputadores VLSI ircuit esign (EE0056) Exam 205/6 4 th year, 2 nd sem. uration: 2:30 Open notes Note: The test has 5 questions for 200 points. Show all

### EE115C Digital Electronic Circuits Homework #4

EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors

### UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CAIFORNIA, BERKEEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #7 - Solutions EECS141 Due Thursday, October 22, 5pm, box in 240 Cory

### UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #2 EECS141 Due Thursday, September 9, 5pm, box in 240 Cory PROBLEM

### EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this

### Properties of CMOS Gates Snapshot

MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)

### 9/18/2008 GMU, ECE 680 Physical VLSI Design

ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design

### EEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW

### UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CLIFORNI, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad lon Homework #6 EECS141 Due Thursday, Oct. 15 @ 40 Cory Unless otherwise noted, you

### EE141Microelettronica. CMOS Logic

Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit

### Circuit A. Circuit B

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on November 19, 2006 by Karl Skucha (kskucha@eecs) Borivoje Nikolić Homework #9

### Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational

### CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed

### COMP 103. Lecture 16. Dynamic Logic

COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03

### UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #9 EECS141 PROBLEM 1: TIMING Consider the simple state machine shown

### Spiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp

2-7.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 2-7.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance

### CPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville

CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit

### Designing Information Devices and Systems II Fall 2017 Miki Lustig and Michel Maharbiz Homework 1. This homework is due September 5, 2017, at 11:59AM.

EECS 16 Designing Information Devices and Systems II Fall 017 Miki Lustig and Michel Maharbiz Homework 1 This homework is due September 5, 017, at 11:59M. 1. Fundamental Theorem of Solutions to Differential

### Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic

### CPE/EE 427, CPE 527 VLSI Design I Pass Transistor Logic. Review: CMOS Circuit Styles

PE/EE 427, PE 527 VLI Design I Pass Transistor Logic Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: MO ircuit

### Digital Integrated Circuits A Design Perspective

igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational

### Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]

Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an N-Switch, the

### EE115C Digital Electronic Circuits Homework #5

EE115C Digital Electronic Circuits Homework #5 Due Thursday, May 13, 6pm @ 56-147E EIV Problem 1 Elmore Delay Analysis Calculate the Elmore delay from node A to node B using the values for the resistors

### Homework Assignment #3 EE 477 Spring 2017 Professor Parker , -.. = 1.8 -, 345 = 0 -

Homework Assignment #3 EE 477 Spring 2017 Professor Parker Note:! " = \$ " % &' ( ) * ),! + = \$ + % &' (, *,, -.. = 1.8 -, 345 = 0 - Question 1: a) (8%) Define the terms V OHmin, V IHmin, V ILmax and V

### THE INVERTER. Inverter

THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)

### DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.

DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-604 yrpeng@uark.edu Pass Transistors We have assumed source is

### Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo

Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic

### Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power

- Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances

### UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Oldham Fall 1999

UNIVERSITY OF CLIFORNI College of Engineering Department of Electrical Engineering and Computer Sciences Professor Oldham Fall 1999 EECS 40 FINL EXM 13 December 1999 Name: Last, First Student ID: T: Kusuma

### EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University

EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar

### Power Dissipation. Where Does Power Go in CMOS?

Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit

### EECS 141: FALL 05 MIDTERM 1

University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION

### COMBINATIONAL LOGIC. Combinational Logic

COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-cmos Combinational vs. Sequential Logic In Logic

### EE241 - Spring 2000 Advanced Digital Integrated Circuits. Announcements

EE241 - Spring 2 Advanced Digital Integrated Circuits Lecture 11 Low Power-Low Energy Circuit Design Announcements Homework #2 due Friday, 3/3 by 5pm Midterm project reports due in two weeks - 3/7 by 5pm

### ECE251 VLSI System Design Spring Homework 1. Jinfeng Liu

ECE251 VLSI System Design Spring 2000 Homework 1 Jinfeng Liu 65547013 05/27/2000 Problem 1: Procedure of solutions 1. Determine β n β n = An * C L / t df Ar = 1 2n (1 n) ln (2(1 n) V 0) 0) Vdd(1 n) V [

### UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Deprtment of Electricl Engineering nd Computer Sciences Eld Alon Homework #3 Solutions EECS4 PROBLEM : CMOS Logic ) Implement the logic function

### CMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering

CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March

### UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engeerg Department of Electrical Engeerg and Computer Sciences Elad Alon Homework # Solutions EECS141 PROBLEM 1: VTC In this problem we will analyze the noise

### ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

### Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!

### Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor

### Objective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components

Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the

### 5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1

5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design

### Lecture 12 CMOS Delay & Transient Response

EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler

### Lecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010

EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1 Outline Power and Energy Dynamic Power Static Power 6.2 Power and Energy Power is drawn from a voltage source attached to the V DD

### ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

### Delay and Power Estimation

EEN454 Digital Integrated ircuit Design Delay and Power Estimation EEN 454 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation But make it easier to ask What

### Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded

### CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411

### Announcements. EE141- Spring 2003 Lecture 8. Power Inverter Chain

- Spring 2003 Lecture 8 Power Inverter Chain Announcements Homework 3 due today. Homework 4 will be posted later today. Special office hours from :30-3pm at BWRC (in lieu of Tuesday) Today s lecture Power

### EEE 421 VLSI Circuits

EEE 421 CMOS Properties Full rail-to-rail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady

### Lecture 7 Circuit Delay, Area and Power

Lecture 7 Circuit Delay, Area and Power lecture notes from S. Mitra Intro VLSI System course (EE271) Introduction to VLSI Systems 1 Circuits and Delay Introduction to VLSI Systems 2 Power, Delay and Area:

### ECE 342 Solid State Devices & Circuits 4. CMOS

ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

### Chapter 5. The Inverter. V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov Inverter

Chapter 5 The Inverter V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov.12 03 Objective of This Chapter Use Inverter to know basic CMOS Circuits Operations Watch for performance Index such as Speed (Delay calculation)

### Lecture 2: CMOS technology. Energy-aware computing

Energy-Aware Computing Lecture 2: CMOS technology Basic components Transistors Two types: NMOS, PMOS Wires (interconnect) Transistors as switches Gate Drain Source NMOS: When G is @ logic 1 (actually over

### EE115C Winter 2017 Digital Electronic Circuits. Lecture 6: Power Consumption

EE115C Winter 2017 Digital Electronic Circuits Lecture 6: Power Consumption Four Key Design Metrics for Digital ICs Cost of ICs Reliability Speed Power EE115C Winter 2017 2 Power and Energy Challenges

### Topic 4. The CMOS Inverter

Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Topic 4-1 Noise in Digital Integrated

### Digital Integrated Circuits

Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Short-circuit current The CMOS inverter :

EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay

### Floating Point Representation and Digital Logic. Lecture 11 CS301

Floating Point Representation and Digital Logic Lecture 11 CS301 Administrative Daily Review of today s lecture w Due tomorrow (10/4) at 8am Lab #3 due Friday (9/7) 1:29pm HW #5 assigned w Due Monday 10/8

### EEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced

### DC and Transient Responses (i.e. delay) (some comments on power too!)

DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02 - CMOS Transistor Theory & the Effects of Scaling

-Spring 2004 Digital Integrated ircuits Lecture 15 Logical Effort Pass Transistor Logic 1 dministrative Stuff First (short) project to be launched next Th. Overall span: 1 week Hardware lab this week Hw

### Dynamic operation 20

Dynamic operation 20 A simple model for the propagation delay Symmetric inverter (rise and fall delays are identical) otal capacitance is linear t p Minimum length devices R W C L t = 0.69R C = p W L 0.69

### Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: Two-Input NOR Gate (NOR2)

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 14: March 1, 2016 Combination Logic: Ratioed and Pass Logic Lecture Outline! CMOS Gates Review " CMOS Worst Case Analysis! Ratioed Logic Gates!

### EECS 312: Digital Integrated Circuits Midterm Exam 2 December 2010

Signature: EECS 312: Digital Integrated Circuits Midterm Exam 2 December 2010 obert Dick Show your work. Derivations are required for credit; end results are insufficient. Closed book. No electronic mental

### The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V

### ECE 342 Electronic Circuits. Lecture 34 CMOS Logic

ECE 34 Electronic Circuits Lecture 34 CMOS Logic Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 De Morgan s Law Digital Logic - Generalization ABC... ABC...

### EE141-Fall 2011 Digital Integrated Circuits

EE4-Fall 20 Digital Integrated Circuits Lecture 5 Memory decoders Administrative Stuff Homework #6 due today Project posted Phase due next Friday Project done in pairs 2 Last Lecture Last lecture Logical

### Lecture 8-1. Low Power Design

Lecture 8 Konstantinos Masselos Department of Electrical & Electronic Engineering Imperial College London URL: http://cas.ee.ic.ac.uk/~kostas E-mail: k.masselos@ic.ac.uk Lecture 8-1 Based on slides/material

### EE115C Digital Electronic Circuits Homework #6

Problem 1 Sizing of adder blocks Electrical Engineering Department Spring 2010 EE115C Digital Electronic Circuits Homework #6 Solution Figure 1: Mirror adder. Study the mirror adder cell (textbook, pages

### Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

### Next, we check the race condition to see if the circuit will work properly. Note that the minimum logic delay is a single sum.

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on May 1, 2003 by Dejan Markovic (dejan@eecs.berkeley.edu) Prof. Jan Rabaey EECS

### MOSFET and CMOS Gate. Copy Right by Wentai Liu

MOSFET and CMOS Gate CMOS Inverter DC Analysis - Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max

### The Physical Structure (NMOS)

The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two

### CPE100: Digital Logic Design I

Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Midterm01 Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Thursday Oct. 5 th In normal lecture (13:00-14:15)

### ENEE 359a Digital VLSI Design

SLIDE 1 ENEE 359a Digital VLSI Design Prof. blj@eng.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay s CSE477 slides

### E40M. Binary Numbers. M. Horowitz, J. Plummer, R. Howe 1

E40M Binary Numbers M. Horowitz, J. Plummer, R. Howe 1 Reading Chapter 5 in the reader A&L 5.6 M. Horowitz, J. Plummer, R. Howe 2 Useless Box Lab Project #2 Adding a computer to the Useless Box alows us

### EE241 - Spring 2001 Advanced Digital Integrated Circuits

EE241 - Spring 21 Advanced Digital Integrated Circuits Lecture 12 Low Power Design Self-Resetting Logic Signals are pulses, not levels 1 Self-Resetting Logic Sense-Amplifying Logic Matsui, JSSC 12/94 2

### CPE/EE 427, CPE 527 VLSI Design I L18: Circuit Families. Outline

CPE/EE 47, CPE 57 VLI Design I L8: Circuit Families Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe57-05f

### Based on slides/material by. Topic 3-4. Combinational Logic. Outline. The CMOS Inverter: A First Glance

ased on slides/material by Topic 3 J. Rabaey http://bwrc.eecs.berkeley.edu/lasses/icook/instructors.html Digital Integrated ircuits: Design Perspective, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html

### Lecture 4: DC & Transient Response

Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide

### EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University

EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time

### EE 330 Lecture 37. Digital Circuits. Other Logic Families. Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates)

EE 330 Lecture 37 Digital Circuits Other Logic Families Static Power Dissipation Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates) Review from Last Time Inverter

### ECE251. VLSI System Design

ECE251. VLSI System Design Project 4 SRAM Cell and Memory Array Operation Area Memory core 4661 mm 2 (256bit) Row Decoder 204.7 mm 2 Collumn Decoder Overall Design Predecoder 156.1 mm 2 Mux 629.2 mm 2

### Digital Integrated Circuits A Design Perspective

Designing ombinational Logic ircuits dapted from hapter 6 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 ombinational vs. Sequential Logic In

### MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences

MSSCHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences nalysis and Design of Digital Integrated Circuits (6.374) - Fall 2003 Quiz #1 Prof. nantha Chandrakasan Student

### Lecture 7: SPICE Simulation

Introduction to CMOS VLSI Design Lecture 7: SPICE Simulation David Harris Harvey Mudd College Spring 2004 Outline Introduction to SPICE DC Analysis Transient Analysis Subcircuits Optimization Power Measurement

### Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Total Power. Energy and Power Optimization. Worksheet Problem 1

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 20, 2018 Energy and Power Optimization, Design Space Exploration Lecture Outline! Energy and Power Optimization " Tradeoffs! Design

### CMOS Digital Integrated Circuits Lec 10 Combinational CMOS Logic Circuits

Lec 10 Combinational CMOS Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic circuit Out In Combinational Logic circuit Out State Combinational The output is determined only by

### EECS 141 F01 Lecture 17

EECS 4 F0 Lecture 7 With major inputs/improvements From Mary-Jane Irwin (Penn State) Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND

### EECS 151/251A Homework 5

EECS 151/251A Homework 5 Due Monday, March 5 th, 2018 Problem 1: Timing The data-path shown below is used in a simple processor. clk rd1 rd2 0 wr regfile 1 0 ALU REG 1 The elements used in the design have

### E40M Capacitors. M. Horowitz, J. Plummer, R. Howe

E40M Capacitors 1 Reading Reader: Chapter 6 Capacitance A & L: 9.1.1, 9.2.1 2 Why Are Capacitors Useful/Important? How do we design circuits that respond to certain frequencies? What determines how fast