UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

Transcription

1 UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Deprtment of Electricl Engineering nd Computer Sciences Eld Alon Homework #3 Solutions EECS4 PROBLEM : CMOS Logic ) Implement the logic function shown below with sttic CMOS gte. You cn ssume tht both the true nd complementry versions of input re vilble (e.g. nd re vilble simultneously). Expnd the logic function in our fmilir AND/OR form: Implementing this function in sttic CMOS: Vdd Vdd Vdd B A C B A B A C B C A Out B B B B A A A A Note tht there re mny other wys for this gte to be implemented (in prticulr mny implementtions tht shre one of the trnsistors for two logicl terms) ny correct implementtion will receive full credit. As n exmple, selfdul implementtion with mximum trnsistor shring is shown below:

2 b) Someone clims they cn build sttic AND gte with the circuit shown below. Wht is wrong with this prticulr implementtion? There re two problems with this gte. The first nd most significnt one is tht Out is only connected to one of the power supplies when A=. In other words, if A=0, the output will not be driven to one of the power supplies, which does not meet the definition of sttic gte. This cn be shown using the truth tble ( Z stnds for the output being undriven i.e., high impednce): A B Out 0 0 Z 0 Z 0 0 Wek

3 As lso indicted in the tble, the second problem is tht when A= nd B=, we will be pssing through n NMOS trnsistor. In other words, the output won t relly mke it ll the wy up to Vdd, but rther will get stuck t VddV TH. c) By dding just two more trnsistors to the circuit shown bove, fix the circuit so tht it will implement sttic AND gte. Note tht you re free to use both the true nd complement versions of the input signls (A nd B) to chieve this. In order to fix the first problem, we need to connect Out to welldefined stte when A=0. Since we re building n AND gte, we know tht when A=0 Out is lwys 0, so we cn simply dd n NMOS t the output with s the gte voltge. To fix the second problem, we need to mke sure we hve PMOS pulling the output up when A=B=. Like we hd discussed in lecture, we cn build switch tht psses both s nd 0 s by plcing PMOS in prllel with n NMOS nd driving it with the complementry signl t the gte, which in this cse is lso. With these two fixes, the circuit shown below does indeed implement sttic AND gte. PROBLEM 2: Simultion Exercise I In the following NAND2 gte, we will use the sme sizing for ll PMOS trnsistors in the PUN. Similrly, ll the NMOS trnsistors in the PDN lso hve the sme size. We will lso define the NAND2 s β rtio s the rtio between the width of the PMOS trnsistors nd the NMOS trnsistors i.e., β = W p /W n. In this problem we will explore how chnging β impcts vrious design metrics by using HSPICE. You should mke the NMOS trnsistor µm wide, nd lter the width of the PMOS trnsistor to chnge the NAND2 s β rtio. The chnnel lengths of both the NMOS nd PMOS trnsistors should be fixed t 0.09µm. This is good chnce to explore HSPICE nd use some of its builtin functionlity to mke this problem esier. (Hint: you ll wnt to sweep trnsistor prmeters nd use.measure sttements. An exmple will be shown in discussion session.)

4 ) Plot VIL nd VIH of the NAND2 gte versus the β rtio. In order to mesure VIL nd VIH, you should ssume tht the B input is set to Vdd nd then sweep the A input from 0 to Vdd to trce out the VTC. The reltionship between VIL/VIH nd β rtio is plotted below. HSPICE deck: * HW3 Problem 2: Simultion Exercise I * Prt ).LIB '/home/ff/ee4/models/gpdk090_mos.sp' TT_sv.PARAM bet=2.param high=.2.param stepsize=0.0.subckt nnd2 b out vdd gnd Mp out vdd vdd gpdk090_pmosv w='bet*u' l=90n

5 Mp2 out b vdd vdd gpdk090_pmosv w='bet*u' l=90n Mn2 out int gnd gpdk090_nmosv w=u l=90n Mn int b gnd gnd gpdk090_nmosv w=u l=90n.ends Xdut A B OUT vdd 0 nnd2 Xdum Ad Bd OUTd vdd 0 nnd2 Vdd vdd 0 high VA A 0 high VB B 0 high VBd Bd 0 high Vn Ad A stepsize.options post=2 nomod.op.dc VA 0 high stepsize SWEEP bet 4 0..MEASURE DC vil FIND v(a) WHEN PAR('(v(OUTd)v(OUT))/stepSize')= CROSS=.MEASURE DC vih FIND v(a) WHEN PAR('(v(OUTd)v(OUT))/stepSize')= CROSS=2.END b) Sweep β nd plot the hightolow trnsition dely, the lowtohigh trnsition dely, nd the verge dely of the second NAND2 in the fnout of 4 NAND2 chin shown below. Wht β would you choose to minimize the verge dely? The verge dely, hightolow dely, nd lowtohigh dely vs. β re shown below. The β tht minimizes the verge dely is pproximtely.

6 HSPICE deck: * HW3 Problem 2: Simultion Exercise I * Prt b).lib '/home/ff/ee4/models/gpdk090_mos.sp' TT_sv.PARAM bet=2.param high=.2.subckt nnd2 b out vdd gnd Mp out vdd vdd gpdk090_pmosv w='bet*u' l=90n Mp2 out b vdd vdd gpdk090_pmosv w='bet*u' l=90n Mn2 out int gnd gpdk090_nmosv w=u l=90n Mn int b gnd gnd gpdk090_nmosv w=u l=90n.ends X in bhigh n vdd 0 nnd2 M= X2 n bhigh n2 vdd 0 nnd2 M=4 *Device under test X3 n2 bhigh n3 vdd 0 nnd2 M=6 X4 n3 bhigh n4 vdd 0 nnd2 M=64 Vdd vdd 0 high Vin in 0 PULSE 0 high 00p 00p 00p 300p 800p

7 VB bhigh 0 high.options post=2 nomod.options ccurte.op.tran 0.0p 0n SWEEP bet * Low to high trnsition dely.measure TRAN tplh TRIG v(n) VAL='high/2' FALL= TARG v(n2) VAL='high/2' RISE= * High to low trnsition dely.measure TRAN tphl TRIG v(n) VAL='high/2' RISE= TARG v(n2) VAL='high/2' FALL= * Averge dely.measure tpavg PARAM='(tpLH+tpHL)/2'.END PROBLEM 3: Simultion Exercise II ) Shown below is n inverter with W p /W n = 2µm/µm with lod cpcitnce of 5fF. Assume tht in our technology the gte cpcitnce C G = 2fF/µm nd tht the junction cpcitnce C D =.6fF/µm. Clculte the energy drwn from V dd (=.2V) when the input trnsitions from high to low. Since the input is chnging from to 0, the output will experience 0 to trnsition. The energy drwn from the supply is to only chrge the lod cpcitnce nd the junction cpcitnce of the inverter. Therefore, we hve:

8 b) Using 0ps fll time slope for the input step, simulte the energy drwn from Vdd in HSPICE. How close is this vlue compred to prt )? To ensure consistent results with the solutions, you should use the flling edge of the pulse wveform shown below s the input step. The pulse hs ns period nd you should mesure the verge energy during the hlf cycle (500ps) tht strts t the flling edge. The simultion result with 0ps fll time is fj, which is quite close to the estimted vlue of fj. The HSPICE deck is shown t the end of c). c) [BONUS] Using 00ps fll time slope for the input step, simulte the energy drwn from Vdd in HSPICE. Is it lrger or smller thn the result you got in b)? Why might it be lrger or smller thn prt b)? If we chnge the fll time from 0ps to 00ps, we get simulted energy of 33.9fJ. This is bout 0% lrger thn wht we got in b). The increse in energy is minly due to the fct tht with slower input slope, the mount of time where both the NMOS nd PMOS trnsistors re both on (nd hence drw current directly from Vdd to Gnd) is lrger thn when the input mkes very shrp step. The current tht flows directly through both trnsistors is clled shortcircuit current, nd results in incresed energy over the previous cse. HSPICE deck: * HW3 Problem 3: Simultion Exercise II * Prt b) & c).lib '/home/ff/ee4/models/gpdk090_mos.sp' TT_sv.PARAM high=.2.param trf=0p.subckt inv in out vdd gnd Mp out in vdd vdd gpdk090_pmosv w=2u l=90n Mn out in gnd gnd gpdk090_nmosv w=u l=90n.ends Xinv in out vdd 0 inv

9 CL out 0 5f Vdd vdd 0 high Vin in 0 PULSE 0 high 00p trf trf '500ptrf' n.options post=2 nomod.options ccurte.op.tran 0.0p 2n * Mesure verge current drwn from supply in cycle.measure TRAN iavg AVG i(vdd) FROM 600p TO.n * Averge energy drwn from supply.measure TRAN eavg PARAM='high*iAVG*500p'.ALTER.PARAM trf=00p.end

10 PROBLEM 4: Decoder Wrmup In this problem you should ssume tht you re given predesigned set of gtes tht consists of only NOR2, NAND2, nd n inverter. For this problem you must choose from this set of gtes to design 3:8 decoder. You cn ssume tht both the true nd complement ddress input signls re vilble to you. ) Drw n implementtion of 3:8 decoder using only NAND2 nd/or inverters. There re mny wys to implement the decoder. The two most strightforwrd wys re shown below, but ny resonble solution will receive full credit. Possible solution I: b7 b6 b5 b4 b3 b2 b b0

11 Possible solution II:

12 b) Drw n implementtion of 3:8 decoder using only NOR2 nd/or inverters. There re gin mny possible implementtions. One strightforwrd solution is to replce ech NAND2 gte followed by n inverter with NOR2 gte whose input polrities hve been flipped. Implementtion I: b7 b6 b5 b4 b3 b2 b b0

13 Implementtion II: c) For this prt of the problem you should ignore ll the junction cpcitors from the trnsistors nd ssume tht ech NAND2 hs 4fF input cpcitnce, while ech inverter hs 3fF input cpcitnce. How much energy is pulled out of the power supply of the decoder from prt ) every time one of the ddress inputs chnges? Don t forget to include the energy used by the gtes tht drive the ddress inputs of the decoder. For implementtion I of prt ), if 2 or trnsitions from low to high, t the first level of logic there re 4 NAND2 gtes whose inputs re chrged from 0 to. At the second level of logic, there re 2 inverters whose inputs re chrged. At the third level 2 NAND2 gtes re chrged, nd t the lst level of logic there is inverter whose input is chrged. Therefore, the totl energy is

14 If 0 rises the outputs from the first two levels of logic do not chnge, while the third level hs 4 NAND2 gtes whose inputs re chrged, nd the input to inverter in the finl level of logic rises. Therefore, the totl energy is:

15 For implementtion II of prt ), if 2 or trnsitions from low to high, t the first level of logic there re 2 NAND2 gtes whose inputs re chrged from 0 to. At the second level of logic, there is inverter whose input is chrged. At the third level 2 NAND2 gtes re chrged, nd t the lst level of logic there is inverter whose input is chrged. Therefore, the totl energy is :

16 If 0 rises the outputs from the first two levels of logic do not chnge, while the third level hs 4 NAND2 gtes whose inputs re chrged, nd the input to inverter in the finl level of logic rises. Therefore, the totl energy is:

17 b7 b6 b5 b4 b3 b2 b b0 d) In order to mke the energy consumed by the implementtion from b) the sme or less thn tht of prt ), wht is the mximum input cpcitnce ech NOR2 gte is llowed to hve? To find the mximum input cpcitnce, we need to first clculte the energy consumption in b). We cn ssume the input cpcitnce of ech NOR2 gte is. For implementtion I: If 2 or trnsitions from low to high, similr to ), we hve 4 NOR2 gtes to chrge t the first level of logic, 2 inverters to chrge t the second level nd 2 NOR2 gtes to chrge t the third level. The totl energy consumption is:

18 If 0 trnsitions, only 4 NOR2 gtes t the third level will be chrged. Therefore, the totl energy is:

19 To mke the NOR2 implementtion less power hungry, we need to gurntee tht: From which we get the NOR2 gte is.. Tht is, the mximum input cpcitnce for Implementtion II: If 2 or trnsitions from low to high, we hve 2 NOR2 gtes tht will be chrged t the first level of logic, inverter is chrged t the second level, nd 2 NOR2s re chrged t the third level. The overll energy consumption is therefore:

20 If 0 trnsitions, 4 NOR2 gtes t the third level will be chrged, with energy consumption

21 b7 b6 b5 b4 b3 b2 b b0 To mke the NOR2 implementtion II less power hungry thn the NAND2 implementtion II, we need to gurntee tht: From which we get. Tht is, the mximum input cpcitnce for the NOR2 gte is.