UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

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1 UNIVERSITY OF CLIFORNI, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad lon Homework #6 EECS141 Due Thursday, Oct. 40 Cory Unless otherwise noted, you should assume the following parameters for all of the problems in this homework: NMOS: L=100nm, V Tn = 0.5V, µ n = 350 cm /(V s), C ox = 0.95 µf/cm, v sat = 1e7 cm/s, λ = 0 PMOS: L=100nm, V Tp = 0.5V, µ p = 175 cm /(V s), C ox = 0.65 µf/cm, v sat = 1e7 cm/s, λ = 0 PROBLEM 1: RC Model Extraction In this problem, you will use the built-in optimization tool in HSPICE to do device characterization. The discussion sessions will cover the syntax needed to perform optimizations in HSPICE, so be sure to attend if you have not used this HSPICE feature before. a) Using the calibration procedure described in the lecture (i.e. Lecture #11 page 1-3), find the linear drain capacitance per µm of width for an NMOS transistor with 100nm channel length. Repeat for a PMOS transistor with 100nm channel length. We can use the following setup for NMOS drain capacitance extraction: The NMOS drain capacitance that matches the average delay is ~0.7617fF/µm. Similarly, we can extract the drain capacitance for PMOS as shown on the next page:

2 The PMOS drain capacitance that matches the average delay is ~ ff/µm. SPICE DECK: * EE141 HW6 P1 a).lib '/home/ff/ee141/models/gpdk090_mos.sp' TT_s1v.PRM Cpermicron=optrange(f, 0.5f, 5f) *Drain capacitance per micron width.model optmod opt itropt=50 * Inverter SUBCKT definition subckt inv vh vl in out M0 out in vh vh gpdk090_pmos1v L=100n W=u M1 out in vl vl gpdk090_nmos1v L=100n W=1u.ENDS * Voltage source VDD vdd 0 1. * Input Stimulus Vin in 0 PULSE ps 10ps 10ps 1ns ns * Inverter Chain for calibration X1c vdd 0 in out1c inv M=1 Xc vdd 0 out1c outc inv M=4 Cc outc 0 'Cpermicron*48' * Equivalent linear cap * Inverter Chain with MOS drain as load X1t vdd 0 in out1t inv M=1 Xt vdd 0 out1t outt inv M=4 MdutN outt gnd gnd gnd gpdk090_nmos1v L=100n W=1u M=48 *MdutP outt vdd vdd vdd gpdk090_pmos1v L=100n W=1u M=48 * Measure the calibration chain.mesure TRN CLtpLH TRIG v(out1c) VL=0.6 FLL= TRG v(outc) VL=0.6 RISE=.MESURE TRN CLtpHL TRIG v(out1c) VL=0.6 RISE= TRG v(outc) VL=0.6 FLL= * Measure the chain with transitor drain as load.mesure TRN tplh TRIG v(out1t) VL=0.6 FLL= TRG v(outt) VL=0.6 RISE=.MESURE TRN tphl TRIG v(out1t) VL=0.6 RISE= TRG v(outt) VL=0.6 FLL=

3 * Optimization GOL.MESURE errorr PRM='abs(tpHL-CLtpHL)' GOL=0.MESURE errorf PRM='abs(tpLH-CLtpLH)' GOL=0.OPTIONS accurate.trn 0.01p 5n SWEEP OPTIMIZE=optrange RESULTS=errorR,errorF MODEL=optmod.MESURE Cdpermicro param='cpermicron'.end b) Now instead of finding the linear drain capacitance for the same NMOS transistor that best matches the delay, find the linear drain capacitance per µm that best matches the power drawn from the inverter supply. Repeat this for a PMOS transistor. The simulation setup is very similar to that in part a). The only difference is that instead of matching the delay of the driving inverters, we need to match the dynamic power drawn from their supplies. That is to say, we need to match the power drawn from VDDc and VDDt. um VDDc 1x 4x 1x = 1um in 1x VDDt 4x Cc M dutn Slope Control The extracted NMOS drain capacitance is ~ ff/µm. The extracted PMOS drain capacitance is ~ fF/µm.

4 SPICE DECK: * EE141 HW6 P1 b).lib '/home/ff/ee141/models/gpdk090_mos.sp' TT_s1v.PRM Cpermicron=optrange(f, 0.5f, 5f).MODEL optmod opt itropt=50 * Inverter SUBCKT definition.subckt inv vh vl in out M0 out in vh vh gpdk090_pmos1v L=100n W=u M1 out in vl vl gpdk090_nmos1v L=100n W=1u.ENDS * Voltage source VDD vdd 0 1. VDDC vddc 0 1. VDDT vddt 0 1. * Input Stimulus Vin in 0 PULSE ps 10ps 10ps 1ns ns * Inverter Chain for calibration X1c vdd 0 in out1c inv M=1 Xc vddc 0 out1c outc inv M=4 Cc outc 0 'Cpermicron*48' * Equivalent linear cap * Inverter Chain with MOS drain as load X1t vdd 0 in out1t inv M=1 Xt vddt 0 out1t outt inv M=4 MdutN outt gnd gnd gnd gpdk090_nmos1v L=100n W=1u M=48 *MdutP outt vdd vdd vdd gpdk090_pmos1v L=100n W=1u M=48 * Measure the calibration chain.mesure TRN ivgchain VG i(vddc) FROM 1.1n TO 3.1n.MESURE TRN pvgchain PRM='-1.*iVGchain' * Measure the chain with transitor drain as load.mesure TRN ivgdut VG i(vddt) FROM 1.1n TO 3.1n.MESURE TRN pvgdut PRM='-1.*iVGdut' * Optimization GOL.measure errorr param='abs(pvgdut-pvgchain)' goal=0.options accurate.trn 0.01p 5n SWEEP OPTIMIZE=optrange RESULTS=errorR MODEL=optmod.MESURE Cdpermicro param='cpermicron'.end c) Using the velocity saturation model, analytically estimate the best-fit for delay resistance/square R sq of both NMOS and PMOS transistors as a function of the supply voltage V DD. Plot your results for V DD ranging from 0.5V 1.V.

5 First we can use the velocity saturated model to find the I DST for both the NMOS and PMOS transistors: υstn ξ L= L, IDN = W υ C µ cn NMOS STN OXN N υstp ξ L= L, IDP = W υ C µ cp PMOS STP OXP P ( VDD VTN ) ( DD TN ) + ( VDD VTP ) ( ) + ξ V V ξ L DD TP cp cn V V L For the delay model, we can treat the delay of the NMOS/PMOS as discharging/charging a load capacitance with a VDD/ voltage swing (lecture #11 page 9). Therefore the delay for the high-to-low and low-to-high transitions can be approximated as: VDD VDD tphl = CL, tplh = CL I I DN DP Note that this expression isn t entirely correct since it doesn t directly include the slope effect. However, setting λ=0 has the effect of underestimating the drain current, and the two effects roughly cancel each other out. more careful extraction of the device parameters (see e.g. HW#5 from EE141 Fall 008) including λ and the slope effect leads would lead to nearly identical numerical results. (Note that if you included slope effect using the given parameters and hence your analysis did not match the simulations, you will still receive full credit on the problem.) If we take into account the effect of input slopes (i.e. ignoring the ln() coefficient), we can also express the RC model delay as: L L tphl = RNsq CL, tplh = RPsq CL W W N P Therefore, we can find the equivalent resistance/square for the NMOS and PMOS to be: VDD WN VDD WP RNsq =, RPsq = I L I L DN DP Plotting the resistance/square for NMOS and PMOS vs. VDD curves:

6 d) Now using HSPICE, extract the best-fit for delay resistance/square R sq of both NMOS and PMOS transistors for V DD =0.5V, 0.75V, 1V and 1.V. Plot the simulated values on the same plot you created in part c), and comment on how well your analytical estimates match the simulations. The resistance/square R sq of both the NMOS and PMOS can be found using the following setup: L L Since t = phl RNsq ( CD, inv CL ) and tplh RPsq ( CD, inv CL) W + = N W +, by tuning the load P capacitance, we can extract both effective resistances by measuring the slope of the t phl and t plh vs. C L curves. We can then repeat this procedure for different voltages. The simulated and calculated R sq values for V DD =0.5V, 0.75V, 1V and 1.V are listed below. They are also plotted on the same plot: Rsqn (kohm/sq) Rsqp(kOhm/sq) Simulated Calculated Simulated Calculated 1.V V V V

7 We can see that the simulated value matches very well with the calculation: the worst case error across the entire voltage range is 4.44% for Rsqn and.88% for Rsqp. SPICE DECK: * EE141 HW6 P1 d).lib '/home/ff/ee141/models/gpdk090_mos.sp' TT_s1v.PRM cl=0.prm vhigh=1. * Inverter SUBCKT definition.subckt inv vh vl in out M0 out in vh vh gpdk090_pmos1v L=100n W=u M1 out in vl vl gpdk090_nmos1v L=100n W=1u.ENDS * Voltage source VDD vdd 0 vhigh * Input Stimulus Vino in0 0 PULSE 0 vhigh 1ps 10ps 10ps 1ns ns * Inverter Chain to model Xs1 vdd 0 in0 inn inv M=1 Xs vdd 0 in0 inp inv M=1 Xn vdd 0 inn outn inv M=4 Xp vdd 0 inp outp inv M=4 Cln outn 0 cl

8 Clp outp 0 cl * Measure the Inverter Chain.measure TRN tphl TRIG v(inn) VL='vhigh/' RISE=1 TRG v(outn) VL='vhigh/' FLL=1.measure TRN tplh TRIG v(inp) VL='vhigh/' FLL=1 TRG v(outp) VL='vhigh/' RISE=1.options accurate.tran 0.01p n SWEEP cl 10f 50f 1f.LTER.PRM vhigh=1.lter.prm vhigh=0.75.lter.prm vhigh=0.5.end e) For an unloaded inverter (i.e., an inverter that does not have any explicit capacitance added to its output), plot the energy pulled out of the power supply on every 0 to 1 transition vs. the average delay of the inverter. Both the energy and delay should be calculated analytically for VDD = 0.5V, 0.75V, 1V, and 1.V using your results from parts a), b) and d). The size of the inverter you use should be Wn = 1µm, Wp = µm, and Ln=Lp=100nm. n unloaded inverter drives only its own junction capacitance. Since we are interested in energy, the linear drain capacitance values that we use values for both the PMOS and the NMOS transistors should be those that were extracted by matching power i.e., the results from part b). Using these values, we can compute energy as follows: V DD (V) C D,inv (ff) E dyn = C D,inv V DD (fj) Where C D,inv =C DN +C DP µm. Similarly, to calculate the delay, we need to find the junction capacitance with delay matching. Using the results from part a) we can get the drain capacitances for both NMOS and PMOS. Together with the result in d), we get: R Psq V DD (V) C D,inv (ff) R Nsq t pavg (ps) (ohm/sq) (ohm/sq)

9 L L Where tpavg = ( RNsq + RPsq ) CD, inv WN WP In the calculations above, we ignored the fact that drain capacitance actually also varies with supply voltage. To include this effect, we can re-run simulations with different V DD for part a) and b) and get different C D,inv for dynamic energy and delay calculations. The results are shown below. For energy calculation: V DD (V) C DN (ff/um) C DP (ff/um) C D,inv (ff) E dyn = C D,inv V DD (fj) For delay calculation: V DD (V) C DN (ff/um) C DP (ff/um) C D,inv (ff) RNsq RPsq t pavg (ps) (ohm/sq) (ohm/sq) L L Where tpavg = ( RNsq + RPsq ) CD, inv WN WP Note however that the total drain capacitance C D,inv doesn t vary much with the supply voltage, so even if we ignore C D,inv s dependence on V DD we will still get pretty accurate results. We can also show this by plotting the ED curves for these two cases as shown below:

10 PROBLEM : Transistor Capacitance and I-V Curves a) For this problem, you should assume that the total gate capacitance of a minimum length transistor follows the curve shown below (all of the transistors in this problem are minimum length). lthough in reality this total gate capacitance is divided between all of the other terminals (source, drain, and body), for simplicity we will assume that all of the gate capacitance goes to the source of the transistor. Now assume a µm/1µm sized target inverter is driven by another driving inverter as shown below. How much energy is pulled out of the previous inverter s supply voltage (i.e., V DDdrive, whose value is the same as V DD ) in order to charge in up to V DD? ll of your answers should be provided in terms of Cov, Cox, VT, and VDD. s the input of the driver goes from 1 to 0, the in signal changes from 0 to 1". When in is between 0 and V TN, the NMOS transistor is in cutoff:

11 For the PMOS, the transistor is in cutoff when V DD -V T < in < V DD : (Note also that the PMOS is twice as wide as the NMOS, so its capacitance is also doubled.) The total capacitance is just the sum of the PMOS and NMOS capacitances: The total energy pulled out from the driver s supply during this transition is: [(6 ) (6 3 ) ( ) (6 ) ] E = C + C V + C + C V V V + C + C V V tot ov ox T ov ox DD T T ov ox T DD = + 6CovVDD 3 Cox ( VDD VT ) VDD

12 b) One of your colleagues suggests precharging the bitlines of your SRM design to V DD / instead of V DD in order to reduce the effective capacitance of the bitlines. Explain whether or not you would follow your colleague s suggestion and why. To understand whether this is a good suggestion or not, let s first revisit the structure of an SRM column: We can see that the the majority of bitline capacitance is actually from the junction capacitance of the access transistor of each SRM cell. If we lower the voltage on the drain of an NMOS transistor, the reverse bias on the drain junctions decreases in magnitude. This means that the effective capacitance would actually increase if we precharge the bitlines to V DD / instead of V DD. c) For this problem you should use the simplified capacitance model with CG = CD = ff/µm. Using the velocity saturated transistor model, estimate the delay of the levelshifter circuit shown below when the input In steps from 0 to 0.8V to Out falling with V DD = 1.V. (Hint: You can assume that Out_c retains its old value while Out is transitioning, and that both the PMOS and NMOS transistors operate in the velocity saturation region during the entire transition.) Since we can assume that Out_c retains its old value while Out is transitioning, we only need to consider the left half circuit to calculate delay.

13 lso, assuming that during the transition both the NMOS and PMOS operate in the saturation region, they can simply be modeled as two current sources either discharging or charging the capacitance at the Out node. The model for calculating the delay is therefore shown below: Vdd I DSTP Out Ctot = CGP + CDP + CDN I DSTN The total capacitance at the Out node is composed of the gate capacitance of the right half PMOS (C GP ), the drain capacitance of the left half PMOS (C DP ), and the drain capacitance of the pull-down NMOS (C DN ). The toal capacitance at node Out is therefore: Ctot = CGP + CDP + CDN = ( ff / µ m) 1( µ m) + ( ff / µ m) 1( µ m) + ( ff / µ m) ( µ m) = 8 ff Using the velocity saturated model, the NMOS current I DSTN is: 7 cm 1 10 υ STN ξcn L s = L= 100nm = V µ 350 cm / V s I PDN = W N υ C NMOS STN OXN = µ ( ) ( VGS VT ) ( ) + V V ξ L = ( µ m) cm s µ F cm 1e7 ( / ) 0.95 ( / ) GS T cn ( 0.8V 0.5V) ( 0.8V 0. 5V ) V Similarly, the PMOS current I DSTP is: 7 cm 1 10 υ STP ξcpl s = L= 100nm = 1.148V µ 175 cm / V s I PUP = W P υ PMOS STP OXP ( ) ( VGS VT ) ( ) + = 1( µ m) cm s µ F 1e7 ( / ) 0.65 ( / ) = µ Therefore, the net current flowing out of the capacitor is: C V V ξ L GS T cp cm ( 1.V 0.5V) ( 1.V 0.5V) V IDIS = IDSTN IDSTP = µ µ =3.173µ

14 The time needed to discharge the Out node from V DD to V DD / is therefore: CtotVDD 8fF 1.V tp = = 0.67 ps I 3.173µΑ DIS PROBLEM 3: Power and Delay Throughout this problem, you should ignore all the junction capacitances of transistors except those explicitly shown in the circuit. lso, you can ignore shoot-through current and assume the leakage current of the transistor is equal to, where and. Now consider the circuit shown below: a) Calculate the leakage current for all 4 possible states of the inputs and B. For each of the 4 different input patterns, different transistors will be in the ON or OFF states. i) =0, B=0: The inverter s NMOS, the pass-gate NMOS, and the pass-gate PMOS are all OFF and hence set the total leakage current:

15 I = I + I + I LEK, = 0, B= 0 LEK1 LEK LEK 3 50mV 50mV ( (1.5 5 mv )) m ( (1.5 5 mv )) µ m µ = 4µ e + 4µ e 0.1µ m 0.1µ m 50 mv µ m ( (1.5 5 mv )) + µ e 0.1µ m µ ii) =1, B=0: VDD OFF W=4µm I leak_total 0 OFF I W=µm VDD leak1 0 0 F W=µm W=µm C1=4 ff C=6 ff OFF W=1µm VDD The inverter PMOS, the pass-gate NMOS, and the pass-gate PMOS are OFF, but only the pull-up PMOS contributes to leakage current since the drain-source voltage across both the pass-gate transistors is zero. Therefore the total leakage current under this condition is:

16 50mV ( (1.5 5 mv )) 4µ m I LEK, = 1, B= 0 = ILEK1 = µ e µ 0. 1µ m iii) =0, B=1: The inverter NMOS, the pass-gate NMOS, and the output NMOS are all OFF, but only the pull-down NMOS and the output NMOS contribute to leakage current since the drainsource voltage across the pass-gate NMOS is zero. Therefore, the total leakage current under this condition is: ( 50 mv (1.5 5 )) ( 50 mv mv 1 m (1.5 5 mv )) m I = LEK, 0, B 1 I + µ µ = = LEK1 ILEK = 4µ e 4µ e 0.1µ m µ m 0.157µ

17 iv) =1, B=1: OFF µm OFF I leak1 µm F µm C1=4 ff OFF C=6 ff µm I leak_total µm The pull-up PMOS, the pass-gate NMOS, and the output NMOS are all OFF, but only the pull-up PMOS contributes to leakage current since the drain-source voltage across both the pass-gate NMOS and the output NMOS is zero. Therefore, the total leakage current under this condition is: 50mV 4µ m ( (1.5 5 mv )) I LEK, = 1, B= 1 = ILEK1 = µ e µ 0. 1µ m b) ssuming that the inputs and B are driven with the waveforms shown below (and that these waveforms repeat every ns), calculate the average dynamic power drawn from the supply. We can use Pavg _ dyn = Pavg _ dyn, C1 + Pavg _ dyn, C1 = αc1 f C1 VDD + αc f C VDD to find the average dynamic power for each cycle. To do this, we need to find the activity factor α for each capacitor. By inspection, we can see that C1will be charged every time the input has a high-to-low transition to turn the inverter PMOS on. Therefore, α C1 = since have two high-to-low transitions each ns cycle.

18 To calculate the activity factor for C, we need to look at the output waveform: ns 1 ns B F From the output waveform, we can see that there is only one low-to-high transition on node F each cycle. Hence, the activity factor for C is α =1. The total dynamic power is therefore: P = α f C1 V + α f C V avg _ dyn C1 DD C DD 1 1 = 4 ff (1. V) ff (1. V) ns ns = 53.8µ W C c) Calculate the average total power drawn from the supply with the same inputs shown in part b). Since we already found the average dynamic power from part b), we just need to find the average leakage power and add it to the average dynamic power, With the input waveforms shown in part b), each of the four possible input patterns to the gate occurs for ¼ of the cycle. Therefore, the average leakage current is just: I avg _ leak I + I + I + I = µ µ µ µ = 4 = 0.157µ LEK, = 0, B= 0 LEK, = 1, B= 0 LEK, = 0, B= 1 LEK, = 1, B= 1 and hence the average total power is:

19 P = P + P = P + I V avg _ total avg _ dyn avg _ leak avg _ dyn avg _ leak DD = 53.8µ W µ 1.V = µ W