UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

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1 UNIVERSITY OF CALIFORNIA, BERKELEY College of Engeerg Department of Electrical Engeerg and Computer Sciences Elad Alon Homework # Solutions EECS141 PROBLEM 1: VTC In this problem we will analyze the noise margs for a cha of gates. For this problem, V dd =.5V. Figure 1.b. is a VTC for all three of the verters Fig. 1.a. The VTC has four segments, with a transient region between the two flat regions that can be approximated with two second-order curves. Figure 1.a. Figure 1.b. a) Add the voltage sources to Figure 1.a. that you would use for modelg noise couplg to the put and output of gate M. You should arrange these voltage sources so that they would both impact the noise marg the same way (i.e., if the voltage source at the put decrease the noise marg, the voltage source at the output should also decrease the noise marg).

2 b) Determe the noise margs for gate M when noise couples only to its put. To fd the noise marg, we need to know V IL, V IH, V OL, and V OH for the verters. V OH and V OL are clear from the VTC: VOH = V, VOL = 0. 5V To fd V IL and V IH, we need to fd the unity-ga pots on the VTC. To fd these pots, we ll need the equations for the VTC the regions 0.75V V 1.5V and 1.5V V 1.75V. For 0.75V V 1.5V, knowg that the curve is second-order, that V out = V for V = 0.75V, and that the slope of the VTC is zero at V = 0.75V, we can write: ( ) V k V V V V out = 1( 0.75) To fd k 1, we just make use of the fact that we know that V out = 1.5V when V = 1.5V: 1.5 = k ( ) k = 1 1 Followg essentially the same procedure, for 1.5V V 1.75V: ( ) V V V V V out = ( 1.75) Now we can fd V IL and V IH :

3 d d ( ( V 0.75) ) dv ( ( V 1.75) ) Fally: dv = 1 V = 1V NM H =.0V 1.65V = 0.375V NM L = 1.0V 0.5V = 0.5V IL = 1 V = 1.65V IH c) The followg piecewise equation describes the VTC of a circuit created by an EE141 student. Is this a digital gate? Why or why not? As part of your answer, you should sketch the VTC of this gate. Vout =.5V.5V 4 V 0.5V.5V V 4( V V ) 0V ( ) 0.0V V < 0.5V 0.5V V < 1.0V 1.0V V < 1.5V 1.5V V <.0V.0V V <.5V This is deed a digital gate. Any noise that places the put with the noise margs of this VTC will be attenuated at the output. Note that there is a stable region of the VTC (between V =1V and V =1.5V) where noise is not attenuated.

4 However, as long as noise couplg to the gate is less than the noise marg, this will not affect the operation of the system. PROBLEM : DELAY Recall that we have defed the propagation delay t p as the time between the 50% transition pots of the put and output waveforms. In this problem, we will explore how the way you set up a simulation can affect the results you measure. Please turn a sgle spice deck that performs the simulations for parts b) through d). You can measure the delays either by usg.measure statements SPICE, or usg awaves. If you use awaves however, you should clude plots of your waveforms. Figure. a) Create a SPICE subcircuit for the verter shown Figure. Use the followg le your SPICE deck to obta the correct NMOS and PMOS transistor models:.lib '/home/ff/ee141/models/g5.mod' TT To help get you started, we have provided the followg example which demonstrates the creation and usage of subcircuits SPICE. The followg put creates an stance named X1 of the MYRC subcircuit, which consists of a 5kΩ resistor and 10fF capacitor parallel. X1 TOP BOTTOM MYRC.SUBCKT MYRC A B R1 A B 5k C1 A B 10f.ENDS.SUBCKT v vdd gnd out Mp out vdd vdd PMOS W=u L=0.4u Mn out gnd gnd NMOS W=1u L=0.4u.ENDS

5 b) Measure the average propagation delay of an verter drivg four copies of itself. Apply a step put to the first verter. Note: Use the M (Multiply) parameter the subcircuit stantiation to replicate the verter. (See part d) for the spice deck) t phl = 67.6ps, t plh = 90.0ps, t pavg = 78.8ps c) Now create a cha of three verters, each with a fanout of 4. Measure the average propagation delay of the middle verter the cha. (See part d) for the spice deck) t phl = 110.4ps, t plh = 13.7ps, t pavg = 117.0ps d) Fally, create a cha of 4 verters, each with a fanout of 4. Measure the average propagation delay across the second verter the cha.

6 t phl = 109.4ps, t plh = 119.9ps, t pavg = 114.6ps SPICE Deck: * Homework Problem.LIB '/home/ff/ee141/models/g5.mod' TT * Inverter SUBCKT Defition.SUBCKT v vdd gnd out Mp out vdd vdd PMOS W=u L=0.4u Mn out gnd gnd NMOS W=1u L=0.4u.ENDS * Voltage Sources V1 vdd 0.5V V vstep 0 PULSE 0V.5V 10p 0.1f 0.1f 10n 0n * Part B Xv1b vdd 0 vstep vout1b v M=1 Xvb vdd 0 vout1b voutb v M=4 * Part C Xv1c vdd 0 vstep vout1c v M=1 Xvc vdd 0 vout1c voutc v M=4 Xv3c vdd 0 voutc vout3c v M=16 * Part D Xv1d vdd 0 vstep vout1d v M=1 Xvd vdd 0 vout1d voutd v M=4 Xv3d vdd 0 voutd vout3d v M=16 Xv4d vdd 0 vout3d vout4d v M=64 * options.option post= nomod * analysis.tran 1PS 0NS * Part B Measurement.MEASURE TRAN tphlb TRIG V(vstep) VAL=1.5V RISE=1 TARG V(vout1b) VAL=1.5V FALL=1.MEASURE TRAN tplhb TRIG V(vstep) VAL=1.5V FALL=1 TARG V(vout1b) VAL=1.5V RISE=1.MEASURE TRAN tpavgb PARAM='(tpHLb+tpLHb)/' * Part C measurement.measure TRAN tphlc TRIG V(vout1c) VAL=1.5V RISE=1 TARG V(voutc) VAL=1.5V FALL=1.MEASURE TRAN tplhc TRIG V(vout1c) VAL=1.5V FALL=1 TARG V(voutc) VAL=1.5V RISE=1.MEASURE TRAN tpavgc PARAM='(tpHLc+tpLHc)/' * Part D measurement.measure TRAN tphld TRIG V(vout1d) VAL=1.5V RISE=1 TARG V(voutd) VAL=1.5V FALL=1.MEASURE TRAN tplhd TRIG V(vout1d) VAL=1.5V FALL=1 TARG V(voutd) VAL=1.5V RISE=1

7 .MEASURE TRAN tpavgd PARAM='(tpHLd+tpLHd)/'.END e) Note that the delays each one of these cases are different. Which one of these simulations is most realistic? Without an fitely large driver, the slew rate of any real on-chip signal will be fite. Therefore, the simulation setup part b) (where the propagation delay is measured with a step put) is not realistic. Notice that there was a small difference between the delays measured parts c) and d). In part c), the third verter (which is only there to act as a load for the verter whose delay we are measurg) has no load. In most real circuits, if a gate wasn t drivg any other gates, there would be no reason to have that gate the first place. Therefore, the simulation setup d) is more realistic. For those who are terested, the ma cause of the difference delay between c) and d) is that the put and output of any CMOS verter are capacitively coupled to each other. We will discuss this effect further later on the class, PROBLEM 3: ENERGY AND DELAY TRADEOFFS As we will discuss a later class lecture, one model for the propagation delay of a gate is proportional to k / ( ) del VDD VDD VT, where k del is a design/technology dependent parameter. In this problem, we will exame the tradeoffs between energy and delay usg this model of propagation delay, and our derivation of energy/operation CMOS gates from Lecture. For parts a), b), and c) of this problem, V T = 0.5V. a) Use this delay model to plot the energy versus delay of an verter for multiple values of V DD from 1V to.5v. You should normalize both the energy and delay to the nomal case where V DD =.5V (i.e., you do not need to know the value of k del or the verter s load capacitance) The energy/operation of a CMOS verter is CV DD, so the normalized energy is just V DD /(.5V).

8 b) Assumg that the capacitance loadg the verter s output is constant, calculate the amount of energy saved by makg the verter run 0% slower than nomal. kdelvddl /( VDDL VT ) k V /( V V ) del DDH DDH T = 1.0, V =.5V V / ( V V ) = / (.5 0.5) DDL DDL T V DDL.V DDH A V DD of.v yields a normalized energy of Therefore the energy saved is 1.1%. c) The energy delay product (EDP) is the product of energy/operation and delay. Create a plot of EDP versus relative delay (the delay and energy should once aga be normalized to those at V DD =.5V).

9 d) As a function of V T, what value of V DD mimizes the EDP of the verter? EDP k V /( V V ) C V del DD DD T L DD 3 dedp dv ( DD /( VDD VT ) ) = = 0 dv dv DD => V = 3 V DD T DD