Chapter 5. The Inverter. V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov Inverter


 Leona Walsh
 4 years ago
 Views:
Transcription
1 Chapter 5 The Inverter V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov.12 03
2 Objective of This Chapter Use Inverter to know basic CMOS Circuits Operations Watch for performance Index such as Speed (Delay calculation) Optimal Transistor Sizing for speed and Energy Power Consumption and Dissipation
3 The CMOS Inverter: A First Glance V DD V in V out C L
4 CMOS Inverter N Well V DD V DD PMOS PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND A=WxL
5 Two Inverters Share power and ground Abut cells V DD Connect in Metal Vin Vout Vout Vin
6 CMOS Inverter FirstOrder DC Analysis V DD V DD V out R p V out V OL = 0 V OH = V DD R n V in = V DD V in = 0
7 Delay Definitions (circuit speed) V in 50% t V out t phl t plh 90% 50% 10% t t f t r
8 CMOS Inverter: Transient Response V DD V DD R p t phl = f(r on.c L ) = 0.69 R on C L V out V out ln(2)=0.69 C L C L R n V in = 0 (a) Lowtohigh V in = V DD (b) Hightolow
9 Voltage Transfer Characteristic
10 PMOS Load Lines (Vdd = 2.5V in 0.25um CMOS Process) (Vt = 0.4V as shown in Table 32) V in = V DD + V GS, p I Dn I D, n = I D, p V out = V DD + V DS, p V out I Dp V in =0 I Dn I Dn V in =0 V in =1.5 V in =1.5 V GSp =1 V DS,p V DS,p V out V GSp =2.5 I V in D, n = V DD = I D, p + V GS, p V out = VDD + V DS, p
11 CMOS Inverter Load Characteristics I Dn V in = 0 V in = 2.5 PMOS V in = 0.5 V in = 2 NMOS V in = 1 V in = 1.5 V in = 1.5 V in = 1 V in = 2 V in = 1.5 V in = 1 V in = 0.5 V in = 2.5 V in = 0 V out
12 CMOS Inverter VTC V out NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat VM: Vin = Vout Switching Threshold Voltage NMOS res PMOS off V in Inverter
13 Switching Threshold as a Function of Transistor Ratio NMOS and PMOS are in Saturation Modes rvdd V M (when VDD >> V 1+ r DSAT For r = 1, and saturated velocity NMOS = 2 PMOS, Wp = 2Wn, V Tn, V Tp )
14 Switching Threshold as a Function of Transistor Ratio V (V) M W p /W n
15 Simulated VTC V out (V ) V in (V)
16 Impact of Process Variations 2.5 V out (V) Good NMOS Bad PMOS Nominal Good PMOS Bad NMOS V in (V) Good definition: Smaller oxide thickness, smaller L, higher W, smaller VT Inverter
17 Propagation Delay Inverter
18 CMOS Inverters V DD PMOS In Out 1.2 µm =2λ Metal1 Polysilicon NMOS GND
19 CMOS Inverter Propagation Delay V DD t phl = f(r on.c L ) = 0.69 R on C L V out V out ln(0.5) R on C L 1 V DD V in = V DD R on C L t
20 The Transistor as a Switch V GS V T S Ron D I D V GS = V DD R mid R 0 V DD /2 V DD V DS
21 The Transistor as a Switch 7 x R eq (O hm ) V DD (V )
22 The Transistor as a Switch Inverter
23 Transient Response 3 2.5? V out (V ) t p = 0.69 C L (R eqn +R eqp )/2 0.5 t plh t phl t (sec) x 1010
24 Delay (speed degrade) as a function of V DD t p (norm alized) when t phl V DD >> V Tn + V C 0.52 ( W / L) k V L ' n DSATn DSATn / V DD (V ) Similar to Rn curve! Sharp change at 2Vt
25 Design for Speed Performance Keep loading capacitances (CL) small Increase transistor ratio (W/L) (adding CMOS gain) Watch out for selfloading (for the previous stage)! Increase Vdd! Trade power/energy dissipation for performance!
26 Propagation delay v.s. Transistor size NMOStoPMOS Ratio: Symmetrical tphl and tplh PMOS is 2.5~3.5 wider than NMOS in width under same L Is there better propagation delay (tp), or a better NtoP ratio for overall tp can be found? Consider two identical cascaded CMOS inverters. The approximated load cap of the 1 st gate is C = ) + C L ( Cdp 1 + Cdn 1) + ( Cgp2 + Cgn2 W C C C, dp1 dn1 C, gp2 gn2 Is drain capacitance of PMOS and NMOS of 1 st stage Is gate capacitance of PMOS and NMOS of 2 nd stage Inverter
27 Propagation delay v.s. Transistor size Inverter When the PMOS device is made β times larger than the ( W / L) p NMOS β = Then CL becomes From (5.20), we have t p = eqp where γ = is the resistance ratio of equalsize NMOS and PMOS C = (1 ( W / L) n βc C βc dp1 dn1 and gp2 gn2 C = ) + C L ( 1+ β )( Cdn 1 + Cgn2 [(1 + β )( C + C ) + C ] dn1 ( R γ [ + β )( C + C ) + C ] R (1 + ) R R eqn dn1 gn2 gn2 W W eqn eqn + R eqp β β ) W
28 NMOS/PMOS ratio t p (sec) x tplh 1.9 tphl β Fig tp β opt β = W p /W n From Table 3.3 β= 31Κ/13Κ = 2.4 when β = opt = γ (1 + ( C C 1 + C 2 dn γ CW + C dn1 gn2 gn >> C Inverter ) W
29 Sizing Inverter
30 Inverter Chain In Out 1 f1 f2 C L If C L is given:  How many stages are needed to minimize the delay?  How to size the inverters? May need some additional constraints.
31 Notation Definition Unitsize NMOS Transistor: the NMOS with minimum Lmin and Wmin that meets the layout design rule (assume L is fixed, and W is varied) : Intrinsic Cap. of unitsize NMOS transistor C unit R unit C g R W : Channel resistance of unitsize NMOS transistor : Gate cap of unitsize NMOS transistor : Channel resistance of Wsized NMOS transistor : Selfloading or intrinsic cap of the inverter C int (diffusion cap and gatedrain overlap (Miller) cap)
32 Delay Minimum length devices, L=0.25µm Assume R P = 2R N and W P = 2W N =2W same pullup and pulldown currents approx. equal resistances R N = R P approx. equal rise t plh and fall t phl delays Analyze as an RC network Delay (D): t phl = (ln 2) R N C L t plh = (ln 2) R P C L 2W W W W unit unit R P = (2Runit ) Runit = RN = W P W N Load for the next stage: C = 3 gin R W W W unit (R of unit size NMOS) C unit Inverter
33 with Load Delay R P 2W R W W C L Load (C L ) t p = kr W C L k is a constant, equal to 0.69 Assumptions: no load zero delay t phl = (ln 2) R N C L t plh = (ln 2) R P C L Inverter
34 with Load and Para. Cap. C P = 2C unit Delay 2W W C int C L C N = C unit Load Delay = kr W (C int + C L ) = kr W C int + kr W C L = Delay (Internal) + Delay (Load) = kr W C int (1+ C L /C int ) Inverter
35 Delay Formula Delay ~ R W ( C + C ) int L t p = kr W C int ( 1 + C / C ) = t ( 1 + f / γ ) L int p 0 C int = γc g,in with γ 1 f = C L /C g,in : Effective fanout RW = R unit / W ; C int =WC unit t p0 = 0.69R unit C unit (Intrinsic or unloaded delay) Not function of transistor size!! Inverter
36 Apply to Inverter Chain In Out 1 2 N C L t p = t p1 + t p2 + + t pn C gin, j+ 1 t + pj ~ RunitCunit 1 γcgin, j N N C gin j t p = t p j = t, + 1, p0 1 +, Cgin N = j i C, + 1 = 1 = 1 γ gin, j C L
37 Optimal Tapering for Given N Delay equation has (N1) unknowns, C gin,2 ~ C gin,n Minimize the delay, find (N 1) partial derivatives Result: C gin,j+1 /C gin,j = C gin,j /C gin,j1 Size of each stage is the geometric mean of two neighbors C gin, j = Cgin, j 1C gin, j+ 1  Each stage has the same effective fanout (C out /C in )  Each stage has the same delay
38 Optimum Delay and Number of Stages When each stage is sized by f and has same effective fanout f N f = F = C Effective fanout of each stage: Minimum path delay p L f = N F t = Nt + p0 / Cgin,1 ( 1 /γ ) N F
39 Example In C 1 1 f f 2 Out C L = 8 C 1 C L /C 1 has to be evenly distributed across N = 3 stages: f = 3 8 = 2
40 Optimum Number of Stages Given load, C L and given input capacitance C in Find optimal sizing f t C p L = = F C Nt p0 in = f N C in with N = t ln ( ) p0 F / γ + 1 = + γ ln ln F F f f ln f γ ln f t f p = t p0 ln γ F ln f 1 γ 2 ln f f = 0 f = exp 1+ ( γ f ) For γ = 0, f = e, N = lnf
41 Optimum Effective Fanout f f ( γ f ) = exp 1+ f opt = 3.6 for γ=1, f opt = for γ=0
42 Normalized delay function of F t = Nt + p p0 ( 1 /γ ) N F
43 Buffer Design N f t p Without considering the internal capacitance Inverter
44 Power Dissipation Inverter
45 Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking diodes and transistors
46 Dynamic Power Consumption E VDD = 0 dvout 2 VDD( t) VDDdt = VDD CL dt = VDDCL dvout CLVDD dt = 0 0 i
47 Dynamic Power Dissipation Vdd Vin Vout C L Energy/transition = C L * V dd 2 Power = Energy/transition * f = C L * V dd 2 * f Not a function of transistor sizes! Need to reduce C L, V dd, and f to reduce power. E C 2 dvout CLVDD = ivdd( t) voutdt = CL voutdt = Energy in CL dt 2 0 0
48 Node Transition Activity and Power Consider switching a CMOS gate for N clock cycles E = C V N L 2 nn dd ( ) E N : the energy consumed for N clock cycles n(n): the number of 0>1 transition in N clock cycles P = lim avg N E N f N clk = nn lim ( ) C N N L V dd 2 fclk α 0 1 = nn lim ( ) N N P avg = α 0 1 C L V dd 2 fclk P AVG = ( α0 1 C L ) V 2 DD f CLK = C Eff V 2 DD f CLK ( C Eff : Effective Capacitance) Inverter
49 Switching Activity (Example 5.12) α0 1 = 2 / 8 = 0.25
50 Transistor Sizing for Minimum Energy Goal: Minimize Energy of whole circuit while maintaining the speed speed performance Design parameters: f and V DD tp tp,ref of referenced circuit with f=1 and Vdd =V ref In Out C g1 1 f C ext t t p p0 f = t p γ VDD V V DD TE F fγ ( F = C ext / C g 1) ( V TE = VT + VDSAT / 2)
51 Transistor Sizing (2) Transistor Sizing (2) Performance Constraint (γ=1) Vdd(f) Energy for single transition Energy ratio of the design and reference circuit ( ) ( ) = = = F f F f V V V V V V F f F f t t t t TE DD TE ref ref DD ref p p pref p = F F f V f V E E ref DD ref ) ( 2 [ ] ] ) )(1 1 1[( F f C V F f f C V E g DD g DD = = γ γ γ
52 Transistor Sizing (4) V DD =f(f) E/E ref =f(f) Required Supply Voltage Energy v.s. Sizing factor
53 Sizing factor for Speed and Energy Device sizing, combined with supply voltage reduction, is a very effective way in reducing energy consumption of a logic network. The gain can be up to 10 for large fanout. Oversizing beyond the optimal value comes at a hefty price in energy. Optimal size for energy is smaller than the optimal sizing for performance. For example, f(energy) = 3.53, f(performance) = 4.47= 20, for F=20
54 Short Circuit Currents (during switching) Vd d Vin Vout C L 0.15 I VDD (ma) V in (V)
55 Minimizing ShortCircuit Power Inverter
56 Neil Weste Textbook Inverter
57 Leakage Current Subthreshold current is one of most compelling issues in lowenergy circuit design!! P = I stat stat V DD
58 ReverseBiased Diode Leakage GATE p + p+ N +  V dd Reverse Leakage Current I DL = J S A JS = pa/µm2 at 25 deg C for 0.25µm CMOS JS doubles for every 9 deg C!
59 Subthreshold Leakage Component Inverter
60 Subthreshold Leakage Component (2) Inverter
61 Putting All Together P total = P dyna + P dp + P stat = ( C V L 2 DD + V DD I peak t s ) f V DD I leak In a typical CMOS circuits, the capacitive dissipation is by far the dominant factor. Leakage is ignorable at present, but will be major issue in deepsubmicron CMOS circuits.
62 Principles for Power Reduction Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question (0.6,, 0.9 V by 2010!) Reduce switching activity (at different levels) Reduce physical capacitance Device Sizing: for example, for F = 20 f opt (energy)=3.53, f opt (performance)=4.47.
63 PowerDelay Product (PDP) PDP = P t av p f = 1/(2t ) max L p CLV DD DD fmaxt p PDP = C V = PDP stands for the average energy consumed per switching event (0 1, 1 0)
64 EnergyDelay Product (EDP) Measure of both Performance and Energy EDP = PDP t C V α p = P av t 2 p = CLV 2 L DD t p, VTE = VT + VDSAT VDD VTE 2 DD t p / 2 (5.21) 2 3 CLVDD EDP = α, VDD, opt = 2( V V ) DD TE 3 2 V TE (5.59) The value of supply voltage that simultaneously optimizes performance and energy. For Vt=0.5V, the VDD is around 1V.
65 EnergyDelay Product (EDP) V V Tn Tp = 0.42V, = 0.4V, V V Dsat, n Dsat, p = 0.63V, V = 1V, V TE, n TE, p = 0.74V = 0.9V V TE = ( V TE, n + V TE, p ) / 2 = 0.8V V DD, opt = (3/ 2) 0.8V = 1.2V Note: Vdd for minimum EDP May not be the Optimal Vdd for a given design problem (speed contraint)
66 Summary Inverter Speed (delay), sizing, and power are discussed. The concept can be extended to complex gates in next chapter and future discussions Very important for the 1 st order guess/approximation for designers in considering power/area/speed of the target CMOS circuits
Digital Integrated Circuits 2nd Inverter
Digital Integrated Circuits The Inverter The CMOS Inverter V DD Analysis Inverter complex gate Cost V in V out complexity & Area Integrity and robustness C L Static behavior Performance Dynamic response
More informationAnnouncements. EE141 Spring 2003 Lecture 8. Power Inverter Chain
 Spring 2003 Lecture 8 Power Inverter Chain Announcements Homework 3 due today. Homework 4 will be posted later today. Special office hours from :303pm at BWRC (in lieu of Tuesday) Today s lecture Power
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full railtorail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power
More informationLecture 4: CMOS review & Dynamic Logic
Lecture 4: CMOS review & Dynamic Logic Reading: ch5, ch6 Overview CMOS basics Power and energy in CMOS Dynamic logic 1 CMOS Properties Full railtorail swing high noise margins Logic levels not dependent
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter
More informationAnnouncements. EE141 Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power
 Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 123pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances
More informationDynamic operation 20
Dynamic operation 20 A simple model for the propagation delay Symmetric inverter (rise and fall delays are identical) otal capacitance is linear t p Minimum length devices R W C L t = 0.69R C = p W L 0.69
More informationPower Dissipation. Where Does Power Go in CMOS?
Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationThe Inverter. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Inverter Revised from Digital Integrated Circuits, Jan M. Rabaey el, 2003 Propagation Delay CMOS
More informationLast Lecture. Power Dissipation CMOS Scaling. EECS 141 S02 Lecture 8
EECS 141 S02 Lecture 8 Power Dissipation CMOS Scaling Last Lecture CMOS Inverter loading Switching Performance Evaluation Design optimization Inverter Sizing 1 Today CMOS Inverter power dissipation» Dynamic»
More informationWhere Does Power Go in CMOS?
Power Dissipation Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 3  The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 6, 2017 Janakiraman, IITM
More informationCOMP 103. Lecture 10. Inverter Dynamics: The Quest for Performance. Section 5.4.2, What is this lecture+ about? PERFORMANCE
COMP 103 Lecture 10 Inverter Dynamics: The Quest for Performance Section 5.4.2, 5.4.3 [All lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated
More informationDigital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman
Digital Microelectronic Circuits (3611301 ) Presented by: Adam Teman Lecture 4: The CMOS Inverter 1 Last Lectures Moore s Law Terminology» Static Properties» Dynamic Properties» Power The MOSFET Transistor»
More information5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 111:3 Thursday, October 6, 6:38:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationDigital Integrated Circuits
Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Shortcircuit current The CMOS inverter :
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationCheck course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory
EE141 Fall 005 Lecture 6 MOS Capacitances, Propagation elay Important! Check course home page periodically for announcements Homework is due TOAY by 5pm In 40 Cory Homework 3 will be posted TOAY ue Thursday
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 3  The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 3, 2018 Janakiraman, IITM
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationEEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay
More informationToday s lecture. EE141 Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
 Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationMOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis  Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
More informationECE321 Electronics I
ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman ZarkeshHa Office: ECE Bldg. 30B Office hours: Tuesday :003:00PM or by appointment Email: payman@ece.unm.edu Slide: 1 CMOS
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 6: Power Consumption
EE115C Winter 2017 Digital Electronic Circuits Lecture 6: Power Consumption Four Key Design Metrics for Digital ICs Cost of ICs Reliability Speed Power EE115C Winter 2017 2 Power and Energy Challenges
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full railtorail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationEE115C Digital Electronic Circuits Homework #4
EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors
More informationB.Supmonchai July 5th, q Quantification of Design Metrics of an inverter. q Optimization of an inverter design. B.Supmonchai Why CMOS Inverter?
July 5th, 4 Goals of This Chapter Quantification of Design Metrics of an inverter Static (or SteadyState) Behavior Chapter 5 CMOS Inverter Boonchuay Supmonchai Integrated Design Application Research (IDAR)
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationTopic 4. The CMOS Inverter
Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ Email: p.cheung@ic.ac.uk Topic 41 Noise in Digital Integrated
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationLecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:308:00pm in 105 Northgate
EE4Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:308:00pm in 05 Northgate Exam is
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
1 Introduction to TransistorLevel Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationObjective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components
Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More information2007 Fall: Electronic Circuits 2 CHAPTER 10. DeogKyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits DeogKyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationVLSI Design and Simulation
VLSI Design and Simulation CMOS Inverters Topics Inverter VTC Noise Margin Static Load Inverters CMOS Inverter FirstOrder DC Analysis R p V OL = 0 V OH = R n =0 = CMOS Inverter: Transient Response R p
More informationEE241  Spring 2000 Advanced Digital Integrated Circuits. Announcements
EE241  Spring 2 Advanced Digital Integrated Circuits Lecture 11 Low PowerLow Energy Circuit Design Announcements Homework #2 due Friday, 3/3 by 5pm Midterm project reports due in two weeks  3/7 by 5pm
More informationECE 342 Solid State Devices & Circuits 4. CMOS
ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationEE115C Digital Electronic Circuits Homework #3
Electrical Engineering Department Spring 1 EE115C Digital Electronic Circuits Homework #3 Due Thursday, April, 6pm @ 56147E EIV Solution Problem 1 VTC and Inverter Analysis Figure 1a shows a standard
More informationEE5780 Advanced VLSI CAD
EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 13 The CMOS Inverter: dynamic behavior (delay) guntzel@inf.ufsc.br
More informationCHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS
CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational
More informationEECS 427 Lecture 11: Power and Energy Reading: EECS 427 F09 Lecture Reminders
EECS 47 Lecture 11: Power and Energy Reading: 5.55 [Adapted from Irwin and Narayanan] 1 Reminders CAD5 is due Wednesday 10/8 You can submit it by Thursday 10/9 at noon Lecture on 11/ will be taught by
More informationDC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575604 yrpeng@uark.edu Pass Transistors We have assumed source is
More informationImportant! EE141 Fall 2002 Lecture 5. CMOS Inverter MOS Transistor Model
 Fall 00 Lecture 5 CMO Inverter MO Transistor Model Important! Lab 3 this week You must show up in one of the lab sessions this week If you don t show up you will be dropped from the class» Unless you
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
More informationDC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02  CMOS Transistor Theory & the Effects of Scaling
More informationEEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW
More informationLecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010
EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1 Outline Power and Energy Dynamic Power Static Power 6.2 Power and Energy Power is drawn from a voltage source attached to the V DD
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More informationMiscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]
Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an NSwitch, the
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationEEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this
More informationCMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering
CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March
More informationECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model
ECE 34 Electronic Circuits Lecture 35 CMOS Delay Model Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 15, 2018 MOS Inverter: Dynamic Characteristics Penn ESE 570 Spring 2018 Khanna Lecture Outline! Inverter Power! Dynamic Characteristics
More informationHightoLow Propagation Delay t PHL
HightoLow Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (nchannel) immediately switches from cutoff to saturation; the pchannel pullup switches from triode to
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits  2 guntzel@inf.ufsc.br
More informationDigital Integrated Circuits
Digital Integrated ircuits YuZhuo Fu contact:fuyuzhuo@ic.sjtu.edu.cn Office location:47 room WeiDianZi building,no 800 Donghuan road,minhang amus Introduction Digital I 3.MOS Inverter Introduction Digital
More informationDigital Microelectronic Circuits ( )
Digital Microelectronic ircuits (36113021 ) Presented by: Dr. Alex Fish Lecture 5: Parasitic apacitance and Driving a Load 1 Motivation Thus far, we have learned how to model our essential building block,
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationEE141Fall Digital Integrated Circuits. Announcements. Lab #2 Mon., Lab #3 Fri. Homework #3 due Thursday. Homework #4 due next Thursday
EE4Fall 2000 Digital Integrated ircuits Lecture 6 Inverter Delay Optimization Announcements Lab #2 Mon., Lab #3 Fri. Homework #3 due Thursday Homework #4 due next Thursday 2 2 lass Material Last lecture
More informationInterconnect (2) Buffering Techniques. Logical Effort
Interconnect (2) Buffering Techniques. Logical Effort Lecture 14 18322 Fall 2002 Textbook: [Sections 4.2.1, 8.2.3] A few announcements! M1 is almost over: The checkoff is due today (by 9:30PM) Students
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time
More informationDesign for Manufacturability and Power Estimation. Physical issues verification (DSM)
Design for Manufacturability and Power Estimation Lecture 25 Alessandra Nardi Thanks to Prof. Jan Rabaey and Prof. K. Keutzer Physical issues verification (DSM) Interconnects Signal Integrity P/G integrity
More informationLecture 81. Low Power Design
Lecture 8 Konstantinos Masselos Department of Electrical & Electronic Engineering Imperial College London URL: http://cas.ee.ic.ac.uk/~kostas Email: k.masselos@ic.ac.uk Lecture 81 Based on slides/material
More informationCMOS Logic Gates. University of Connecticut 181
CMOS Logic Gates University of Connecticut 181 Basic CMOS Inverter Operation V IN P O N O pchannel enhancementtype MOSFET; V T < 0 nchannel enhancementtype MOSFET; V T > 0 If V IN 0, N O is cut off and
More informationASIC FPGA Chip hip Design Pow Po e w r e Di ssipation ssipa Mahdi Shabany
ASIC/FPGA Chip Design Power Di ssipation Mahdi Shabany Department tof Electrical ti lengineering i Sharif University of technology Outline Introduction o Dynamic Power Dissipation Static Power Dissipation
More informationCOMBINATIONAL LOGIC. Combinational Logic
COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino npcmos Combinational vs. Sequential Logic In Logic
More informationUniversity of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA
University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm 3 @
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationCARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
More informationPower Consumption in CMOS CONCORDIA VLSI DESIGN LAB
Power Consumption in CMOS 1 Power Dissipation in CMOS Two Components contribute to the power dissipation:» Static Power Dissipation Leakage current Subthreshold current» Dynamic Power Dissipation Short
More informationEE241  Spring 2001 Advanced Digital Integrated Circuits
EE241  Spring 21 Advanced Digital Integrated Circuits Lecture 12 Low Power Design SelfResetting Logic Signals are pulses, not levels 1 SelfResetting Logic SenseAmplifying Logic Matsui, JSSC 12/94 2
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.
More informationLecture 14  Digital Circuits (III) CMOS. April 1, 2003
6.12  Microelectronic Devices and Circuits  Spring 23 Lecture 141 Lecture 14  Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:
More informationLecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos IV Characteristics
More informationCOMP 103. Lecture 16. Dynamic Logic
COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03
More informationCSE493/593. Designing for Low Power
CSE493/593 Designing for Low Power Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.].1 Why Power Matters Packaging costs Power supply rail design Chip and system
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationInterconnect (2) Buffering Techniques.Transmission Lines. Lecture Fall 2003
Interconnect (2) Buffering Techniques.Transmission Lines Lecture 12 18322 Fall 2003 A few announcements Partners Lab Due Times Midterm 1 is nearly here Date: 10/14/02, time: 3:004:20PM, place: in class
More information