UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

Transcription

1 UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #2 - Solutions EECS141 Due Thursday, September 10, 5pm, box in 240 Cory PROBLEM 1: VTC In this problem we will analyze the noise margins for a chain of gates, Fig. 1a. The VTC has four segments, where the two curved regions can be approximated as quarter ellipses. Figure 1.a. Figure 1.b. a) Add the DC voltage sources to Figure 1.a. that you would use for modeling noise coupling to the input and output of gate M 2. You should arrange these voltage sources so that they would both impact the noise margin in the same way (i.e., if the voltage source at the input decreases the noise margin, the voltage source at the output should also decrease the noise margin). b) Determine the noise margins (as defined in lecture) for gate M 2 when noise couples only to its input. We want a numerical answer in Volts, not one based on just looking at the VTC.

2 To find the noise margin, we need to know V IL, V IH, V OL, and V OH for the inverters. V OH and V OL are clear from the VTC: V OH =1.2V,V OL = 0V To find V IL and V IH, we need to find the unity-gain points on the VTC. To find these points, we ll need the equations for the VTC in the regions 0.2V V in 0.6V and 0.6V V in 1.0V. For 0.2V V in 0.6V, knowing that the curve is part of an ellipse, we have: (x 0.2) 2 (y 0.4)2 + = To find the point of unity gain, we take the derivative (with respect to x) of the above equation while keeping in mind that at the point we are looking for y / x = 1. Therefore: 2 2 (x 0.2) (y 0.4) = 0, or y = 4x 0.4. Now we plug this linear equation into the equation for the ellipse and we get the solution: x 0.38.

3 So, V IL 0.38V. Since the second ellipse is actually just a quarter circle, finding its unity gain point is much easier. The quarter circle has a radius of 0.4V with its origin at (V in =1V, V out = 0.4V), and so the point on the -135 degree line away from the origin (which corresponds to the point with y / x = 1) is at: Finally: NM H = 1.2V 0.72V = 0.48V NM L = 0.38V 0.0V = 0.38V V IH = / V. c) Are the gates M4 and M5, whose VTCs are shown below in Figures 1.c and 1.d, digital? Is the cascade of the two gates (Figure 1.e) digital? Why or why not? As part of your answer, you should sketch the VTC of the cascade of the two gates. Figure 1.c. Figure 1.d. Figure 1.e. M5 is clearly a digital gate, but M4 is a little trickier. M4 is marginally digital: it has V OL = 0.6V, V OH = 1.2V, V IL = 0.6V, and V IH = 0.9V. In other words, the circuit has zero NM L, but nonetheless the gate is regenerative. Interestingly, despite the fact that both M4 and M5 are digital, the cascade of the two gates is not digital. The easiest way to prove this is to notice that for the VTC traced out by the cascade of the two gates, V M < V IL. This means that the output of a cascade of two such gates (where each gate is composed of the cascade of

4 M4 and M5) would always be 0 (no matter what the input is). The other way is to do this is to draw the butterfly curve of the two gates and notice that the only stable point is V out (M5) = 0V. d) [BONUS] If the cascade of M4 and M5 is digital, would any digital VTC for M5 also make the cascade digital? If the cascade is not digital, how would you modify M5 to make it digital? To make the cascade of M4 and M5 a digital gate, we need to ensure that output of the cascade reaches at least 0.9V instead of 0.6V. There are many possible ways to achieve this, and any valid solution will receive full credit. Interestingly, this can actually be achieved without changing the maximum gain of M5, but rather by shifting its V M up to 0.7V (as shown on Fig. 1.f.). The VTC of the cascade is shown on Fig. 1.g. Figure 1.f. Figure 1.g. PROBLEM 2: DELAY Recall that we have defined the propagation delay t p as the time between the 50% transition points of the input and output waveforms. In this problem, we will explore how the way you set up a simulation can affect the results you measure. Please turn in a single spice deck that performs the simulations for parts b) through d). You can measure the delays either by using.measure statements in SPICE, or using WaveView. However, if you use WaveView you should include plots of your waveforms.

5 a) Create a SPICE subcircuit for the inverter shown above. Use the following line in your SPICE deck to obtain the correct NMOS and PMOS transistor models:.lib '/home/ff/ee141/models/gpdk090_mos.sp' TT_s1v To help get you started, we have provided the following example which demonstrates the creation and usage of subcircuits in SPICE. The following input creates an instance named X1 of the MYRC subcircuit, which consists of a 5kΩ resistor and 10fF capacitor in parallel. X1 TOP BOTTOM MYRC.SUBCKT MYRC A B R1 A B 5k C1 A B 10f.ENDS * Inverter SUBCKT Definition.SUBCKT inv vdd gnd in out Mp out in vdd vdd gpdk090_pmos1v W=2u L=0.09u Mn out in gnd gnd gpdk090_nmos1v W=1u L=0.09u.ENDS (a)

6 (b) (c) (d) Figure 2 b) Measure the average propagation delay of an inverter driving four copies of itself (Fig. 2a). First apply a step input with a rise/fall time of 1 ns to the first inverter. Then, repeat this measurement with a rise/fall time of 1 ps. Note: Use the M (Multiply) parameter in the subcircuit instantiation to replicate the inverter. (See part e) for the spice deck) 1 ns: t phl = 46.8ps, t plh = 96.1ps, t pavg = 71.4ps 1 ps: t phl = 18.2ps, t plh = 18.9ps, t pavg = 18.6ps c) Now create a chain of four inverters, each with a fanout of 4 (Fig. 2b). Measure the average propagation delay of the second inverter in the chain when applying a step input to the first inverter. Is the delay from part b) or part c) more realistic in terms of what you might see on an actual IC? Explain the role of the first inverter in the chain. (See part e) for the spice deck) t phl = 23.7ps, t plh = 25.3ps, t pavg = 24.5ps

7 The delay from part c) is more realistic because the input is provided by the output of the previous gate (first inverter in the chain) instead of a step function with an arbitrary (i.e., unrealistic) rise/fall time. d) Repeat part c) with the chain of four inverters, each with the fanout of 4 (Fig. 2c), but this time add a 10 ff capacitor (which could be from a wire) between the second and the third inverter. Compare this delay with the result from part c). (See part e) for the spice deck) t phl = 25.5ps, t plh = 27.2ps, t pavg = 26.3ps e) Now let s use the circuit from Fig. 2d to see how connecting the capacitor in a different way may have more or less impact on the delay. What value of C do you need to use to make the delay of the circuit from Fig. 2d match the delay you measured in part d)? Why might this capacitor be larger or smaller than the 10fF used in part d)? To match the average delay of the two chains, C 4.7fF. This capacitor is smaller than the one in part d) because the two nodes that the capacitor is tied to are switching in the opposite directions at approximately the same time. This means that the total voltage swing across the capacitor is roughly twice what was in part d) i.e., the Miller effect is making this C look larger than it would if one of the terminals was grounded (i.e., not moving). t phl = 25.5ps, t plh = 27.2ps, t pavg = 26.3ps SPICE Deck: *** HW2 Problem 2 ***.LIB '/home/ff/ee141/models/gpdk090_mos.sp' TT_s1v.PARAM vddval=1.2 * Inverter SUBCKT Definition.SUBCKT inv vdd gnd in out Mp out in vdd vdd gpdk090_pmos1v W=2u L=0.09u Mn out in gnd gnd gpdk090_nmos1v W=1u L=0.09u.ENDS * Voltage Sources V1 vdd 0 'vddval' V2 vstep 0 PWL 0 0V 10p 0V 1010p 'vddval' 1210p 'vddval' 2210p 0V V3 vstep2 0 PWL 0 0V 10p 0V 11p 'vddval' 211p 'vddval' 212p 0V * Part B Xinv1b vdd 0 vstep vout1b inv M=1 Xinv2b vdd 0 vout1b vout2b inv M=4 Xinv1b2 vdd 0 vstep2 vout1b2 inv M=1

8 Xinv2b2 vdd 0 vout1b2 vout2b2 inv M=4 * Part C Xinv1c vdd 0 vstep2 vout1c inv M=1 Xinv2c vdd 0 vout1c vout2c inv M=4 Xinv3c vdd 0 vout2c vout3c inv M=16 Xinv4c vdd 0 vout3c vout4c inv M=64 * Part D Xinv1d vdd 0 vstep2 vout1d inv M=1 Xinv2d vdd 0 vout1d vout2d inv M=4 Xinv3d vdd 0 vout2d vout3d inv M=16 Xinv4d vdd 0 vout3d vout4d inv M=64 C2 vout2d 0 10f * Part E Xinv1e vdd 0 vstep2 vout1e inv M=1 Xinv2e vdd 0 vout1e vout2e inv M=4 Xinv3e vdd 0 vout2e vout3e inv M=16 Xinv4e vdd 0 vout3e vout4e inv M=64 C vout2e vout1e1 4.7f Xinv1e1 vdd 0 vstep2 vout1e1 inv M=1 Xinv2e1 vdd 0 vout1e1 vout2e1 inv M=4 Xinv3e1 vdd 0 vout2e1 vout3e1 inv M=16 Xinv4e1 vdd 0 vout3e1 vout4e1 inv M=64 * options.option post=2 nomod * analysis.tran 0.1PS 20NS * Part B Measurement.MEASURE TRAN tphlb TRIG V(vstep) VAL='vddval/2' RISE=1 TARG V(vout1b) VAL='vddval/2' FALL=1.MEASURE TRAN tplhb TRIG V(vstep) VAL='vddval/2' FALL=1 TARG V(vout1b) VAL='vddval/2' RISE=1.MEASURE TRAN tpavgb PARAM='(tpHLb+tpLHb)/2'.MEASURE TRAN tphlb2 TRIG V(vstep2) VAL='vddval/2' RISE=1 TARG V(vout1b2) VAL='vddval/2' FALL=1.MEASURE TRAN tplhb2 TRIG V(vstep2) VAL='vddval/2' FALL=1 TARG V(vout1b2) VAL='vddval/2' RISE=1.MEASURE TRAN tpavgb2 PARAM='(tpHLb2+tpLHb2)/2' * Part C measurement.measure TRAN tphlc TRIG V(vout1c) VAL='vddval/2' RISE=1 TARG V(vout2c) VAL='vddval/2' FALL=1.MEASURE TRAN tplhc TRIG V(vout1c) VAL='vddval/2' FALL=1 TARG V(vout2c) VAL='vddval/2' RISE=1.MEASURE TRAN tpavgc PARAM='(tpHLc+tpLHc)/2' * Part D measurement.measure TRAN tphld TRIG V(vout1d) VAL='vddval/2' RISE=1 TARG V(vout2d) VAL='vddval/2' FALL=1.MEASURE TRAN tplhd TRIG V(vout1d) VAL='vddval/2' FALL=1 TARG V(vout2d) VAL='vddval/2' RISE=1.MEASURE TRAN tpavgd PARAM='(tpHLd+tpLHd)/2' * Part E measurement.measure TRAN tphle TRIG V(vout1e) VAL='vddval/2' RISE=1 TARG V(vout2e) VAL='vddval/2' FALL=1.MEASURE TRAN tplhe TRIG V(vout1e) VAL='vddval/2' FALL=1 TARG V(vout2e) VAL='vddval/2' RISE=1.MEASURE TRAN tpavge PARAM='(tpHLe+tpLHe)/2'.END

9 PROBLEM 3: SWITCH MODEL Figure 3 In this problem, you should use the simple switch model for MOSFETs with the following characteristics: V TP = V dd /3, V TN = V dd /3, R NMOS = R PMOS. a) Sketch the VTC of the circuit shown in Figure 3a where In is swept from 0V to V dd with R = 2*R NMOS.

10 b) What happens if R is a lot bigger, say R = 10*R NMOS? Explain your answer! If the resistance in series with the PMOS is large, the switch model results in neither of the possible states of the PMOS switch having a self-consistent solution. Namely, for V in > (2/3)*V dd, if we assume that the PMOS in series with the resistance R is on, we get that its V gs is less than V TP because the output would be very nearly 0V. This is a contradiction since the V gs would need to be greater than V TP for the switch to be on. Similarly, if you assume that the PMOS switch is off, we once again get a contradiction since the source of that switch would eventually go up to V dd (with the output still at 0V). The good news is that in both cases the output is very nearly 0V; any answer that explains the above situation and gives V out 0V will receive full credit. For those interested in using the switch model to come up with a somewhat more accurate (but still crude) estimate, a reasonable approach to take is to notice that the voltage at the source of the PMOS has to basically be pinned at V TP = V dd /3. At this point the switch would hover right between being on and off, so we can imagine that the switch would be on just long enough to pass the same average current as flows through the large resistor. As an example, if R=10*R NMOS, then the current flowing through that resistor is (V dd - V TP )/10*R NMOS = (1/15)*V dd /R NMOS. This would imply that V out = V dd /15 (i.e., very nearly 0V). a) For the input signal In given below, what amount of energy is pulled from the power supply Vdd for the circuits shown in Figs. 3b and 3c respectively? Assume R NMOS = R PMOS =2.5kΩ and R = 7.5kΩ. Circuit from Fig. 3b: When In rises to 1V, the NMOS transistor in the inverter turns on and the PMOS transistor turns off (the V GS of the PMOS is 0.2V, which is less than V TP ). Therefore, the capacitance at the output of the inverter is being discharged through the NMOS transistor, and the time constant isτ 1 = R N C = 2.5kΩ 10 ff = 25ps. Since In is 1V for 1ns, the load capacitance has enough time to discharge completely. The same thing happens when In goes low again the capacitor gets completely charged back to Vdd. Therefore, the total energy pulled out of Vdd due to charging the load capacitance is: E CV V CV ff V fj = sw dd = dd = = 14.4

11 Circuit from Fig. 3c: In this case the time constants are also on the order of ps i.e., still much less than the input pulse length. However, the capacitance is not discharged completely since there is a resistive divider when the NMOS is on. In other words, when the NMOS is on, the capacitor only gets discharged to R N /(R N +R) (instead of to 0V). Thus, the energy due to charging the load capacitance is: 2 R N 2 E1 c = CV sw Vdd = CV dd 1 = 10 ff 1.44V 0.75 = 10.8 fj RN + R In addition to the energy required to charge the capacitor, during the time the NMOS transistor is on we have current continuously flowing out of V dd i.e., there is static power dissipation. The power dissipation due to this current is constant as long as the NMOS is on, and therefore the energy pulled from the power supply is: E 2 = P dd 1ns = V dd V dd 1ns =144 fj R N + R Therefore, the total energy for the circuit from Fig. 3c is: E 3c = E 1c + E 2 =154.8 fj, which is clearly much greater than the CMOS inverter that doesn t dissipate static power to drive its output.