Digital Integrated Circuits A Design Perspective


 Franklin Mills
 3 years ago
 Views:
Transcription
1 Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC
2 Dynamic Logic Introduction Digital IC 2 EE141
3 Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Dynamic logic cascade solution Digital IC 3
4 first glance of dynamic logic Basic components PDN,just like CMOS and pseudonmos Clock control transistors, seperate circuit to two phases Dynamic logic s two phases precharge evaluation Digital IC 4
5 Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. fanin of n requires 2n (n Ntype + n Ptype) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 Ntype + 1 Ptype) transistors Digital IC 5
6 Dynamic Gate M p M p Out Out In 1 In 2 In 3 PDN C L B C M e M e Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1) Digital IC 6
7 Dynamic Gate M p Out M p off on 1 Out In 1 In 2 In 3 PDN C L B ((B)+C) C M e Two phase operation Precharge ( = 0) Evaluate( = 1) M e off on Digital IC 7
8 Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L Digital IC 8
9 Dynamic Logic Dynamic gates uses a clocked pmos pullup Two modes: precharge and evaluate 2 1 2/3 4/3 1 1 Static PseudonMOS Dynamic Precharge Evaluate Precharge Digital IC Slide 9
10 The Foot What if pulldown network is ON during precharge? Use series evaluation transistor to prevent fight. precharge transistor inputs f inputs f foot footed unfooted Digital IC Slide 10
11 Logical Effort Inverter NND2 NOR2 unfooted 1 1 g d = p d = B g d = p d = 1 1 B 1 g d = p d = footed B 3 2 B 2 g d = g d = 2 p d = 3 p d = 2 g d = p d = Digital IC Slide 11
12 Logical Effort Inverter NND2 NOR2 unfooted 1 1 g d = 1/3 p d = 2/3 B g d = 2/3 p d = 3/3 1 1 B 1 g d = 1/3 p d = 3/3 footed B 3 2 B 2 g d = 2/3 g d = 3/3 2 p d = 3/3 3 p d = 4/3 2 g d = 2/3 p d = 5/3 Digital IC Slide 12
13 Monotonicity Dynamic gates require monotonically rising inputs during evaluation 0 > 0 0 > 1 1 > 1 But not 1 > 0 violates monotonicity during evaluation Precharge Evaluate Precharge Output should rise but does not Digital IC Slide 13
14 Monotonicity Woes But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another! = 1 X Precharge Evaluate X Precharge Digital IC Slide 14
15 Monotonicity Woes But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another! = 1 X Precharge Evaluate X Precharge X monotonically falls during evaluation should rise but cannot Digital IC Slide 15
16 Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Dynamic logic cascade solution Digital IC 16
17 Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (V OL = GND and V OH = V DD ) Nonratioed sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (C in ) reduced load capacitance due to smaller output loading (C out ) Digital IC 17
18 Properties of Dynamic Gates Overall power dissipation usually higher than static CMOS no static current path ever exists between V DD and GND (including P sc ) No glitching higher transition probabilities extra load on PDN starts to work as soon as the input signals exceed V Tn, so V M, V IH and V IL equal to V Tn low noise margin (NM L ) Needs a precharge/evaluate clock Digital IC 18
19 Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Chargeleakage Chargesharing Backgate Coupling Clock feedthrough Dynamic logic cascade solution Digital IC 19
20 Issues in Dynamic Design 1: Charge Leakage CLK M p Out C L M e Leakage sources V Out Precharge Evaluate Dominant component is subthreshold current Digital IC 20
21 Solution to Charge Leakage M p M kp Keeper Width:min Length:L B C L Out Option! M e Same approach as level restorer for passtransistor logic Digital IC 21
22 Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Chargeleakage Chargesharing Backgate Coupling Clock feedthrough Dynamic logic cascade solution Digital IC 22
23 Issues in Dynamic Design 2: Charge Sharing M p C L Out Charge stored originally on C L is redistributed (shared) over C L and C leading to reduced robustness B=0 C M e C B Could we move it to there? Digital IC 23
24 Charge Sharing Dynamic gates suffer from charge sharing B = 0 x C x C Charge sharing noise x V x = V = Digital IC Slide 24
25 Charge Sharing Dynamic gates suffer from charge sharing B = 0 x C x C Charge sharing noise x C V = V = V x DD Cx + C Digital IC Slide 25
26 Solution to Charge Redistribution M p M kp Out B M e Precharge internal nodes using a clockdriven transistor (at the cost of increased area and power) Digital IC 26
27 Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Chargeleakage Chargesharing Backgate Coupling Clock feedthrough Dynamic logic cascade solution Digital IC 27
28 Issues in Dynamic Design 3: Backgate Coupling =0 M p C L1 Out1 =1 Out2 =0 C L2 In B=0 M e 3 Dynamic NND Voltage 2 1 Static NND Out1 0 In Out21 Digital IC Time, ns
29 Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Chargeleakage Chargesharing Backgate Coupling Clock feedthrough Dynamic logic cascade solution Digital IC 29
30 Issues in Dynamic Design 4: Clock Feedthrough B M p M e C L Out Coupling between Out and input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above V DD. The fast rising (and falling edges) of the clock couple to Out. Digital IC 30
31 Voltage Clock Feedthrough Out 2.5 Clock feedthrough In 1 In In 3 In In & Out Time, ns 1 Clock feedthrough Digital IC 31
32 Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Chargeleakage Chargesharing Backgate Coupling Clock feedthrough Dynamic logic cascade solution Digital IC 32
33 Domino Gates Follow dynamic stage with inverting static gate Dynamic / static pair is called domino gate Produces monotonic outputs Precharge Evaluate Precharge domino ND W W X Z X B C Z dynamic NND static inverter B W H C X H X Z = B C Z Digital IC Slide 33
34 Designing with Domino Logic V DD V DD V DD M p Out1 M p M r Out2 In 1 In 2 PDN In 4 PDN In 3 Can be eliminated! M e M e Inputs = 0 during precharge Digital IC 34
35 Footless Domino V DD V DD V DD M p Out 1 M p Out 2 M p Out n In In In 3 In n The first gate in the chain needs a foot switch Precharge is rippling shortcircuit current solution is to delay the clock for each stage Digital IC 35
36 npcmos In 1 M p Out1 In 4 M e PUN In 2 In 3 PDN M e In 5 M p Out2 (to PDN) Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN Digital IC 36
37 Domino Summary Domino logic is attractive for highspeed circuits 1.5 2x faster than static CMOS But many challenges: Monotonicity Leakage Charge sharing Noise Widely used in highperformance microprocessors Digital IC Slide 37
38 Summary Static CMOS gates are very robust Logic effect Fanin relate to the delay Power evalutation Other circuits suffer from a variety of pitfalls Pseodu NMOS logic Pass transistor cascade problem,restorer(keeper),some pass logic Dynamic logic Characteristic Cascade issue Domino logic Some pitfalls of dynamic logic Digital IC Slide 38
Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo
Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationEECS 141 F01 Lecture 17
EECS 4 F0 Lecture 7 With major inputs/improvements From MaryJane Irwin (Penn State) Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationCOMP 103. Lecture 16. Dynamic Logic
COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03
More informationTopics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
More informationΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018
ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΔΙΑΛΕΞΗ 11: Dynamic CMOS Circuits ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) (ack: Prof. Mary Jane Irwin and Vijay Narayanan) [Προσαρμογή από
More informationDynamic Combinational Circuits. Dynamic Logic
Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic npcmos (zipper CMOS) Krish Chakrabarty 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:
More informationDynamic Combinational Circuits. Dynamic Logic
Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic npcmos (zipper CMOS) Krish Chakrabarty 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:
More informationLecture 14: Circuit Families
Introduction to CMOS VLSI Design Lecture 4: Circuit Families David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q PseudonMOS Logic q Dynamic Logic q
More informationCPE/EE 427, CPE 527 VLSI Design I L18: Circuit Families. Outline
CPE/EE 47, CPE 57 VLI Design I L8: Circuit Families Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe5705f
More informationPassTransistor Logic
all 26 Digital tegrated ircuits nnouncements No new homework this week roject phase one due on Monday Midterm 2 next Thursday Review session on Tuesday Lecture 8 Logic Dynamic Logic EE4 EE4 2 lass Material
More informationCOMBINATIONAL LOGIC. Combinational Logic
COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino npcmos Combinational vs. Sequential Logic In Logic
More informationDigital Integrated Circuits A Design Perspective
Designing ombinational Logic ircuits dapted from hapter 6 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 ombinational vs. Sequential Logic In
More informationDigital EE141 Integrated Circuits 2nd Combinational Circuits
Digital Integrated Circuits Designing i Combinational Logic Circuits 1 Combinational vs. Sequential Logic 2 Static CMOS Circuit t every point in time (except during the switching transients) each gate
More informationLecture 6: Circuit design part 1
Lecture 6: Circuit design part 6. Combinational circuit design 6. Sequential circuit design 6.3 Circuit simulation 6.4. Hardware description language Combinational Circuit Design. Combinational circuit
More informationCMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More informationCPE/EE 427, CPE 527 VLSI Design I Pass Transistor Logic. Review: CMOS Circuit Styles
PE/EE 427, PE 527 VLI Design I Pass Transistor Logic Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: MO ircuit
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationMiscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]
Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an NSwitch, the
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " DLatch " Timing Constraints! Dynamic Logic " Domino
More informationEEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this
More information2007 Fall: Electronic Circuits 2 CHAPTER 10. DeogKyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits DeogKyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Views / bstractions / Hierarchies ehavioral Structural
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationCPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville
CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit
More informationPower Dissipation. Where Does Power Go in CMOS?
Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit
More informationMODULE 5 Chapter 7. Clocked Storage Elements
MODULE 5 Chapter 7 Clocked Storage Elements 3/9/2015 1 Outline Background Clocked Storage Elements Timing, terminology, classification Static CSEs Latches Registers Dynamic CSEs Latches Registers 3/9/2015
More informationCHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS
CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power
More informationEE141 Spring 2004 Digital Integrated Circuits
EE141 pring 2004 Digital Integrated ircuits Lecture 19 Dynamic Logic  Adders (that is wrapup) 1 Administrative tuff Hw 6 due on Th No lab this week Midterm 2 next week Project 2 to be launched week
More informationEEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits  2 guntzel@inf.ufsc.br
More informationCPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look
CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )
More informationBased on slides/material by. Topic 34. Combinational Logic. Outline. The CMOS Inverter: A First Glance
ased on slides/material by Topic 3 J. Rabaey http://bwrc.eecs.berkeley.edu/lasses/icook/instructors.html Digital Integrated ircuits: Design Perspective, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2018 Memory Overview, Memory Core Cells Today! Charge Leakage/Charge Sharing " Domino Logic Design Considerations! Logic Comparisons!
More informationLecture 16: Circuit Pitfalls
Introduction to CMOS VLSI Design Lecture 16: Circuit Pitfalls David Harris Harvey Mudd College Spring 2004 Outline Pitfalls Detective puzzle Given circuit and symptom, diagnose cause and recommend solution
More informationCMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.
CMOS Inverter: Steady State Response CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates R p V OL = V OH = V M = f(r n, R p ) epartment of Electrical and Computer Engineering University
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationChapter 5 CMOS Logic Gate Design
Chapter 5 CMOS Logic Gate Design Section 5. To achieve correct operation of integrated logic gates, we need to satisfy 1. Functional specification. Temporal (timing) constraint. (1) In CMOS, incorrect
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Designing Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL
More information! Charge Leakage/Charge Sharing. " Domino Logic Design Considerations. ! Logic Comparisons. ! Memory. " Classification. " ROM Memories.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification
More informationName: Answers. Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering CircuitLevel Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Midterm 1 Monday, September 28 5 problems
More informationCARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
More informationMASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences
MSSCHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences nalysis and Design of Digital Integrated Circuits (6.374)  Fall 2003 Quiz #1 Prof. nantha Chandrakasan Student
More informationMOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis  Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
More informationCPE/EE 427, CPE 527 VLSI Design I L07: CMOS Logic Gates, Pass Transistor Logic. Review: CMOS Circuit Styles
PE/EE 427, PE 527 VLI esign I L07: MO Logic Gates, Pass Transistor Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full railtorail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar
More informationStatic CMOS Circuits. Example 1
Static CMOS Circuits Conventional (ratioless) static CMOS Covered so far Ratioed logic (depletion load, pseudo nmos) Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0,
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2018 Final Monday, Apr 0 5 Problems with point weightings shown.
More informationEE213, Spr 2017 HW#3 Due: May 17 th, in class. Figure 1
RULES: Please try to work on your own. Discussion is permissible, but identical submissions are unacceptable! Please show all intermediate steps: a correct solution without an explanation will get zero
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationObjective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components
Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the
More informationMODULE III PHYSICAL DESIGN ISSUES
VLSI Digital Design MODULE III PHYSICAL DESIGN ISSUES 3.2 Powersupply and clock distribution EE  VDD P2006 3:1 3.1.1 Power dissipation in CMOS gates Power dissipation importance Package Cost. Power
More informationECE 342 Solid State Devices & Circuits 4. CMOS
ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More information5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
More informationCMOS Logic Gates. University of Connecticut 172
CMOS Logic Gates University of Connecticut 172 Basic CMOS Inverter Operation V IN P O N O pchannel enhancementtype MOSFET; V T < 0 nchannel enhancementtype MOSFET; V T > 0 If V IN 0, N O is cut off and
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 3  The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 6, 2017 Janakiraman, IITM
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design Prof. blj@eng.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay s CSE477 slides
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: TwoInput NOR Gate (NOR2)
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 14: March 1, 2016 Combination Logic: Ratioed and Pass Logic Lecture Outline! CMOS Gates Review " CMOS Worst Case Analysis! Ratioed Logic Gates!
More informationDC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02  CMOS Transistor Theory & the Effects of Scaling
More informationECE 342 Electronic Circuits. Lecture 34 CMOS Logic
ECE 34 Electronic Circuits Lecture 34 CMOS Logic Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 De Morgan s Law Digital Logic  Generalization ABC... ABC...
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More informationTopics to be Covered. capacitance inductance transmission lines
Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationEE 434 Lecture 33. Logic Design
EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The twoinverter loop X Y X
More informationLogical Effort: Designing for Speed on the Back of an Envelope David Harris Harvey Mudd College Claremont, CA
Logical Effort: Designing for Speed on the Back of an Envelope David Harris David_Harris@hmc.edu Harvey Mudd College Claremont, CA Outline o Introduction o Delay in a Logic Gate o Multistage Logic Networks
More informationEE241  Spring 2000 Advanced Digital Integrated Circuits. Announcements
EE241  Spring 2 Advanced Digital Integrated Circuits Lecture 11 Low PowerLow Energy Circuit Design Announcements Homework #2 due Friday, 3/3 by 5pm Midterm project reports due in two weeks  3/7 by 5pm
More informationLecture 7 Circuit Delay, Area and Power
Lecture 7 Circuit Delay, Area and Power lecture notes from S. Mitra Intro VLSI System course (EE271) Introduction to VLSI Systems 1 Circuits and Delay Introduction to VLSI Systems 2 Power, Delay and Area:
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationLecture 14  Digital Circuits (III) CMOS. April 1, 2003
6.12  Microelectronic Devices and Circuits  Spring 23 Lecture 141 Lecture 14  Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:
More informationL2: Combinational Logic Design (Construction and Boolean Algebra)
L2: Combinational Logic Design (Construction and oolean lgebra) cknowledgements: Lecture material adapted from Chapter 2 of R. Katz, G. orriello, Contemporary Logic Design (second edition), Pearson Education,
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 6: Power Consumption
EE115C Winter 2017 Digital Electronic Circuits Lecture 6: Power Consumption Four Key Design Metrics for Digital ICs Cost of ICs Reliability Speed Power EE115C Winter 2017 2 Power and Energy Challenges
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More information4.10 The CMOS Digital Logic Inverter
11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/1 4.10 The CMOS Digital Logic Inverter Reading Assignment: pp. 336346 Complementary MOSFET (CMOS) is the predominant technology for constructing
More informationL2: Combinational Logic Design (Construction and Boolean Algebra)
L2: Combinational Logic Design (Construction and Boolean Algebra) Acknowledgements: Lecture material adapted from Chapter 2 of R. Katz, G. Borriello, Contemporary Logic Design (second edition), Pearson
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.
More informationDigital Microelectronic Circuits ( ) Ratioed Logic. Lecture 8: Presented by: Mr. Adam Teman
Digital Microelectronic ircuits (36113021 ) Presented by: Mr. Adam Teman Lecture 8: atioed Logic 1 Motivation In the previous lecture, we learned about Standard MOS Digital Logic design. MOS is unquestionably
More information5. CMOS Gate Characteristics CS755
5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 2: January 17, 2017 MOS Fabrication pt. 1: Physics and Methodology Lecture Outline! Digital CMOS Basics! VLSI Fundamentals! Fabrication Process
More informationTopic 4. The CMOS Inverter
Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ Email: p.cheung@ic.ac.uk Topic 41 Noise in Digital Integrated
More informationEE40 Lec 20. MOS Circuits
EE40 Lec 20 MOS Circuits eading: Chap. 12 of Hambley Supplement reading on MOS Circuits http://www.inst.eecs.berkeley.edu/~ee40/fa09/handouts/ee40_mos_circuit.pdf Slide 1 Bias circuits OUTLINE Smallsignal
More informationLecture 13  Digital Circuits (II) MOS Inverter Circuits. March 20, 2003
6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
1 Introduction to TransistorLevel Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationDigital Integrated Circuits A Design Perspective
Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures
More informationEECS 427 Lecture 8: Adders Readings: EECS 427 F09 Lecture 8 1. Reminders. HW3 project initial proposal: due Wednesday 10/7
EECS 427 Lecture 8: dders Readings: 11.111.3.3 3 EECS 427 F09 Lecture 8 1 Reminders HW3 project initial proposal: due Wednesday 10/7 You can schedule a halfhour hour appointment with me to discuss your
More informationEE241  Spring 2001 Advanced Digital Integrated Circuits
EE241  Spring 21 Advanced Digital Integrated Circuits Lecture 12 Low Power Design SelfResetting Logic Signals are pulses, not levels 1 SelfResetting Logic SenseAmplifying Logic Matsui, JSSC 12/94 2
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 2: January 19, 2016 MOS Fabrication pt. 1: Physics and Methodology Lecture Outline! Digital CMOS Basics! VLSI Fundamentals! Fabrication Process
More informationC.K. Ken Yang UCLA Courtesy of MAH EE 215B
Decoders: Logical Effort Applied C.K. Ken Yang UCLA yang@ee.ucla.edu Courtesy of MAH 1 Overview Reading Rabaey 6.2.2 (Ratioed logic) W&H 6.2.2 Overview We have now gone through the basics of decoders,
More informationEE141Fall 2011 Digital Integrated Circuits
EE4Fall 20 Digital Integrated Circuits Lecture 5 Memory decoders Administrative Stuff Homework #6 due today Project posted Phase due next Friday Project done in pairs 2 Last Lecture Last lecture Logical
More informationHw 6 due Thursday, Nov 3, 5pm No lab this week
EE141 Fall 2005 Lecture 18 dders nnouncements Hw 6 due Thursday, Nov 3, 5pm No lab this week Midterm 2 Review: Tue Nov 8, North Gate Hall, Room 105, 6:308:30pm Exam: Thu Nov 10, Morgan, Room 101, 6:308:00pm
More information