EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation


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1 EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
2 nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this Friday at 4 PM in box, Kemper 2131 mirtharajah/parkhurst, EEC 118 Spring
3 Outline Review: CMOS Inverter Transient Characteristics Review: Inverter Power Consumption Combinational MOS Logic Circuits: Rabaey (Kang & Leblebici, ) Combinational MOS Logic Transient Response C Characteristics, Switch Model mirtharajah/parkhurst, EEC 118 Spring
4 Review: Logic Circuit Delay For CMOS (or almost all logic circuit families), only one fundamental equation necessary to determine delay: I = C Consider the discretized version: Rewrite to solve for delay: dv Only three ways to make faster logic: C, ΔV, I dt Δt = I C = C ΔV I ΔV Δt mirtharajah/parkhurst, EEC 118 Spring
5 t t PHL PLH Review: Inverter Delays Hightolow and lowtohigh transitions (exact): = C 2V T 0, n 4( VOH V ) L T 0, n + ln k ( ) + 1 n VOH VT 0, n VOH VT 0, n VOH VOL = C 2V T 0, p 4( VOH VOL V ) L T 0, p + ln k ( ) + 1 p VOH VOL VT 0, p VOH VOL VT 0, p VOH VOL Similar exact method to find rise and fall times Note: to balance rise and fall delays (assuming V OH = V DD, V OL = 0V, and V T0,n =V T0,p ) requires k k p n =1 W L W L 2.5 mirtharajah/parkhurst, EEC 118 Spring p n = μ μ n p
6 Review: Inverter Power Consumption Static power consumption (ideal) = 0 ctually DIL (DrainInduced arrier Lowering), gate leakage, junction leakage are still present Dynamic power consumption P P avg avg / 1 T 2 dv T = out Vout Cload dt + DD out load T dt dt 0 T / 2 T / 2 2 T 1 V = out 1 2 Cload + VDDVoutCload CloadVout T T 2 2 Pavg = CloadVDD = CloadVDD f 1 T P avg = 1 T T 0 ()() t i t dv out ( V V ) C dt mirtharajah/parkhurst, EEC 118 Spring v dt / 2
7 Static CMOS Complementary pullup network (PUN) and pulldown network (PDN) Only one network is on at a time C PUN PUN: PMOS devices Why? PDN: NMOS devices C PDN F Why? PUN and PDN are dual networks mirtharajah/parkhurst, EEC 118 Spring
8 Dual Networks Dual networks: parallel connection in PDN = series connection in PUN, viceversa If CMOS gate implements logic function F: PUN implements function F Example: NND gate parallel F series PDN implements function G = F mirtharajah/parkhurst, EEC 118 Spring
9 NND function: F = NND Gate PUN function: F = = + Or function (+) parallel connection Inverted inputs, PMOS transistors PDN function: G = F = nd function ( ) series connection Noninverted inputs NMOS transistors mirtharajah/parkhurst, EEC 118 Spring
10 NOR Gate NOR gate operation: F = + PUN: F = + = PDN: G = F = + mirtharajah/parkhurst, EEC 118 Spring
11 nalysis of CMOS Gates Represent on transistors as resistors 1 1 W R 1 W W R R Transistors in series resistances in series Effective resistance = 2R Effective length = 2L mirtharajah/parkhurst, EEC 118 Spring
12 nalysis of CMOS Gates (cont.) Represent on transistors as resistors W W R R W R Transistors in parallel resistances in parallel Effective resistance = ½ R Effective width = 2W mirtharajah/parkhurst, EEC 118 Spring
13 CMOS Gates: Equivalent Inverter Represent complex gate as inverter for delay estimation Typically use worstcase delays Example: NND gate Worstcase (slowest) pullup: only 1 PMOS on Pulldown: both NMOS on W P W P W P W N ½W N W N mirtharajah/parkhurst, EEC 118 Spring
14 Example: Complex Gate Design CMOS gate for this truth table: C F F = (+C) mirtharajah/parkhurst, EEC 118 Spring
15 Example: Complex Gate Design CMOS gate for this logic function: F = (+C) = + C 1. Find NMOS pulldown network diagram: G = F = (+C) C Not a unique solution: can exchange order of series connection mirtharajah/parkhurst, EEC 118 Spring
16 Example: Complex Gate 2. Find PMOS pullup network diagram: F = +( C) C F Not a unique solution: can exchange order of series connection ( and C inputs) mirtharajah/parkhurst, EEC 118 Spring
17 Example: Complex Gate Completed gate: W P W P C W N W P F What is worsecase pullup delay? What is worsecase pulldown delay? Effective inverter for delay calculation: C W N ½W P W N ½W N mirtharajah/parkhurst, EEC 118 Spring
18 CMOS Gate Design Designing a CMOS gate: Find pulldown NMOS network from logic function or by inspection Find pullup PMOS network y inspection Using logic function Using dual network approach Size transistors using equivalent inverter Find worstcase pullup and pulldown paths Size to meet rise/fall or threshold requirements mirtharajah/parkhurst, EEC 118 Spring
19 nalysis of CMOS gates Represent on transistors as resistors 1 1 W R 1 W W R R Transistors in series resistances in series Effective resistance = 2R Effective width = ½ W (equivalent to 2L) Typically use minimum length devices (L = L min ) mirtharajah/parkhurst, EEC 118 Spring
20 nalysis of CMOS Gates (cont.) Represent on transistors as resistors W W R R W R Transistors in parallel resistances in parallel Effective resistance = ½ R Effective width = 2W Typically use minimum length devices (L = Lmin) mirtharajah/parkhurst, EEC 118 Spring
21 Equivalent Inverter CMOS gates: many paths to Vdd and Gnd Multiple values for V M, V IL, V IH, etc Different delays for each input combination Equivalent inverter Represent each gate as an inverter with appropriate device width Include only transistors which are on or switching Calculate V M, delays, etc using inverter equations mirtharajah/parkhurst, EEC 118 Spring
22 Static CMOS Logic Characteristics For V M, the V M of the equivalent inverter is used (assumes all inputs are tied together) For specific input patterns, V M will be different For V IL and V IH, only the worst case is interesting since circuits must be designed for worstcase noise margin For delays, both the maximum and minimum must be accounted for in race analysis mirtharajah/parkhurst, EEC 118 Spring
23 Equivalent Inverter: V M Example: NND gate threshold V M Three possibilities: & switch together switches alone switches alone What is equivalent inverter for each case? mirtharajah/parkhurst, EEC 118 Spring
24 Equivalent Inverter: Delay Represent complex gate as inverter for delay estimation Use worsecase delays Example: NND gate Worsecase (slowest) pullup: only 1 PMOS on Pulldown: both NMOS on W P W P W P W N ½W N W N mirtharajah/parkhurst, EEC 118 Spring
25 Example: NOR gate Find threshold voltage V TH when both inputs switch simultaneously W P W P F Two methods: Transistor equations (complex) Equivalent inverter W N Should get same answer W N mirtharajah/parkhurst, EEC 118 Spring
26 Example: Complex Gate Completed gate: W P W P C W N W P F What is worsecase pullup delay? What is worsecase pulldown delay? Effective inverter for delay calculation: W N C W N ½W P ½W N mirtharajah/parkhurst, EEC 118 Spring
27 Transistor Sizing Sizing for switching threshold ll inputs switch together Sizing for delay Find worstcase input combination Find equivalent inverter, use inverter analysis to set device sizes mirtharajah/parkhurst, EEC 118 Spring
28 Common CMOS Gate Topologies ndorinvert (OI) Sum of products boolean function Parallel branches of series connected NMOS OrndInvert (OI) Product of sums boolean function Series connection of sets of parallel NMOS mirtharajah/parkhurst, EEC 118 Spring
29 Graphased Dual Network Use graph theory to help design gates Mostly implemented in CD tools Draw network for PUN or PDN Circuit nodes are vertices Transistors are edges F F gnd mirtharajah/parkhurst, EEC 118 Spring
30 Graphased Dual Network (2) To derive dual network: Create new node in each enclosed region of graph Draw new edge intersecting each original edge Edge is controlled by inverted input F n1 vdd F n1 F gnd Convert to layout using consistent Euler paths mirtharajah/parkhurst, EEC 118 Spring
31 Propagation Delay nalysis  The Switch Model = R ON V DD V V DD DD R R p R p R p p F F R n C L R n C L R n R n R n R p F C L (a) Inverter (b) 2input NND (c) 2input NOR t p = 0.69 R on C L (assuming that C L dominates!) mirtharajah/parkhurst, EEC 118 Spring
32 Switch Level Model Model transistors as switches with series resistance Resistance R on = average resistance for a transition Capacitance C L = average load capacitance for a transition (same as we analyzed for transient inverter delays) R N R P C L mirtharajah/parkhurst, EEC 118 Spring
33 What is the Value of R on? mirtharajah/parkhurst, EEC 118 Spring
34 Switch Level Model Delays R N C L I I t t 1 p Delay estimation using switchlevel model (for general RC circuit): = = t = C V R 0 dv dt = RC t p = V 1 V 0 dt RC dv V = dt RC V V [ ] 1 ln( V = 1) ln( V0 ) RC ln V0 = C I dv dv mirtharajah/parkhurst, EEC 118 Spring
35 Switch Level Model RC Delays For fall delay t phl, V 0 =V DD, V 1 =V DD /2 t t t t p p phl plh = = = = V V RC ln 1 = RC ln 2 V V 0 RC ln(0.5) 0.69R C 0.69R n p C L L 1 DD DD Standard RCdelay equations from literature mirtharajah/parkhurst, EEC 118 Spring
36 Numerical Examples Example resistances for 1.2 μm CMOS mirtharajah/parkhurst, EEC 118 Spring
37 nalysis of Propagation Delay V DD R p R p F 1. ssume R n =R p = resistance of minimum sized NMOS inverter 2. Determine Worst Case Input transition (Delay depends on input values) R n R n C L 3. Example: t plh for 2input NND  Worst case when only ONE PMOS Pulls up the output node  For 2 PMOS devices in parallel, the resistance is lower t plh = 0.69R p C L 2input NND 4. Example: t phl for 2input NND  Worst case : TWO NMOS in series t phl = 0.69(2R n )C L mirtharajah/parkhurst, EEC 118 Spring
38 Design for Worst Case V DD V DD F C L D 2 C D C 2 F NND Gate Complex Gate Here it is assumed that R p = R n mirtharajah/parkhurst, EEC 118 Spring
39 FanIn and FanOut V DD C D FanOut Number of logic gates connected to output (2 FET gate capacitances per fanout) C D FanIn Number of logical inputs Quadratic delay term due to: 1.Resistance increasing 2.Capacitance increasing for t phl (series NMOS) t p proportional to a 1 FI + a 2 FI 2 + a 3 FO mirtharajah/parkhurst, EEC 118 Spring
40 Fast Complex Gates  Design Techniques Increase Transistor Sizing: Works as long as Fanout capacitance dominates self capacitance (S/D cap increases with increased width) Progressive Sizing: In N MN Out C L M 1 > M 2 > M 3 > MN In 3 M3 C 3 In 2 In 1 M2 M1 C 2 C 1 Distributed RCline Can Reduce Delay by more than 30%! mirtharajah/parkhurst, EEC 118 Spring
41 Fast Complex Gates  Design Techniques (2) Transistor Ordering Place last arriving input closest to output node critical path critical path In 3 M3 C L In 1 M1 C L In 2 M2 C 2 In 2 M2 C 2 In 1 M1 C 1 In 3 M3 C 3 (a) mirtharajah/parkhurst, EEC 118 Spring (b)
42 Fast Complex Gates  Design Techniques (3) Improved Logic Design Note FanOut capacitance is the same, but FanIn resistance lower for input gates (fewer series FETs) mirtharajah/parkhurst, EEC 118 Spring
43 Fast Complex Gates  Design Techniques (4) uffering: Isolate Fanin from Fanout C L C L Keeps high fanin resistance isolated from large capacitive load C L mirtharajah/parkhurst, EEC 118 Spring
44 4 Input NND Gate VDD V DD In 1 In 2 In 3 In 4 In 1 Out Out In 2 In 3 In 4 GND In1 In2 In3 In4 mirtharajah/parkhurst, EEC 118 Spring
45 Capacitances in a 4 input NND Gate VDD Cgs Cgs 5 Csb 6 Csb 5 6 Cgs 7 Csb Cgs In In 7 8 Csb In 3 In 4 Cgd Cgd 5 Cdb 6 Cdb 5 6 Cgd 7 Cdb Cgd 7 8 Cdb 8 In 1 In 2 In 3 In 4 Cgd 1 Cgs 1 Cgd 2 Cgs 2 Cgd 3 Cgs 3 Cgd 4 Cgs Cdb 1 Csb 1 Cdb 2 Csb 2 Cdb 3 Csb 3 Cdb 4 Csb 4 Vout Note that the value of Cload for calculating propagation delay depends on which capacitances need to be discharged or charged when the critical signal arrives. Example: In 1 = In 3 = In 4 = 1. In 2 = 0. In 2 switches from low to high. Hence, Nodes 3 and 4 are already discharged to ground. In order for Vout to go from high to low Vout node and node 2 must be discharged. CL = Cgd5+Cgd7+Cgd8+2Cgd6(Miller)+Cdb5+Cdb6+Cdb7+Cd b8 +Cgd1+ Cdb1+ Cgs1+ Csb1+ 2Cgd2+ Cdb2+ Cw mirtharajah/parkhurst, EEC 118 Spring
46 Next Topic: Sequential Logic asic sequential circuits in CMOS RS latches, transparent latches, flipflops lternative sequential element topologies Pipelining mirtharajah/parkhurst, EEC 118 Spring
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