L2: Combinational Logic Design (Construction and Boolean Algebra)

Transcription

1 L2: Combinational Logic Design (Construction and oolean lgebra) cknowledgements: Lecture material adapted from Chapter 2 of R. Katz, G. orriello, Contemporary Logic Design (second edition), Pearson Education, 25. Some lecture material adapted from J. Rabaey,. Chandrakasan,. Nikolic, Digital Integrated Circuits: Design Perspective Copyright 23 Prentice Hall/Pearson. L2: 6. Spring 27 Introductory Digital Systems Laboratory

2 Review: Noise Margin Truth Table IN OUT IN OUT "" V OH V IH V(y) V OH Slope = - Undefined Region NM L = V IL -V OL NM H = V OH -V IH V IL Slope = - "" V OL V OL V OL V IL V IH V OH V(x) Large noise margins protect against various noise sources L2: 6. Spring 27 Introductory Digital Systems Laboratory 2

3 TTL Logic Style (97 s-early 8 s) C + + v E - E v CE - Q Q2 Q3 74LS4 (courtesy TI) L2: 6. Spring 27 Introductory Digital Systems Laboratory 3

4 MOS Technology: The NMOS Switch source gate drain D N+ N+ G V T =.5V P-substrate S V s Switch Model OFF R NMOS V GS < V T ON R NMOS V GS > V T NMOS ON when Switch Input is High L2: 6. Spring 27 Introductory Digital Systems Laboratory 4

5 NMOS Device Characteristics Polysilicon luminum 6 x -4 VGS= 2.5 V 5 4 Resistive Saturation VGS= 2. V I D () 3 2 VGS=.5 V VGS=. V D V DS (V) G + V GS - S I D V T =.5V MOS is a very non-linear. Switch-resistor model sufficient for first order analysis. L2: 6. Spring 27 Introductory Digital Systems Laboratory 5

6 PMOS: The Complementary Switch source gate drain S P+ P+ N-substrate G V T = -.5V D Switch V DD R PMOS RPMOS OFF ON Model V GS > V T V GS < V T PMOS ON when Switch Input is Low L2: 6. Spring 27 Introductory Digital Systems Laboratory 6

7 The CMOS Inverter V DD Switch Model V DD G S R PMOS IN D D OUT IN OUT G R NMOS S IN Rail-to-rail Swing in CMOS L2: 6. Spring 27 Introductory Digital Systems Laboratory 7

8 Inverter VTC: Load Line nalysis I Dn = = 2.5 V DD PMOS =.5 = 2 NMOS G S = =.5 IN G D OUT D S =.5 = 2 = 2.5 = = = =.5 = V out 2 CMOS gates have: Rail-to-rail swing (V to V DD ) Large noise margins zero static power dissipation V out (V) V (V) in L2: 6. Spring 27 Introductory Digital Systems Laboratory 8

9 Possible Function of Two Inputs There are 6 possible functions of 2 input variables: X Y F X Y 6 possible functions (F F 5 ) X ND Y X Y X XOR Y X OR Y X = Y X NOR Y NOT (X OR Y) NOT Y NOT X X NND Y NOT (X ND Y) In general, there are 2 (2^n) functions of n inputs L2: 6. Spring 27 Introductory Digital Systems Laboratory 9

10 Common Logic Gates Gate Symbol Truth-Table Expression X Y Z NND X Y Z Z = X Y X Y Z ND X Y Z Z = X Y X Y Z NOR X Y Z Z = X + Y X Y Z OR X Y Z Z = X + Y L2: 6. Spring 27 Introductory Digital Systems Laboratory

11 Exclusive (N)OR Gate XOR (X Y) X Y Z X Y Z Z = X Y + X Y X or Y but not both ("inequality", "difference") XNOR (X Y) X Y Z X Y Z Z = X Y + X Y X and Y the same ("equality") Widely used in arithmetic structures such as adders and multipliers L2: 6. Spring 27 Introductory Digital Systems Laboratory

12 Generic CMOS Recipe V dd... F(,, n ) n pullup: make this connection when we want F(,, n ) = pulldown: make this connection when we want F(,, n ) = Note: CMOS gates result in inverting functions! (easier to build NND vs. ND) PUN PDN C L O PDN PUN O ff n ff n ff n n ff How do you build a 2-input NOR Gate? L2: 6. Spring 27 Introductory Digital Systems Laboratory 2

13 Theorems of oolean lgebra (I) Elementary. X + = X D. X = X 2. X + = 2D. X = 3. X + X = X 3D. X X = X 4. (X) = X 5. X + X = 5D. X X = Commutativity: 6. X + Y = Y + X 6D. X Y = Y X ssociativity: 7. (X + Y) + Z = X + (Y + Z) 7D. (X Y) Z = X (Y Z) Distributivity: 8. X (Y + Z) = (X Y) + (X Z) 8D. X + (Y Z) = (X + Y) (X + Z) Uniting: 9. X Y + X Y = X 9D. (X + Y) (X + Y) = X bsorption:. X + X Y = X D. X (X + Y) = X. (X + Y) Y = X Y D. (X Y) + Y = X + Y L2: 6. Spring 27 Introductory Digital Systems Laboratory 3

14 Theorems of oolean lgebra (II) Factoring: 2. (X Y) + (X Z) = 2D. (X + Y) (X + Z) = X (Y + Z) X + (Y Z) Consensus: 3. (X Y) + (Y Z) + (X Z) = 3D. (X + Y) (Y + Z) (X + Z) = X Y + X Z (X + Y) (X + Z) De Morgan's: 4. (X + Y +...) = X Y... 4D. (X Y...) = X + Y +... Generalized De Morgan's: 5. f(x,x2,...,xn,,,+, ) = f(x,x2,...,xn,,,,+) Duality Dual of a oolean expression is derived by replacing by +, + by, by, and by, and leaving variables unchanged f (X,X2,...,Xn,,,+, ) f(x,x2,...,xn,,,,+) L2: 6. Spring 27 Introductory Digital Systems Laboratory 4

15 Simple Example: One it dder -bit binary adder inputs:,, Carry-in outputs: Sum, Carry-out Cin S Cout Cin S Cout Product term (or minterm) Sum-of-Products Canonical Form S = Cin + Cin + Cin + Cin Cout = Cin + Cin + Cin + Cin NDed product of literals input combination for which output is true Each variable appears exactly once, in true or inverted form (but not both) L2: 6. Spring 27 Introductory Digital Systems Laboratory 5

16 Simplify oolean Expressions Cout = Cin + Cin + Cin + Cin = Cin + Cin + Cin + Cin + Cin + Cin = ( + ) Cin + ( + ) Cin + (Cin + Cin) = Cin + Cin + = ( + ) Cin + S = Cin + Cin + Cin + Cin =( + )Cin + ( + ) Cin =( ) Cin + ( ) Cin = Cin L2: 6. Spring 27 Introductory Digital Systems Laboratory 6

17 Sum-of of-products & Product-of of-sum Product term (or minterm): NDed product of literals input combination for which output is true C minterms C m C m C m2 C m3 C m4 C m5 C m6 C m7 short-hand notation form in terms of 3 variables F in canonical form: F(,, C) = Σm(,3,5,6,7) = m + m3 + m5 + m6 + m7 F = C + C+ C + C + C canonical form minimal form F(,, C) = C + C + C + C + C = ( )C + C = (( + )( + ))C + C = C + C = C + C = + C Sum term (or maxterm) - ORed sum of literals input combination for which output is false C maxterms + + C M F in canonical form: + + C M F(,, C) = ΠM(,2,4) + + C M2 = M M2 M4 + + C M3 = ( + + C) ( + + C) ( + + C) + + C M4 canonical form minimal form + + C M5 F(,, C) = ( + + C) ( + + C) ( + + C) + +C M6 = ( + + C) ( + + C) + + C M7 ( + + C) ( + + C) = ( + C) ( + C) short-hand notation for maxterms of 3 variables L2: 6. Spring 27 Introductory Digital Systems Laboratory 7

18 The Uniting Theorem Key tool to simplification: ( + ) = Essence of simplification of two-level logic Find two element subsets of the ON-set where only one variable changes its value this single varying variable can be eliminated and a single product term used to represent both elements F F = + = ( +) = has the same value in both on-set rows remains has a different value in the two rows is eliminated L2: 6. Spring 27 Introductory Digital Systems Laboratory 8

19 oolean Cubes Just another way to represent truth table Visual technique for identifying when the uniting theorem can be applied n input variables = n-dimensional "cube" -cube X Y X XY 2-cube Y Z XYZ X 3-cube Y Z W X 4-cube WXYZ L2: 6. Spring 27 Introductory Digital Systems Laboratory 9

20 Mapping Truth Tables onto oolean Cubes Uniting theorem Circled group of the on-set is called the F F adjacency plane. Each adjacency plane corresponds to a product term. ON-set = solid nodes OFF-set = empty nodes varies within face, does not this face represents the literal Three variable example: inary full-adder carry-out logic Cin Cout (+)Cin C (Cin+Cin) Cout = Cin++Cin (+)Cin The on-set is completely covered by the combination (OR) of the subcubes of lower dimensionality - note that is covered three times L2: 6. Spring 27 Introductory Digital Systems Laboratory 2

21 Higher Dimension Cubes F(,,C) = Σm(4,5,6,7) C on-set forms a square i.e., a cube of dimension 2 (2-D adjacency plane) represents an expression in one variable i.e., 3 dimensions 2 dimensions is asserted (true) and unchanged and C vary This subcube represents the literal In a 3-cube (three variables): -cube, i.e., a single node, yields a term in 3 literals -cube, i.e., a line of two nodes, yields a term in 2 literals 2-cube, i.e., a plane of four nodes, yields a term in literal 3-cube, i.e., a cube of eight nodes, yields a constant term "" In general, m-subcube within an n-cube (m < n) yields a term with n m literals L2: 6. Spring 27 Introductory Digital Systems Laboratory 2

22 Karnaugh Maps lternative to truth-tables to help visualize adjacencies Guide to applying the uniting theorem - On-set elements with only one variable changing value are adjacent unlike in a linear truth-table 2 3 Numbering scheme based on Gray code F e.g.,,,, (only a single bit changes in code for adjacent map cells) 2-variable K-map 3-variable K-map C C L2: 6. Spring 27 Introductory Digital Systems Laboratory 22 CD D 4-variable K-map

23 K-Map Examples Cin C Cout = F(,,C) = C C F(,,C) = Σm(,4,5,7) F = F' simply replace 's with 's and vice versa F'(,,C) = Σm(,2,3,6) F' = L2: 6. Spring 27 Introductory Digital Systems Laboratory 23

24 Four Variable Karnaugh Map CD F(,,C,D) = Σm(,2,3,5,6,7,8,,,4,5) F = C + D + D C D Find the smallest number of the largest possible subcubes that cover the ON-set C D K-map Corner djacency Illustrated in the 4-Cube L2: 6. Spring 27 Introductory Digital Systems Laboratory 24

25 K-Map Example: Don t t Cares Don't Cares can can be be treated as as 's 's or or 's 's if if it it is is advantageous to to do do so so CD X F(,,C,D) = Σm(,3,5,7,9) + Σd(6,2,3) F = D + C D w/o don't cares C X X D F = C D + D w/ don't cares y treating this DC as a "", a 2-cube can be formed rather than one -cube CD X In PoS form: F = D ( + C) Equivalent answer as above, but fewer literals C X X D L2: 6. Spring 27 Introductory Digital Systems Laboratory 25

26 Hazards L2: 6. Spring 27 Introductory Digital Systems Laboratory 26

27 Fixing Hazards In general, it is difficult to avoid hazards need a robust design methodology to deal with hazards. L2: 6. Spring 27 Introductory Digital Systems Laboratory 27