CHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS


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1 CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power Dissipation 5
2 5. CMOS Logic Gate Circuits Switch Level Transistor Model NMOS and PMOS transistors as switches Switch on: small resistance R on or r DS Switch off: open circuit The CMOS Inverter Invert the logic value of the input represented by Boolean expression When X = (V X = V ) Y = 0 (V Y = 0V) When X = 0 (V X = 0V) Y = (V Y = V ) Y X 5
3 General Structure of CMOS Logic NMOS pull down network (PDN) and PMOS pull up network (PUN) operated by input variables in a complementary fashion Alternative Circuit Symbols for MOSFETS in Digital Circuits 5 3
4 Two Input Logic Gates Two input NOR gate, two input NAND gate and Exclusive OR gate 5 4
5 Synthesis Method for PUN and PDN The PDN can be directly synthesized by expressing the inverted Boolean function in uncomplemented variables (inverters are needed if complemented variables appear in the expression) The PUN can be directly synthesized by expressing the nonverted Boolean function in complemented variables (inverters are needed if uncomplemented variables appear in the expression) The PDN can be obtained from the PUN (and vice versa) using the duality property 5 5
6 Examples for CMOS Logic Gates 5 6
7 5. Digital Logic Inverters The Voltage Transfer Characteristic (VTC) The function of the inverter is to invert the logic value of its input signal The voltage transfer characteristic is used to evaluate the quality of inverter operation VTC parameters V OH : output high level V OL : output low level V IH : the minimum value of input interpreted by the inverter as a logic V IL : the maximum value of input interpreted by the inverter as a logic 0 Transition region: input level between V IL and V IH 5 7
8 Noise Margins The VTC is generally non linear V IH and V IL are defined as the points at which the slope of the VTC is Robustness (noise margin at a high level): NM H = V OH V IH Robustness (noise margin at a low level): NM L = V IL V OL Static inverter characteristics for ideal VTC: V OH = V V OL = 0 V IH = V IL = V / NM H = NM L = V / Ideal VTC 5 8
9 Propagation Delay t PHL : high to low propagation delay t PLH : low to high propagation delay t P (propagation delay) = ( t PLH + t PHL )/ Maximum switching frequency f max = /t P The output transient of the inverter can be characterized by a RC charge/discharge model v O ( t) V ( V V t / RC 0 ) e 5 9
10 Inverter Implementation Simplest implementation of the inverter with a MOSFET and a load Inverter implementation with complementary switches Inverter implementation with a double throw switch 5 0
11 Circuit Operation 5.3 The CMOS Inverter A CMOS inverter consists of an n channel and a p channel MOSFET The n channel device turns on and the p channel device turns off as the input level goes high The p channel device turns on and the n channel device turns off as the input level goes low ' The turn on device is modeled by a resistance: ' rdsn kn W / L n( V Vtn) and rdsp k p W / Lp( V V OH = V and V OL = 0 for any CMOS inverter V ) tp 5
12 The Voltage Transfer Characteristic The transistors go through five different operation regions as the input goes from 0 to V The operating point is obtained by making i DN = i DP Region I: (Q N off; Q P tri.) Region II: (Q N sat.; Q P tri.) Region III: (Q N sat; Q P sat) Region IV: (Q N tri.; Q P sat.) Region V: (Q N tri.; Q P off) i ( 0) DN i DP idn kn( vi Vtn) idn kn( vi Vtn) idn kn vi Vtn) v i DN i DP ( 0) i i DP DP v k p ( V k i p ( V v k I V I tp v V ( V )( V tp ) v v V ( O O DP p I tp O ) ) ( V v O ) i D i D Region I v O Region II v O i D i D i D Region III Region IV Region V v O v O v O 5
13 Static Characteristics of the CMOS Inverter Ratioless logic: V OH and V OL are independent of ratio of the transistors V OH = V V OL = 0 Static power dissipation is zero for both states Noise margins can be determined by the VTC The switching voltage (when v I = v O ) is defined by V r( V V ) V k tp tn p p ( W / L) p where r M r kn n( W / L) n V M increases (VTC shifts) with r NM L increases and NM H decreases as r increases NM L decreases and NM H increases as r decreases 5 3
14 The Matched Inverter A matched inverter has equivalent pull up and pull down device with k n = k p and V tn = V tp = V t The VTC is symmetric Determine V IL from the VTC in Region II: ( vi V ) t ( V v V )( V v Determine V IH from the VTC in Region IV: ) Noise margins: NM H = NM L = (3V + V t )/8 Switching voltage: V M = V / I t O ( V v O v I Vt ( V vo ) ( V vi Vt ) ( V vo ) dvi V IL (3V 8 V ) t dv ( vi Vt ) vo vo ( V vi Vt ) dvo dvo vo ( vi Vt ) vo ( V vi Vt ) dvi dvi VIH (5V V t ) 8 O ) dv dv O I 5 4
15 5.4 Dynamic Operation of the CMOS Inverter Determining the Propagation Delay Evaluated by charging/discharge the output capacitor C through Q P and Q N Average current method: t PHL : I i i av DN t PLH : i DN ( E) idn ( M ) ( E) kn( V Vtn) V M ) kn ( V Vtn) CV nc I k V V DN ( t PHL where t PLH where av n 7 3V tn Vtn n / 4 V V Propagation delay: t P = (t PHL +t PLH )/ CV pc Iav k pv 7 3 Vtp Vtp n / 4 V V 5 5
16 An alternative approach: Modeling the turn on device as a resistance Use RC charge/discharge behavior to evaluate the propagation delay The empirical values of the resistors are given by R.5 ( k) ( W / L) R ( ) N P k n ( W / L) p t PHL = 0.69R N C t PLH = 0.69R P C and
17 Determining the Equivalent Load Capacitance Components accountable for the equivalent load capacitance Transistor parasitic capacitances Wiring capacitance or interconnect capacitance Input capacitance of the following stages C Cgd Cgd Cdb Cdb Cg3 Cg 4 C w 5 7
18 Inverter Sizing 5.5 Transistor Sizing Minimum length permitted by the technology is usually used as the length for all channels Device aspect ratio (W/L) n is usually selected in the range to.5 The selection of (W/L) p is relative to (W/L) n Matched inverter by (W/L) p : (W/L) n = n : p (W/L) p = (W/L) n : minimum area, small propagation delay (W/L) p = (W/L) n : a frequently used compromise Transistor sizing (aspect ratios are increased by a factor of S) versus propagation delay Load capacitance: C C C SC Equivalent resistance: Propagation delay: int ext int 0 C ext R eq RN ( S R R P eq ) S S Req tp ( SCint 0 Cext ) 0.69 Req C 0 int 0 Req0C S S 0 ext 5 8
19 Transistor Sizing The (W/L) ratios are chosen for a worst case gate delay equal to that of the basic inverter The derivation of equivalent (W/L) ratio is based on the equivalent resistance of the transistors Series Connection ( W / L)... eq ( W / L) ( W / L) r DS ( W / L) ParallelConnection ( W / L) eq ( W / L) ( W / L)... Effects of Fan In and Fan Out Each additional input to a CMOS gate requires two additional transistors Increases the chip area and the propagation delay due to excess capacitive loading The number of NAND gate is typically limited to 4 Redesign the logic design may be required for a higher number of inputs Advantages of using CMOS logic: static power dissipation, ratioless design, noise margin Disadvantage of using CMOS logic: area, complexity, capacitive loading, propagation delay 5 9
20 Driving a Large Capacitance A large capacitive load drastically increases the propagation delay Use a large inverter to drive the load could alleviate the propagation delay The input capacitance increases accordingly equivalently shifting the burden forward Chain of scaled inverters in cascade to alleviate the problem with large capacitive load 5 0
21 Power Dissipation 5.6 Power Dissipation Static power dissipation: power dissipated when the inverter stays in logic 0 or logic Dynamic power dissipation: power dissipated as the output is switching 0.5C(V ) is dissipated in the PUN in each cycle 0.5C(V ) is dissipated in the PDN in each cycle Dynamic power dissipation: P D = f C(V ) Another component of power dissipation during switching results from the current conduction through Q P and Q N and the peak current is given by I peak V kn V tn Power Delay Product and Energy Delay Product Power and delay are often in conflict for inverter operation Power delay product is a figure of merit for comparing logic circuit technologies or families Power delay product is defined as PDP PD tp CV / Energy delay product is defined as / EDP CV t P 5
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