VLSI Design and Simulation


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1 VLSI Design and Simulation CMOS Inverters
2 Topics Inverter VTC Noise Margin Static Load Inverters
3 CMOS Inverter FirstOrder DC Analysis R p V OL = 0 V OH = R n =0 =
4 CMOS Inverter: Transient Response R p t phl = f(r on.c L ) = 0.69 R on C L C L C L R n =0 (a) Lowtohigh = (b) Hightolow
5 PMOS Load Lines = +V GSp I Dn =  I Dp I Dn = +V DSp I Dp =0 I Dn I Dn =0 =1.5 =1.5 V GSp =1 V DSp V DSp V GSp =.5 = +V GSp I Dn =  I Dp = +V DSp
6 CMOS Inverter Load Characteristics I Dn = 0 =.5 PMOS = 0.5 = NMOS = 1 = 1.5 = 1.5 = 1 = = 1.5 = 1 = 0.5 =.5 = 0
7 CMOS Inverter VTC NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off
8 CMOS Inverter VTC nmos cutoff pmos linear V tn
9 CMOS Inverter VTC nmos saturation pmos linear V tn V tp
10 CMOS Inverter VTC Set pmos Linear I DS equal to nmos Saturation I DS k n V tn ( ) ( ) = k p V tp ( ) ( V tp )( ) + k n k p ( ( ) V DD) ( V tn) ( ) = ( V tp ) + ( V tp ) k n k p = ( V tp ) + ( V tp ) k n k p ( V tn ) = 0 ( V tn )
11 CMOS Inverter VTC Short channel model k n V DSATn V tn V DSATn = k p V tp ( ) ( ) ( V tp )( ) + k n ( ) = ( V tp ) + ( V tp ) k n = ( V tp ) + ( V tp ) k n ( ( ) ) V DSATn V tn V DSATn = 0 k p V DSATn V tn V DSATn k p V DSATn V tn V DSATn k p
12 CMOS Inverter VTC nmos saturation pmos saturation V tn V tp V tn
13 CMOS Inverter VTC nmos linear pmos saturation V tn V tp V tp V tn
14 CMOS Inverter VTC Set nmos Linear I DS equal to pmos Saturation I DS k p ( V tp ) = k n ( V tn ) ( V tn ) + k p k n = ( V tn ) ( V tn ) k p k n ( V tp ) = 0 ( V tp )
15 CMOS Inverter VTC Short channel model k p V DSATp V tp V DSATp = k n ( V tn ) ( V tp ) + k p V DSATp V tp V DSATp = 0 k n = ( V tn ) ( V tn ) k p V DSATp V tp V DSATp k n
16 CMOS Inverter VTC nmos linear pmos cutoff V tn V tp V tp V tn
17 CMOS Inverter VTC V tn V tp
18 CMOS Inverter pmos mode nmos mode <V t Linear Cutoff V t < <  V t Linear Saturation ( + V t ) + ( + V t ) ( V t ) V t < < +V t Saturation Saturation Interpolate out +V t < in < V t Saturation Linear ( V t ) ( V t ) ( + V t ) in > DD V t Cutoff Linear 0
19 Switching Threshold The point at which the inverter has both transistors in saturation k n ( V V M tn) = k p ( V V V M DD tp) ( V M V tn ) = k p k n V M ( V M V tp ) ( ) ( ) ( 1+ r) = V tn + r + V tp V M = V + r V + V tn DD tp 1+ r
20 Switching Threshold V M = r ( V + tp) + V tn 1+ r When V tn =V tp and r=1, V M = In switching region, the curve is actually vertical; can have multiple values
21 CMOS Inverter VTC V M V tp V M V tp V tn V M V tp
22 Switching Threshold With shortchannel devices k n V DSATn V M V tn V DSATn = k p V DSATp V M V tp V DSATp V M V tn V DSATn = k V p DSATp V M V tp V DSATp k n V DSATn V M 1+ k V p DSATp = V tn + V DSATn k V p DSATp V tp V DSATp k n V DSATn k n V DSATn V tn + V DSATn + r + V tp + V DSATp V M = 1+ r V M = r 1+ r
23 Noise Margin A measure of the acceptable noise at a gate input so that the output is not affected. Noise Noise
24 Noise Budget Allocates gross noise margin to expected sources of noise Sources: supply noise, cross talk, interference, offset Differentiate between fixed and proportional noise sources
25 Key Reliability Properties Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) Noise immunity is the more important metric the capability to suppress noise sources Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver;
26 Noise Margins V OHmin NM H V IHmin V ILmax V OLmax NM L V SS
27 Noise Margins Obvious choice Set V IH =V IL =V M No noise margin V OH? High gain at V IH and V IL Any perturbations could cause incorrect values V sth
28 Noise Margins Set V IL = V tn and V IH = V tp V OL = 0 and V OH = Too restrictive V tn V tp
29 Noise Margins Voltage Transfer Function = f ( ) Voltage Transfer Function with Noise = f ( + ΔV noise ) f ( ) + d d ΔV noise Perturbed voltage is the sum of the nominal output plus the gain times the noise Keep the gain less than 1
30 Noise Margins V OH V OL V IL V IH
31 Noise Margins Setting the derivative to 1 and solving V M V Tn V DSATn V IH = V M + V M 1+ r V IL = V M V M Assuming ( ) ( ) λ n λ p ( ) ( ( ) V V V M Tn DSATn ) λ n λ p 1+ r r =1,V Tn = V Tp,V DSATn = V V IH = V DD 1+ V T V DSAT λ DSATp n λ p ( ) ( ) V IL = V DD 1 V T V DSAT λ n λ p
32 Noise Margins 4.4 = 5 V V t = 0.5 V V DSAT =1.0V λ=
33 Static Load Inverter V OUT V IN
34 Static Load Inverter V OUT V IN V t
35 Static Load Inverter Transistor is in saturation ( V I DS = k GS V T ) n ( 1+ λv DS ) V OUT = Rk n V OUT = V Rk V n IN T + λrk n V IN V T ( V IN V T ) ( 1+ λv OUT ) ( ) ( ) V IN V OUT
36 Static Load Inverter V OUT V IN V t
37 Static Load Inverter Transistor is in linear region I DS = k n ( V GS V T )V DS V DS V OUT = Rk n ( V IN V T )V OUT V OUT V IN V OUT Rk n V OUT ( Rk n ( V IN V T ) +1)V OUT + = 0 V OUT = ( V IN V T ) + 1 Rk n ( ) + 1 V IN V T Rk n Rk n
38 Static Load Inverter V OUT V IN V t
39 Static Load Inverter Noise Margin V IL = V T + 1 k n R V IH = V T k n R 1 k n R V t
40 Static Load Inverter Does not go down all the way to 0 Noise margins are tighter Switching threshold is not centered To get high gain in the transition region, you need bigger resistors
41 Homework Due February 3rd Read Chapter
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