Logic Gate Sizing. The method of logical effort. João Canas Ferreira. March University of Porto Faculty of Engineering

Transcription

1 Logic Gate Sizing The method of logical effort João Canas Ferreira University of Porto Faculty of Engineering March 016

2 Topics 1 Modeling CMOS Gates Chain of logic gates João Canas Ferreira (FEUP) Logic Gate Sizing March 016 /

3 Relative dimensions of logic gates A CMOS logic gate may be characterized by four parameters: 1 input capacitance C in intrinsic output capacitance C p 3 pull-up resistance R up 4 pull-down resistance R dn For each type of logic gate we can define a template (a reference gate) 1 input capacitance C t intrinsic output capacitance C pt 3 symmetric output resistance R t = R upt = R dnt For a sized gate (a larger): 1 C in = a C t R up = R dn = R out = R t /a 3 C p = a C pt João Canas Ferreira (FEUP) Logic Gate Sizing March /

4 Propagation delay model (1) Absolute propagation delay of a logic gate: t pabs = 0.69 R out (C out + C p ) = 0.69 R out C out R out C p For each gate type, this can be written in terms of the template: ( ) ( ) Rt C t pabs = 0.69 C out Rt a in (a C C in a pt ) t pabs = 0.69 R t C t f R t C pt Let s map this to an equation of the form t pabs = τ (g f + p) f = Cout /C in g = R t C t R (inv) t C (inv) t R t C pt p = R (inv) t C (inv) t (inv) τ = 0.69 R t C (inv) t (parameters of the template inverter) d = g f + p propagation delay in units of τ João Canas Ferreira (FEUP) Logic Gate Sizing March /

5 Propagation delay model () Gate delay Logical effort d = h + p h: effort delay p: intrinsic delay h = g f g: logical effort f: effective fan-out d = g f + p Logical effort depends only on gate topology, not its size. Intrinsic delay is constant for each gate type. Effective fan-out depends on the relation between load and input capacitance (size of the gate). By definition, g inv = 1. p inv = γ, the relation between input and output capacitance of the inverter. João Canas Ferreira (FEUP) Logic Gate Sizing March /

6 Definitions of logical effort The following definitions of logical effort are all equivalent: Definition 1: The logical effort of a gate is how many times the output current of that gate is lower than the output current of an inverter with the same input capacitance. Definition : The logical effort of a gate is given by the relation of its input capacitance to the input capacitance of an inverter with the same output current. Definition 3: The logical effort of a gate is given by the slope of its delay vs. fan-out curve divided by the slope of the corresponding curve for an inverter. João Canas Ferreira (FEUP) Logic Gate Sizing March /

7 Logical effort of some basic gates The logical effort of a gate is given by the relation of its input capacitance to the input capacitance of an inverter with the same output current. a 1 x a b x a b x (a) (b) (c) g=1 g=4/3 g=5/3 João Canas Ferreira (FEUP) Logic Gate Sizing March /

8 Summary of the logical effort of some basic gates Number of inputs 1 3 n inverter 1 nand 4/3 5/3 (n+)/3 nor 5/3 7/3 (n+1)/3 xor 4 1 João Canas Ferreira (FEUP) Logic Gate Sizing March /

9 Graphical model Source: [Sutherland99] (Illustrates definition 3) João Canas Ferreira (FEUP) Logic Gate Sizing March /

10 Estimation of the intrinsic delay The intrinsic delay of some type of logic gate is X times the intrinsic delay of the template inverter p inv where X is : the ratio between the sum of the diffusion areas (proportional to their widths) of sources or drains connected to the output node of the gate to the corresponding areas of the template inverter. (Condition for having the same output current as the template inverter.) p = ( ) W p 1 + β inv with β = (W/L) p (W/L) n Estimation assumes that all transistors have the same length of the diffusion areas (contacts as close as possible to the channel). For better results, calibrate the model from simulation data. João Canas Ferreira (FEUP) Logic Gate Sizing March /

11 Table of estimated intrinsic delays Gate Inverter n-input NAND n-input NOR n-input XOR or XNOR Intrinsic delay p inv n p inv n p inv n (n 1) p inv João Canas Ferreira (FEUP) Logic Gate Sizing March /

12 Examples Find the delay of the FO4 (fan-out of 4) inverter d = f g + p = p inv = = 5 Find the delay of a NOR4 gate that drives 10 identical gates d = f g + p = = 34 Find the frequency of oscillation of a ring with N identical inverters (N odd) For each inverter: Propagation delay around the ring: Frequency of oscillation: d = f g + p = p inv = F = T = N d τ 1 N d τ João Canas Ferreira (FEUP) Logic Gate Sizing March /

13 Topics 1 Modeling CMOS Gates Chain of logic gates João Canas Ferreira (FEUP) Logic Gate Sizing March /

14 Branching effort Problem: when sizing a logic path it is necessary to account for the loads imposed by gates that do not belong to that path. C i C on 1 C total a dimensionar When sizing the gates on the path, the size of logic gate 1 must take into account not just the load of gate, but also the load C off (which is constant as the gate is not being sized). C off Define b, the branching effort, as b = C path + C off C path Then, the effective fan-out of gate 1 is: f 1 = C path + C off C in = C path C in C path + C off C path = f percurso b João Canas Ferreira (FEUP) Logic Gate Sizing March /

15 Minimizing the delay of two gates Input capacitance: Logical effort: Parasitic delay: Gate 1 C 1 g 1 p 1 Gate C g p C 3 Source: [Sutherland99] D = (g 1 f 1 + p 1 ) + (g f + p ) f 1 = C f C = C 3 f 1 C 1 f = C 3 = F C 1 ( ) g F D = (g 1 f 1 + p 1 ) + + p f 1 In general δd = g δf 1 g F 1 f = 0 g 1 f 1 = g f 1 Delay is minimized when each stage has the same effort h = g f. This fact is independent of the size and intrinsic delays; it is valid for any number of stages and branching effort (included in f). João Canas Ferreira (FEUP) Logic Gate Sizing March /

16 Optimum delay For a path of N logic gates: f 1 f f N = BF with B = b 1 b b N Path effort: H = (g 1 f 1 )(g f ) (g N f N ) = GBF with G = g 1 g g N H does not depend on the size of the gates. The value of H is not changed by inserting inverters. All stages bear the same optimum effort ĥ: H = ĥ1/n or ĥ = N H The minimum delay is: ˆD = i (ĥ + p i ) = NH(1/N) + P with P = i p i João Canas Ferreira (FEUP) Logic Gate Sizing March /

17 Optimum number of stages Scenario: path with n 1 stages and n inverters, N = n 1 + n Assume you can change n, because it does not change the path effort (H) ˆD = NH (1/N) + ( n1 ) p i + (N n 1 )p inv δˆd δn = H(1/N) ln(h (1/N) ) + H (1/N) + p inv = 0 Let ρ be the stage effort delay for the optimum number of stages: ρ = H (1/ˆN) : i=1 p inv + ρ(1 ln(ρ)) = 0 The value of ρ that satisfies this equation is the stage effort delay (h) for all stages of the path: it is independent of other path characteristics. João Canas Ferreira (FEUP) Logic Gate Sizing March /

18 Pragmatic aspects If p inv = 0 then ρ = e =.718 Approximation: ρ 0.71 p inv +.8 For p inv = 1 we get ρ 3.59 Another approximation: ˆN log 4 (H) Use table: ( 1/ˆN ˆN ) H + p inv = ( ) (ˆN + 1) 1/(ˆN+1) H + pinv Fan-out of each stage: f i = ĥ/g i If there is branching at the output of that stage: f i = ĥ b g i p inv ˆN Path effort H João Canas Ferreira (FEUP) Logic Gate Sizing March /

19 Example: path optimization A C y z B C C C Source: [Sutherland99] C G = g 0 g 1 g = (4/3) 3 =.37 B = 1 F = 1 H =.37 ˆD = /3 +3 p inv = 10 ĥ = 4/3 z = C (4/3)/(4/3) = C y = C C Source: [Sutherland99] Assumes β = João Canas Ferreira (FEUP) Logic Gate Sizing March /

20 Example: implementation of a logic function g = g = 1 g = g = p = 8 p = 1 p = 4 p = (a ) D = N (FBG) 1/N + P (a) D = (3.33 F) 1/ + 9 (b) D = (3.33 F) 1/ + 6 (c) D = 4 (.86 F) 1/ g = 3 p = 5 g = 3 p = 4 g = 3 p = g = 1 p = 1 (b) F = 1: use (b) D = 9.65 F = 1: use (c) D = (c) Source: [Sutherland99] João Canas Ferreira (FEUP) Logic Gate Sizing March /

21 Logical effort: summary Determine the path effort: H = BFG Determine the optimum number of stages: N log 4 (H) Find the optimum stage effort delay: h = N H Draw the logic path Find the input capacitance of each gate: C in = C out b g h If necessary, find the sizes of the transistors (using information from the template). João Canas Ferreira (FEUP) Logic Gate Sizing March /

22 References Some figures come from the following books: Rabaey03 J. M. Rabaey et al, Digital Integrated Circuits, nd edition,prentice Hall, Sutherland99 I. Sutherland, B. Sproull and D. Harris, Logical Effort, Morgan Kaufmann Publishers, João Canas Ferreira (FEUP) Logic Gate Sizing March 016 /