# ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Size: px
Start display at page:

Download "ESE 570: Digital Integrated Circuits and VLSI Fundamentals"

Transcription

1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2018 Memory Overview, Memory Core Cells

2 Today! Charge Leakage/Charge Sharing " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification " ROM Memories " RAM Memory " Architecture " Memory core " SRAM " DRAM " Periphery (time permitting) Penn ESE 570 Spring Khanna 2

3 Charge Leakage

4 4

5 Charge Storage and Leakage 5

6 Example Overview: Min Hold Time! Find min voltage value for storage node to maintain data " V x = voltage across storage capacitor! With dimensions of switch MOS and load MOS " Calculate C ext = C gb + C int = C gb + C poly + C metal " Calculate C j = junction capacitance! With max leakage value " Calculate min hold time (i.e. min time for storage capacitor to leak to min V x ) min(t hold ) = Δt = C x min I leakage max ΔV x = C x min I leakage max (V x max V x min ) Penn ESE 570 Spring Khanna 6

7 Charge Sharing

8 Dynamic Circuit Techniques 8

9 Shift Register! Shift registers store and delay data! Simple design: cascade of latches D D- Latch ϕ 2 D- Latch ϕ 1 ϕ 1 D- Latch Out 9

10 Shift Register with Dynamic D Latches When V out(i) = 0V (or 5V) and V in(i+1) = 5V (or 0V) for i = 1,2 (stage) Charge Sharing is an issue when ϕ 1 /ϕ 2 close. 10

11 Charge Sharing V b >> V a 11

12 Charge Sharing V b >> V a 12

13 Charge Sharing Rule of Thumb make C out1 = 10 C in2 V b >> V a 13

14 Charge Sharing V b << V a 14

15 Charge Sharing V b << V a If V b = 0 and V a >> V b # V R C in2 C out1 + C in2 15

16 Charge Sharing V b << V a If V b = 0 and V a >> V b # V R C in2 C out1 + C in2 If C out1 >> C in2 # V R C in2 C out1 << 16

17 Charge Sharing Rule of Thumb make C out1 = 10 C in2 V b << V a If V b = 0 and V a >> V b # V R C in2 C out1 + C in2 If C out1 >> C in2 # V R C in2 C out1 << 17

18 Domino Logic Design Considerations

19 Requirements! Single transition " Once transitioned, it is done # like domino falling! All inputs at 0 during precharge " Outputs pre-charged to 1 then inverted to 0 " I.e. Inputs are pre-charge to 0! Non-inverting gates 19

20 Cascaded Domino CMOS Logic Gates propagating 20

21 Pre-charge Leakage weak keeper (W/L) p-keeper < (W/L) n-min 21

22 Charge Sharing within PDN 22

23 Charge Sharing within PDN 23

24 Charge Sharing within PDN 24

25 Charge Sharing within PDN 25

26 Charge Sharing within PDN 26

27 Charge Sharing within PDN Since all nodes are precharged there is no chargesharing. C 4 Z4 Z3 C 3 C 2 Z2 Z1 P0 C 1 Z1 = G1 + P1 * P0 Z2 = G2 + P2 * G1 + P2 * P1 * P0 = G2 + P2 * Z1 Z3 = G3 + P3 * G2 + P3 * P2 * G1 + P3 * P2 * P1 * P0 = G3 + P3 * Z2 Z4 = G4 + P4 * G3 + P4 * P3 * G2 + P4 * P3 * P2 * G1 + P4 * P3 *P1 * P0 = G4 + P4 * Z3 27

28 CMOS Logic! Best option in the majority of CMOS circuits! Advantages: " Noise-immunity not sensitive to k n /k p " does not involve pre-charging of nodes " dissipates no DC power " layout can be automated! Disadvantages: " Large fan-in gates lead to complex circuit structures (2N transistors) " larger parasitics " slower and higher dynamic power dissipation than alternatives " no clock and no synchronization. 28

29 Pseudo-nMOS/Ratioed Logic! Finds widest utility in large fan-in gates! Advantages: " Requires only N+1 transistors for N fan-in " smaller parasitics " faster and lower dynamic power dissipation than full CMOS! Disadvantages: " Noise-immunity sensitive to k n /k p " dissipates DC power when pulled down " not well-suited for automated layout " no clock and no synchronization. 29

30 CMOS domino-logic! Used for low-power, high-speed applications.! Advantages: " Requires N+k transistors for N fan-in (size advantages of pseudonmos) " dissipates no DC power " noise immunity not sensitive to k n /k p " use of clocks enables synchronous operation! Disadvantages: " Relies on storage on soft nodes " will require thorough simulation at all the process corners to insure proper operation " some of the speed advantage over static gates is diminished by the required pre-charge (pre-discharge) time 30

31 Memory Overview

32 CPU Memory Hierarchy CPU Chip L1 on-cpu cache 1k to 64 k SRAM (register file) off-chip cache memory L2 L3 L4 64k to 4M 4M to 32M 8M SRAM or DRAM 32

33 Locality and Cacheing! Memory hierarchies exploit locality by cacheing (keeping close to the processor) data likely to be used again! This is done because we can build " large, slow memories OR " small, fast memories BUT " we can t build large, fast memories! If hierarchy works, we get the illusion of SRAM access time with disk based memory capacity. " SRAM (static RAM) ns access time, very expensive (on-cpu faster) " DRAM (dynamic RAM) ns, cheaper " Disk -- access time measured in milliseconds, very cheap 33

34 Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM Penn ESE 570 Spring Khanna

35 Memory Architecture: Core M bits M bits N Words S 0 S 1 S 2 S N-2 S N_1 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell A 0 A 1 A K-1 Decoder S 0 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell Input-Output (M bits) Input-Output (M bits) N words => N select signals Too many select signals Decoder reduces # of select signals K = log 2 N Penn ESE 570 Spring Khanna

36 Memory Architecture: Decoders M bits M bits N Words S 0 S 1 S 2 S N-2 S N_1 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell A 0 A 1 A K-1 Decoder S 0 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell Input-Output (M bits) Input-Output (M bits) N words => N select signals Too many select signals Decoder reduces # of select signals K = log 2 N Penn ESE 570 Spring Khanna

37 Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH 2 L-K Bit Line Storage Cell A K A K+1 A L-1 Row Decoder Word Line Sense Amplifiers / Drivers M.2 K Amplify swing to rail-to-rail amplitude A 0 A K-1 Column Decoder Selects appropriate word Input-Output (M bits) Penn ESE 570 Spring Khanna

38 Latches/Register Can Store a State! Build master-slave register from pair of latches! Control with non-overlapping clocks Penn ESE 570 Spring Khanna 38

39 ROM Memories Penn ESE 570 Spring Khanna 39

40 MOS NOR ROM Pull-up devices WL[0] WL[1] GND WL[2] WL[3] GND BL[0] BL[1] BL[2] BL[3] Penn ESE 570 Spring Khanna

41 MOS NOR ROM Pull-up devices WL[0] WL[1] GND WL[2] WL[3] GND BL[0] BL[1] BL[2] BL[3] Penn ESE 570 Spring Khanna

42 MOS NOR ROM Pull-up devices WL[0] WL[1] GND WL[2] WL[3] GND BL[0] BL[1] BL[2] BL[3] Penn ESE 570 Spring Khanna

43 MOS NOR ROM Pull-up devices WL[0] WL[1] GND WL[2] GND WL[3] BL[0] BL[1] BL[2] BL[3] Penn ESE 570 Spring Khanna

44 MOS NOR ROM Pull-up devices WL[0] WL[1] GND WL[2] GND WL[3] BL[0] BL[1] BL[2] BL[3] Penn ESE 570 Spring Khanna

45 MOS NAND ROM BL[0] BL[1] BL[2] BL[3] Pull-up devices WL[0] WL[1] WL[2] WL[3] All word lines high by default with exception of selected row Penn ESE 570 Spring Khanna

46 MOS NAND ROM BL[0] BL[1] BL[2] BL[3] Pull-up devices WL[0] WL[1] WL[2] WL[3] All word lines high by default with exception of selected row Penn ESE 570 Spring Khanna

47 MOS NAND ROM Pull-up devices WL[0] WL[1] 0 BL[0] BL[1] BL[2] BL[3] WL[2] WL[3] All word lines high by default with exception of selected row Penn ESE 570 Spring Khanna

48 MOS NAND ROM Pull-up devices WL[0] WL[1] WL[2] WL[3] BL[0] BL[1] BL[2] BL[3] All word lines high by default with exception of selected row Penn ESE 570 Spring Khanna

49 Non-Volatile Memory ROM PseudonMOS NOR gate 49

50 Contact-Mask Programmable ROM 50

51 Contact-Mask Programmable ROM 51

52 Read-Write Memories (RAM)! Static (SRAM) " Data stored as long as supply is applied " Large (6 transistors/cell) " Fast " Differential! Dynamic (DRAM) " Periodic refresh required " Small (1-3 transistors/cell) " Slower " Single ended Penn ESE 570 Spring Khanna

53 6T SRAM Cell! Cell size accounts for most of memory array size! 6T SRAM Cell " Used in most commercial chips " Data stored in cross-coupled inverters! Read: " Precharge BL, BL BL bit " Raise WL word WL! Write: " Drive data onto BL, BL " Raise WL BL bit_b 53

54 6-transistor CMOS SRAM Cell WL M2 M4 M5 Q Q M6 M1 M3 BL BL Penn ESE 570 Spring Khanna

55 6-transistor CMOS SRAM Cell WL M2 M4 M5 Q Q M6 M1 M3 BL BL Penn ESE 570 Spring Khanna

56 6-transistor CMOS SRAM Cell WL Assume 1 is stored (Q=1) M5 M2 Q 0 M4 Q 1 M6 M1 M3 BL BL Penn ESE 570 Spring Khanna

57 CMOS SRAM Analysis (stored 1) WL BL M4 BL M5 0 Q = 0 1 Q = 1 M6 M1 C bit C bit Penn ESE 570 Spring Khanna

58 6-transistor CMOS SRAM Cell WL Assume 1 is stored (Q=1) Read Operation: - First bitlines get VDD precharged high (Vdd) - Then wordline goes high (Vdd) BL M5 M2 Q 0 M1 M4 M3 Q 1 M6 BL VDD Penn ESE 570 Spring Khanna

59 CMOS SRAM Analysis (Read) VDD WL BL M4 BL M5 0 Q = 0 1 Q = 1 M6 VDD V M1 VDD C bit C bit Penn ESE 570 Spring Khanna

60 CMOS SRAM Analysis (Read) VDD WL BL M4 BL M5 0 Q = 0 1 Q = 1 M6 VDD V M1 VDD C bit C bit ( ) 2 = k n,m1 ( V Tn )ΔV ΔV 2 k n,m5 ΔV V Tn 2 Penn ESE 570 Spring Khanna

61 CMOS SRAM Analysis (Read) VDD WL BL M4 BL M5 0 Q = 0 1 Q = 1 M6 VDD V M1 VDD C bit C bit k n,m 1 k n,m 5 = W L W L 1 5 = ( ΔV V Tn ) 2 ( V Tn )ΔV ΔV 2 2 Penn ESE 570 Spring Khanna

62 CMOS SRAM Analysis (Read) VDD WL BL M4 BL M5 0 Q = 0 1 Q = 1 M6 VDD V M1 VDD C bit C bit k n,m 1 k n,m 5 = W L W L Penn ESE 570 Spring Khanna 1 5 = ( ΔV V Tn ) 2 ( V Tn )ΔV ΔV 2 2 ΔV =V Tn W L W L 1 5 = ( 2V Tn ) 2 ( 1.5V Tn )V Tn

63 CMOS SRAM Analysis (Read) Voltage Rise (V) Cell Ratio (CR) 2.5 3

64 CMOS SRAM Analysis (Read) VDD WL BL M4 BL M5 0 Q = 0 1 Q = 1 M6 VDD V M1 VDD C bit C bit Penn ESE 570 Spring Khanna

65 6-transistor CMOS SRAM Cell WL Assume 1 is stored (Q=1) Write Operation: - Want to write a 0 VDD - First drive bitlines with input data - Then wordline goes high (Vdd) BL M5 M2 Q 0 M1 M4 M3 Q 1 M6 BL 0 Penn ESE 570 Spring Khanna

66 CMOS SRAM Analysis (Write) VDD WL M4 M5 0 Q = 0 Q = 1 1 M6 M1 VDD BL = 1 0 BL = 0 Penn ESE 570 Spring Khanna

67 CMOS SRAM Analysis (Write) VDD WL M4 M5 0 Q = 0 Q = 1 1 M6 M1 VDD BL = 1 0 BL = 0 ( ) 2 = k n,m 4 ( V Tp )V Q V Q k n,m 6 V Tn 2 2 Penn ESE 570 Spring Khanna

68 CMOS SRAM Analysis (Write) VDD WL M4 M5 0 Q = 0 Q = 1 1 M6 M1 VDD BL = 1 0 BL = 0 k n,m 4 k n,m 6 = ( V Tn ) 2 ( V Tp )V Q V 2 Q 2 Penn ESE 570 Spring Khanna

69 CMOS SRAM Analysis (Write) VDD WL M5 0 Q = 0 M4 Q = 1 1 M6 PR = W 4 L 4 W 6 L 6 M1 VDD BL = 1 0 BL = 0 k n,m 4 k n,m 6 = ( V Tn ) 2 ( V Tp )V Q V 2 Q 2 Penn ESE 570 Spring Khanna V Q =V Tn k n,m 4 k n,m 6 = ( V Tn ) 2 ( V Tp )V Tn V 2 Tn 2

70 CMOS SRAM Analysis (Write) PR = W 4 L 4 W 6 L 6

71 CMOS SRAM Analysis (Write) VDD WL M5 0 Q = 0 M4 Q = 1 1 M6 PR = W 4 L 4 W 6 L 6 M1 VDD BL = 1 0 BL = 0 Penn ESE 570 Spring Khanna

72 DRAM! Smaller than SRAM! Require data refresh to compensate for leakage 72

73 3-Transistor DRAM Cell BL1 BL2 WWL RWL WWL RWL M1 X M2 M3 X BL1 -V T C S BL2 -V T ΔV No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = V WWL -V Tn

74 1-Transistor DRAM Cell BL WL WL Write "1" Read "1" M1 C S X GND V T C BL BL /2 sensing /2 Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance C ΔV V BL V ( PRE V BIT V ) S = = PRE C S + C BL Voltage swing is small; typically around 250 mv.

75 DRAM Cell Observations! 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out! DRAM memory cells are single ended in contrast to SRAM cells! The read-out of the 1T DRAM cell is destructive " Read and refresh operations are necessary for correct operation! Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design! When writing a 1 into a DRAM cell, a threshold voltage is lost " This charge loss can be circumvented by bootstrapping the word lines to a higher value than

76 Idea! Memory for compact state storage! Share circuitry across many bits " Minimize area per bit # maximize density! Aggressively use: " Pass transistors, Ratioing " Precharge, Amplifiers to keep area down Penn ESE 570 Spring Khanna 76

77 Admin! Homework 7 due Thursday! Final Project " Design and layout memory " Handout posted before Thursday class " Due 4/24 (last day of class) " Everyone gets an extension until 5/4 " Keep in mind our final exam is on 4/30 " Leave time to study! Penn ESE 570 Spring Khanna 77

### ! Charge Leakage/Charge Sharing. " Domino Logic Design Considerations. ! Logic Comparisons. ! Memory. " Classification. " ROM Memories.

ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification

More information

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 21: April 4, 2017 Memory Overview, Memory Core Cells Penn ESE 570 Spring 2017 Khanna Today! Memory " Classification " ROM Memories " RAM Memory

More information

### ! Memory. " RAM Memory. ! Cell size accounts for most of memory array size. ! 6T SRAM Cell. " Used in most commercial chips

ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec : April 3, 8 Memory: Core Cells Today! Memory " RAM Memory " Architecture " Memory core " SRAM " DRAM " Periphery Penn ESE 57 Spring 8 - Khanna

More information

### Topics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut

Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance

More information

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " D-Latch " Timing Constraints! Dynamic Logic " Domino

More information

### EE241 - Spring 2000 Advanced Digital Integrated Circuits. References

EE241 - Spring 2000 Advanced Digital Integrated Circuits Lecture 26 Memory References Rabaey, Digital Integrated Circuits Memory Design and Evolution, VLSI Circuits Short Course, 1998.» Gillingham, Evolution

More information

### Digital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories

Digital Integrated Circuits A Design Perspective Semiconductor Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification

More information

### Semiconductor Memory Classification

Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH

More information

### Semiconductor Memories

Semiconductor References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian

More information

### Lecture 25. Semiconductor Memories. Issues in Memory

Lecture 25 Semiconductor Memories Issues in Memory Memory Classification Memory Architectures TheMemoryCore Periphery 1 Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access

More information

### Digital Integrated Circuits A Design Perspective

Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures

More information

### GMU, ECE 680 Physical VLSI Design 1

ECE680: Physical VLSI Design Chapter VIII Semiconductor Memory (chapter 12 in textbook) 1 Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies

More information

### SEMICONDUCTOR MEMORIES

SEMICONDUCTOR MEMORIES Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM

More information

### Semiconductor memories

Semiconductor memories Semiconductor Memories Data in Write Memory cell Read Data out Some design issues : How many cells? Function? Power consuption? Access type? How fast are read/write operations? Semiconductor

More information

### Semiconductor Memories

!"#"\$%&'()\$*#+%\$*,' -"+./"\$0 1'!*0"#)'2*+03*.\$"4* Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Semiconductor Memories December 20, 2002 !"#\$%&'()*&'*+&, Memory Classification Memory Architectures

More information

### Hw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today

EECS141 1 Hw 8 Posted Last one to be graded Due Friday April 30 Hw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today EECS141 2 1 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 Frequency

More information

### Magnetic core memory (1951) cm 2 ( bit)

Magnetic core memory (1951) 16 16 cm 2 (128 128 bit) Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM

More information

### Chapter Overview. Memory Classification. Memory Architectures. The Memory Core. Periphery. Reliability. Memory

SRAM Design Chapter Overview Classification Architectures The Core Periphery Reliability Semiconductor Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable

More information

### EE141- Fall 2002 Lecture 27. Memory EE141. Announcements. We finished all the labs No homework this week Projects are due next Tuesday 9am EE141

- Fall 2002 Lecture 27 Memory Announcements We finished all the labs No homework this week Projects are due next Tuesday 9am 1 Today s Lecture Memory:» SRAM» DRAM» Flash Memory 2 Floating-gate transistor

More information

### Semiconductor Memories. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Paolo Spirito

Semiconductor Memories Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Paolo Spirito Memory Classification Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random

More information

### CMOS Digital Integrated Circuits Lec 13 Semiconductor Memories

Lec 13 Semiconductor Memories 1 Semiconductor Memory Types Semiconductor Memories Read/Write (R/W) Memory or Random Access Memory (RAM) Read-Only Memory (ROM) Dynamic RAM (DRAM) Static RAM (SRAM) 1. Mask

More information

### Semiconductor Memories

Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Semiconductor Memories December 20, 2002 Chapter Overview Memory Classification Memory Architectures

More information

### Administrative Stuff

EE141- Spring 2004 Digital Integrated Circuits Lecture 30 PERSPECTIVES 1 Administrative Stuff Homework 10 posted just for practice. No need to turn in (hw 9 due today). Normal office hours next week. HKN

More information

### Semiconductor Memories

Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Semiconductor Memories December 20, 2002 Chapter Overview Memory Classification Memory Architectures

More information

### Memory Trend. Memory Architectures The Memory Core Periphery

Semiconductor Memories: an Introduction ti Talk Overview Memory Trend Memory Classification Memory Architectures The Memory Core Periphery Reliability Semiconductor Memory Trends (up to the 90 s) Memory

More information

### EE141Microelettronica. CMOS Logic

Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit

More information

### COMP 103. Lecture 16. Dynamic Logic

COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03

More information

### EE141-Fall 2011 Digital Integrated Circuits

EE4-Fall 20 Digital Integrated Circuits Lecture 5 Memory decoders Administrative Stuff Homework #6 due today Project posted Phase due next Friday Project done in pairs 2 Last Lecture Last lecture Logical

More information

### CMOS Inverter. Performance Scaling

Announcements Exam #2 regrade requests due today. Homework #8 due today. Final Exam: Th June 12, 8:30 10:20am, CMU 120 (extension to 11:20am requested). Grades available for viewing via Catalyst. CMOS

More information

### ECE520 VLSI Design. Lecture 23: SRAM & DRAM Memories. Payman Zarkesh-Ha

ECE520 VLSI Design Lecture 23: SRAM & DRAM Memories Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture

More information

### EE141. EE141-Spring 2006 Digital Integrated Circuits. Administrative Stuff. Class Material. Flash Memory. Read-Only Memory Cells MOS OR ROM

EE141-pring 2006 igital Integrated Circuits Lecture 29 Flash memory Administrative tuff reat job on projects and posters! Homework #10 due today Lab reports due this week Friday lab in 353 Final exam May

More information

### Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic

More information

### Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo

Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic

More information

### 9/18/2008 GMU, ECE 680 Physical VLSI Design

ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design

More information

### ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018

ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΔΙΑΛΕΞΗ 11: Dynamic CMOS Circuits ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) (ack: Prof. Mary Jane Irwin and Vijay Narayanan) [Προσαρμογή από

More information

### Semiconductor Memories

Introduction Classification of Memory Devices "Combinational Logic" Read Write Memories Non Volatile RWM Read Only Memory Random Access Non-Random Access Static RAM FIFO Dynamic RAM LIFO Shift Register

More information

### MODULE 5 Chapter 7. Clocked Storage Elements

MODULE 5 Chapter 7 Clocked Storage Elements 3/9/2015 1 Outline Background Clocked Storage Elements Timing, terminology, classification Static CSEs Latches Registers Dynamic CSEs Latches Registers 3/9/2015

More information

### Chapter 7. Sequential Circuits Registers, Counters, RAM

Chapter 7. Sequential Circuits Registers, Counters, RAM Register - a group of binary storage elements suitable for holding binary info A group of FFs constitutes a register Commonly used as temporary storage

More information

### EECS 141 F01 Lecture 17

EECS 4 F0 Lecture 7 With major inputs/improvements From Mary-Jane Irwin (Penn State) Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND

More information

### Memory, Latches, & Registers

Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) How to save a few bucks at toll booths 5) Edge-triggered Registers L13 Memory 1 General Table Lookup Synthesis

More information

### Dynamic Combinational Circuits. Dynamic Logic

Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic np-cmos (zipper CMOS) Krish Chakrabarty 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:

More information

### Name: Answers. Mean: 83, Standard Deviation: 12 Q1 Q2 Q3 Q4 Q5 Q6 Total. ESE370 Fall 2015

University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Final Tuesday, December 15 Problem weightings

More information

### CMPEN 411 VLSI Digital Circuits Spring Lecture 21: Shifters, Decoders, Muxes

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 21: Shifters, Decoders, Muxes [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11 CMPEN

More information

### F14 Memory Circuits. Lars Ohlsson

Lars Ohlsson 2018-10-18 F14 Memory Circuits Outline Combinatorial vs. sequential logic circuits Analogue multivibrator circuits Noise in digital circuits CMOS latch CMOS SR flip flop 6T SRAM cell 1T DRAM

More information

### C.K. Ken Yang UCLA Courtesy of MAH EE 215B

Decoders: Logical Effort Applied C.K. Ken Yang UCLA yang@ee.ucla.edu Courtesy of MAH 1 Overview Reading Rabaey 6.2.2 (Ratio-ed logic) W&H 6.2.2 Overview We have now gone through the basics of decoders,

More information

### Topics to be Covered. capacitance inductance transmission lines

Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of

More information

### Dynamic Combinational Circuits. Dynamic Logic

Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic np-cmos (zipper CMOS) Krish Chakrabarty 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:

More information

### Power Dissipation. Where Does Power Go in CMOS?

Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit

More information

### COMBINATIONAL LOGIC. Combinational Logic

COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-cmos Combinational vs. Sequential Logic In Logic

More information

### CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,

More information

### CMSC 313 Lecture 25 Registers Memory Organization DRAM

CMSC 33 Lecture 25 Registers Memory Organization DRAM UMBC, CMSC33, Richard Chang A-75 Four-Bit Register Appendix A: Digital Logic Makes use of tri-state buffers so that multiple registers

More information

### Pass-Transistor Logic

-all 26 Digital tegrated ircuits nnouncements No new homework this week roject phase one due on Monday Midterm 2 next Thursday Review session on Tuesday Lecture 8 Logic Dynamic Logic EE4 EE4 2 lass Material

More information

### Introduction to Computer Engineering. CS/ECE 252, Fall 2012 Prof. Guri Sohi Computer Sciences Department University of Wisconsin Madison

Introduction to Computer Engineering CS/ECE 252, Fall 2012 Prof. Guri Sohi Computer Sciences Department University of Wisconsin Madison Chapter 3 Digital Logic Structures Slides based on set prepared by

More information

### S No. Questions Bloom s Taxonomy Level UNIT-I

GROUP-A (SHORT ANSWER QUESTIONS) S No. Questions Bloom s UNIT-I 1 Define oxidation & Classify different types of oxidation Remember 1 2 Explain about Ion implantation Understand 1 3 Describe lithography

More information

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler

More information

### Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: Two-Input NOR Gate (NOR2)

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 14: March 1, 2016 Combination Logic: Ratioed and Pass Logic Lecture Outline! CMOS Gates Review " CMOS Worst Case Analysis! Ratioed Logic Gates!

More information

### ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.

More information

### CMPEN 411. Spring Lecture 18: Static Sequential Circuits

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 18: Static Sequential Circuits [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11

More information

### University of Toronto. Final Exam

University of Toronto Final Exam Date - Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last

More information

### ALU A functional unit

ALU A functional unit that performs arithmetic operations such as ADD, SUB, MPY logical operations such as AND, OR, XOR, NOT on given data types: 8-,16-,32-, or 64-bit values A n-1 A n-2... A 1 A 0 B n-1

More information

### EE 434 Lecture 33. Logic Design

EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The two-inverter loop X Y X

More information

### Last Lecture. Power Dissipation CMOS Scaling. EECS 141 S02 Lecture 8

EECS 141 S02 Lecture 8 Power Dissipation CMOS Scaling Last Lecture CMOS Inverter loading Switching Performance Evaluation Design optimization Inverter Sizing 1 Today CMOS Inverter power dissipation» Dynamic»

More information

### Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!

More information

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 2: January 17, 2017 MOS Fabrication pt. 1: Physics and Methodology Lecture Outline! Digital CMOS Basics! VLSI Fundamentals! Fabrication Process

More information

### ECE251. VLSI System Design

ECE251. VLSI System Design Project 4 SRAM Cell and Memory Array Operation Area Memory core 4661 mm 2 (256bit) Row Decoder 204.7 mm 2 Collumn Decoder Overall Design Predecoder 156.1 mm 2 Mux 629.2 mm 2

More information

### Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements.

1 2 Introduction Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. Defines the precise instants when the circuit is allowed to change

More information

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 2: January 19, 2016 MOS Fabrication pt. 1: Physics and Methodology Lecture Outline! Digital CMOS Basics! VLSI Fundamentals! Fabrication Process

More information

### ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018

ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΔΙΑΛΕΞΕΙΣ 12-13: esigning ynamic and Static CMOS Sequential Circuits ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) (ack: Prof. Mary Jane Irwin and

More information

### EE115C Winter 2017 Digital Electronic Circuits. Lecture 6: Power Consumption

EE115C Winter 2017 Digital Electronic Circuits Lecture 6: Power Consumption Four Key Design Metrics for Digital ICs Cost of ICs Reliability Speed Power EE115C Winter 2017 2 Power and Energy Challenges

More information

### Random Access Memory. DRAM & SRAM Design DRAM SRAM MS635. Dynamic Random Access Memory. Static Random Access Memory. Cell Structure. 6 Tr.

DRAM & SRAM Design Random Access Memory Volatile memory Random access is possible if you know the address DRAM DRAM Dynamic Random Access Memory SRAM Static Random Access Memory SRAM Cell Structure Power

More information

### LOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.

Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor

More information

### Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Designing Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL

More information

### MTJ-Based Nonvolatile Logic-in-Memory Architecture and Its Application

2011 11th Non-Volatile Memory Technology Symposium @ Shanghai, China, Nov. 9, 20112 MTJ-Based Nonvolatile Logic-in-Memory Architecture and Its Application Takahiro Hanyu 1,3, S. Matsunaga 1, D. Suzuki

More information

### EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University

EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar

More information

### Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power

- Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances

More information

### Lecture 24. CMOS Logic Gates and Digital VLSI II

ecture 24 CMOS ogic Gates and Digital VSI II In this lecture you will learn: Static CMOS ogic Gates FET Scaling CMOS Memory, SRM and DRM CMOS atches, and Registers (Flip-Flops) Clocked CMOS CCDs CMOS ogic:

More information

### WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays

WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays Mahadevan Gomathisankaran Iowa State University gmdev@iastate.edu Akhilesh Tyagi Iowa State University tyagi@iastate.edu ➀ Introduction

More information

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 13, 2017 Variation; I/O Circuits, Inductive Noise Lecture Outline! Design Quality " Variation! Packaging! Variation and Testing!

More information

### Spiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp

2-7.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 2-7.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance

More information

### Lecture 16: Circuit Pitfalls

Introduction to CMOS VLSI Design Lecture 16: Circuit Pitfalls David Harris Harvey Mudd College Spring 2004 Outline Pitfalls Detective puzzle Given circuit and symptom, diagnose cause and recommend solution

More information

### Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Total Power. Energy and Power Optimization. Worksheet Problem 1

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 20, 2018 Energy and Power Optimization, Design Space Exploration Lecture Outline! Energy and Power Optimization " Tradeoffs! Design

More information

### Lecture 34: Portable Systems Technology Background Professor Randy H. Katz Computer Science 252 Fall 1995

Lecture 34: Portable Systems Technology Background Professor Randy H. Katz Computer Science 252 Fall 1995 RHK.F95 1 Technology Trends: Microprocessor Capacity 100000000 10000000 Pentium Transistors 1000000

More information

### Clock Strategy. VLSI System Design NCKUEE-KJLEE

Clock Strategy Clocked Systems Latch and Flip-flops System timing Clock skew High speed latch design Phase locked loop ynamic logic Multiple phase Clock distribution Clocked Systems Most VLSI systems are

More information

### 5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1

5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design

More information

### and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

More information

### EE241 - Spring 2000 Advanced Digital Integrated Circuits. Announcements

EE241 - Spring 2 Advanced Digital Integrated Circuits Lecture 11 Low Power-Low Energy Circuit Design Announcements Homework #2 due Friday, 3/3 by 5pm Midterm project reports due in two weeks - 3/7 by 5pm

More information

### CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed

More information

### CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411

More information

### Digital Integrated Circuits A Design Perspective

Designing ombinational Logic ircuits dapted from hapter 6 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 ombinational vs. Sequential Logic In

More information

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 23, 2017 Energy and Power Optimization, Design Space Exploration, Synchronous MOS Logic Lecture Outline! Energy and Power Optimization

More information

### EE 330 Lecture 37. Digital Circuits. Other Logic Families. Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates)

EE 330 Lecture 37 Digital Circuits Other Logic Families Static Power Dissipation Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates) Review from Last Time Inverter

More information

### Topic 4. The CMOS Inverter

Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Topic 4-1 Noise in Digital Integrated

More information

### Digital Integrated Circuits Lecture 14: CAMs, ROMs, and PLAs

Digital Integrated Circuits Lecture 4: CAMs, ROMs, and PLAs Chih-Wei Liu VLSI Signal Processing LAB National Chiao Tung University cwliu@twins.ee.nctu.edu.tw DIC-Lec4 cwliu@twins.ee.nctu.edu.tw Outline

More information

### ECE321 Electronics I

ECE321 Electronics I Lecture 1: Introduction to Digital Electronics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 Textbook

More information

### Moores Law for DRAM. 2x increase in capacity every 18 months 2006: 4GB

MEMORY Moores Law for DRAM 2x increase in capacity every 18 months 2006: 4GB Corollary to Moores Law Cost / chip ~ constant (packaging) Cost / bit = 2X reduction / 18 months Current (2008) ~ 1 micro-cent

More information

### Lecture 3 Review on Digital Logic (Part 2)

Lecture 3 Review on Digital Logic (Part 2) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ ircuit Optimization Simplest implementation ost criterion literal

More information

### THE INVERTER. Inverter

THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)

More information

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 15, 2018 MOS Inverter: Dynamic Characteristics Penn ESE 570 Spring 2018 Khanna Lecture Outline! Inverter Power! Dynamic Characteristics

More information

### Chapter 5 CMOS Logic Gate Design

Chapter 5 CMOS Logic Gate Design Section 5. -To achieve correct operation of integrated logic gates, we need to satisfy 1. Functional specification. Temporal (timing) constraint. (1) In CMOS, incorrect

More information

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 17, 2018 I/O Circuits, Inductive Noise, CLK Generation Lecture Outline! Packaging! Variation and Testing! I/O Circuits! Inductive

More information