# 9/18/2008 GMU, ECE 680 Physical VLSI Design

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1 ECE680: Physical VLSI esign Chapter IV esigning Sequential Logic Circuits (Chapter 7) 1

2 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state 2 storage mechanisms positive feedback charge based 2

3 In our text: Naming Conventions a latch is level sensitive a register is edge triggered gg There are many different naming conventions For instance, many books call edge triggered elements flip flops This leads to confusion however 3

4 Latch versus Register Latch stores data when clock is low Register stores data when clock rises Clk Clk Clk Clk 4

5 Latches Positive Latch Negative Latch In G Out In Out G clk In Out clk In Out Out stable Out follows In Out stable Out follows In 5

6 Latch Based esign N latch is transparent Pl latch his transparent when φ = 0 when φ = 1 φ N Latch Logic P Latch Logic 6

7 Timing efinitions t su t hold t Register ATA STABLE t t c 2 q ATA STABLE t 7

8 Characterizing Timing t 2 Clk Clk Register t C 2 t C 2 Latch 8

9 Maximum Clock Frequency φ FF s LOGIC t p,comb t clk- + t p,comb + t setup = T Also: t cdreg + t cdlogic > t hold t cd : contamination delay = minimum delay 9

10 Positive Feedback: Bi Stability V i1 V o1 =V i2 V o2 V o1 V o1 V i2 5Vo1 i2 V V o2 =V i1 V i1 V o2 V i2 =V o1 V o1 5 V i 2 A 5 C B V i1 =V o2 10

11 Meta Stability o1 V i2 5V o A o1 V i2 5V o A C C B B V d i1 5 V o2 V d i1 5 V o2 Gain should be larger than 1 in the transition region 11

12 Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states Converting into a MUX Forcing the state (can implement as NMOS-only) 12

13 Mux Based Latches Negative latch (transparent when = 0) Positive latch (transparent when = 1) = Clk + Clk In = Clk + Clk In 13

14 Mux Based Latch 14

15 Mux Based Latch M M NMOS only Non-overlapping clocks 15

16 Master Slave (Edge Triggered) Register Master Slave M 1 M Two opposite latches trigger on edge Also called master-slave latch pair 16

17 Master Slave Register Multiplexer-based l latch pair I 2 T 2 I 3 I 5 T 4 I 6 M I 1 T 1 I 4 T 3 17

18 Clk elay 2.5 Volts t c 2 q(lh) t c 2 q(hl) time, nsec 18

19 Setup Time M 2.0 I 2 2 T 2 Volts I 2 2 T 2 Volts M time (nsec) time (nsec) (a) T setup nsec (b) T setup nsec 19

20 Reduced Clock Load Master Slave Register T 1 I 1 T 2 I 3 I 2 I 4 20

21 Avoiding Clock Overlap X A B (a) Schematic diagram (b) Overlapping clock pairs 21

22 Overpowering the Feedback Loop NOR-based set-reset Cross Coupled Pairs S S S R 0 0 R R Forbidden State 22

23 Cross Coupled NAN Cross-coupled NANs Added clock V S M 2 M 4 M R 6 M 8 M 1 M 3 S M 5 M 7 R This is not used in datapaths any more, but is a basic building memory cell 23

24 Sizing Issues S W = 0.5 μm (V Volts) W/L 5 and Vo olts 1 0 W = 1 μm W = 0.6 μm W = 0.7 μm W = 0.8 μm W = 0.9 μm time (ns) (a) (b) Output voltage dependence on transistor t width Transient response 24

25 Storage Mechanisms Static ynamic (charge-based) 25

26 Making a ynamic Latch Pseudo Static 26

27 More Precise Setup Time Clk t t (a) t 1.05t C 2 t C 2 t Su t 2 C t H (b) 27

28 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 CP T Clk- ata Clock T Setup-1 Time T Setup-1 t=0 Time 28

29 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 CP T Clk- ata Clock T Setup-1 Time T Setup-1 t=0 Time 29

30 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 CP T Clk- ata Clock T Setup-1 Time T Setup-1 t=0 Time 30

31 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 T Clk- CP ata Clock T Setup-1 Time T Setup-1 t=0 Time 31

32 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay T Clk- Inv1 CP ata Clock T Setup-1 Time T Setup-1 t=0 Time 32

33 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 CP 0 T Clk- Clock ata T Hold-1 Time T Hold-1 t=0 Time 33

34 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 CP 0 T Clk- Clock ata T Hold-1 Time T Hold-1 t=0 Time 34

35 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 CP 0 T Clk- T Hold-1 Time Clock ata T Hold-1 t=0 Time 35

36 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 T Clk- CP 0 Clock ata T Hold-1 T Hold-1 Time t=0 Time 36

37 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M T Clk- Clk- elay Inv1 CP 0 Clock ata T Hold-1 T Hold-1 Time t=0 Time 37

38 Other Latches/Registers: C 2 MOS V V M 2 M 6 M 4 M 8 X C M L1 3 M 7 C L2 M 1 M 5 Master Stage Slave Stage Keepers can be added d to make circuit it pseudo-static ti 38

39 Insensitive to Clock Overlap V V V V M 2 M 6 M 2 M 6 0 M 4 0 X M 8 X 1 M 3 1 M 7 M 1 M 5 M 1 M 5 (a) (0 0) overlap (b) (1 1) overlap 39

40 Pipelining a RE EG a RE EG log REG Out REG REG log REG Out b RE EG b RE EG Rf Reference Pipelined 40

41 Other Latches/Registers: TSPC V V V V In In Out Out Positive latch (transparent when = 1) Negative latch (transparent when = 0) 41

42 Including Logic in TSPC V V V V PUN In 1 In 2 In PN In 1 In 2 Example: logic inside the latch AN latch 42

43 TSPC Register V V V M 3 M 6 M 9 Y M 2 X M 5 M 8 M 1 M 4 M 7 43

44 Pulse Triggered Latches An Alternative Approach Ways to design an edge-triggered dsequential cell: Master Slave SlaveLatches Pulse Triggered Latch ata L1 L2 L ata Clk Clk Clk Clk Clk 44

45 Pulsed Latches V V M 3 M 6 V G M 2 G M5 M P X G M M1 M N 4 M M (a) register (b) glitch generation G (c) glitch clock 45

46 Pulsed Latches Hybrid Latch Flip-flop (HLFF), AM K-6 and K-7 : P 1 P 3 x M 3 M 6 M 2 P 2 M 5 M 1 M 4 46

47 Hybrid Latch FF Timing lts Vo time (ns) 47

48 Latch Based Pipeline In F G Out C 1 C 2 C 3 Compute F compute G 48

49 Non Bistable Sequential Circuits Schmitt Trigger In Out V ou t V OH VTC with hysteresis V OL Restores signal slopes V M V M+ V in 49

50 Noise Suppression using Schmitt Trigger V in V out V M+ V M t 0 t t 0 + t p t 50

51 CMOS Schmitt Trigger V M 2 M 4 V in X V out M 1 M 3 Moves switching threshold of the first inverter 51

52 Schmitt Trigger Simulated VTC V M1 1.5 (V) V X(V) 1.0 V M2 1.0 V x(v) k= 1 k= 2 k= k= V in (V) V in (V) Vlt Voltage-transfer t characteristics ti with hysteresis. The effect of varying the ratio of fthe PMOS device M 4. The width is k* 0.5 m m. 52

53 CMOS Schmitt Trigger (2) V M 4 M 6 M 3 M 6 In Out M 2 X M 5 V M 1 53

54 Multivibrator Circuits R S Bistable Multivibrator flip-flop, Schmitt Trigger T Monostable Multivibrator one-shot Astable Multivibrator oscillator 54

55 Transition Triggered Monostable In ELAY t d Out t d 55

56 Monostable Trigger (RC based) V In A R B Out C (a) Trigger circuit. In B V M (b) Waveforms. Out t t 1 t 2 56

57 Astable Multivibrators (Oscillators) N V 1 V 3 V 5 Ring Oscillator 2.0 Volts time (ns) simulated response of 5 stage oscillator 57

58 Relaxation Oscillator Out 1 Out 2 I1 I2 R C Int T = 2 (log3) RC 58

59 Voltage Controller Oscillator (VCO) V M6 V M4 Schmitt Trigger restores signal slopes In M2 I ref M1 I ref V contr M5 M3 Current starved inverter 6 t ph L (nsec) V contr (V) propagation delay as a function of control voltage 59

60 ifferential elay Element and VCO in1 V o 2 V o 1 in2 v 1 v 3 1 v 2 v 4 V ctrl delay cell 3.0 two stage VCO 2.5 V 1 V 2 V 3 V time (ns) simulated waveforms of 2 stage VCO 60

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