Lecture 14: Circuit Families


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1 Introduction to CMOS VLSI Design Lecture 4: Circuit Families David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh
2 Outline q PseudonMOS Logic q Dynamic Logic q Pass Transistor Logic Slide 2
3 Introduction q What makes a circuit fast? I C dv/dt > t pd (C/I) ΔV low capacitance high current small swing q Logical effort is proportional to C/I q pmos are the enemy! High capacitance for a given current q Can we take the pmos capacitance off the input? q Various circuit families try to do this B 4 4 Slide 3
4 PseudonMOS q In the old days, nmos processes had no pmos Instead, use pullup transistor that is always ON q In CMOS, use a pmos that is always ON Ratio issue Make pmos about ¼ effective strength of.8 pulldown network load I ds P/2 V out P 24 V in 6/2 V out P 4 P V in Slide 4
5 PseudonMOS Gates q Design for unit current on output to compare with unit inverter. q pmos fights nmos inputs f Inverter NND2 NOR2 g u g avg p u p avg B g u g avg p u p avg B g u g avg p u p avg Slide 5
6 PseudonMOS Gates q Design for unit current on output to compare with unit inverter. q pmos fights nmos inputs f Inverter NND2 NOR2 2/3 4/3 g u g avg p u p avg B 2/3 8/3 8/3 g u g avg p u p avg 2/3 4/3 B 4/3 g u g avg p u p avg Slide 6
7 PseudonMOS Gates q Design for unit current on output to compare with unit inverter. q pmos fights nmos inputs f Inverter NND2 NOR2 2/3 4/3 g u 4/3 4/9 g avg 8/9 p u p avg B 2/3 8/3 8/3 g u 8/3 8/9 g avg 6/9 p u p avg 2/3 4/3 B 4/3 g u 4/3 4/9 g avg 8/9 p u p avg Slide 7
8 PseudonMOS Gates q Design for unit current on output to compare with unit inverter. q pmos fights nmos inputs f Inverter NND2 NOR2 2/3 4/3 g u 4/3 4/9 g avg 8/9 p u 6/3 6/9 p avg 2/9 B 2/3 8/3 8/3 g u 8/3 8/9 g avg 6/9 p u 0/3 0/9 p avg 20/9 2/3 4/3 B 4/3 g u 4/3 4/9 g avg 8/9 p u 0/3 0/9 p avg 20/9 Slide 8
9 PseudonMOS Design q Ex: Design a kinput ND gate using pseudonmos. Estimate the delay driving a fanout of H q G q F q P q N In In k PseudonMOS H q D Slide 9
10 PseudonMOS Design q Ex: Design a kinput ND gate using pseudonmos. Estimate the delay driving a fanout of H q G * 8/9 8/9 q F GBH 8H/9 q P + (4+8k)/9 (8k+3)/9 q N 2 q D NF /N + P 4 2H 8k In In k PseudonMOS H Slide 0
11 PseudonMOS Power q PseudonMOS draws power whenever 0 Called static power P I V DD few m / gate * M gates would be a problem This is why nmos went extinct! q Use pseudonmos sparingly for wide NORs q Turn off pmos when not in use en B C Slide
12 Dynamic Logic q Dynamic gates uses a clocked pmos pullup q Two modes: precharge and evaluate 2 2/3 4/3 Static PseudonMOS Dynamic Precharge Evaluate Precharge Slide 2
13 The Foot q What if pulldown network is ON during precharge? q Use series evaluation transistor to prevent fight. precharge transistor inputs f inputs f foot footed unfooted Slide 3
14 Logical Effort Inverter NND2 NOR2 unfooted B 2 2 B footed 3 2 B 3 2 B Slide 4
15 Logical Effort Inverter NND2 NOR2 unfooted /3 2/3 B 2 2 2/3 3/3 B /3 3/3 footed 3 2 B 3 2 B 2 2/3 3/3 2 3/3 3 4/3 2 2/3 5/3 Slide 5
16 Monotonicity q Dynamic gates require monotonically rising inputs during evaluation 0 > 0 0 > > But not > 0 violates monotonicity during evaluation Precharge Evaluate Precharge Output should rise but does not Slide 6
17 Monotonicity Woes q But dynamic gates produce monotonically falling outputs during evaluation q Illegal for one dynamic gate to drive another! X Precharge Evaluate X Precharge Slide 7
18 Monotonicity Woes q But dynamic gates produce monotonically falling outputs during evaluation q Illegal for one dynamic gate to drive another! X Precharge Evaluate X Precharge X monotonically falls during evaluation should rise but cannot Slide 8
19 Domino Gates q Follow dynamic stage with inverting static gate Dynamic / static pair is called domino gate Produces monotonic outputs Precharge Evaluate Precharge domino ND W W X Z X B C Z dynamic NND static inverter B W H C X H X Z B C Z Slide 9
20 Domino Optimizations q Each domino gate triggers next one, like a string of dominos toppling over q Gates evaluate sequentially but precharge in parallel q Thus evaluation is more critical than precharge q HIskewed static stages can perform logic S0 S S2 S3 D0 D D2 D3 H S4 S5 S6 S7 D4 D5 D6 D7 Slide 20
21 DualRail Domino q Domino only performs noninverting functions: ND, OR but not NND, NOR, or XOR q Dualrail domino solves this problem Takes true and complementary inputs Produces true and complementary outputs sig_h sig_l Meaning 0 0 Precharged _l _h 0 0 inputs f f 0 invalid Slide 2
22 Example: ND/NND q Given _h, _l, B_h, B_l q Compute _h * B, _l ~( * B) Slide 22
23 Example: ND/NND q Given _h, _l, B_h, B_l q Compute _h * B, _l ~( * B) q Pulldown networks are conduction complements _l *B _h _h *B _l B_l B_h Slide 23
24 Example: XOR/XNOR q Sometimes possible to share transistors _l xnor B _h _l _l _h _h xor B B_l B_h Slide 24
25 Leakage q Dynamic node floats high during evaluation Transistors are leaky (I OFF 0) Dynamic value will leak away over time Formerly miliseconds, now nanoseconds! q Use keeper to hold dynamic node Must be weak enough not to fight evaluation weak keeper k 2 X H 2 Slide 25
26 Charge Sharing q Dynamic gates suffer from charge sharing B 0 x C x C x Slide 26
27 Charge Sharing q Dynamic gates suffer from charge sharing B 0 x C x C Charge sharing noise x V x V Slide 27
28 Charge Sharing q Dynamic gates suffer from charge sharing B 0 x C x C Charge sharing noise x C V V V x DD Cx + C Slide 28
29 Secondary Precharge q Solution: add secondary precharge transistors Typically need to precharge every other node q Big load capacitance C helps as well x secondary precharge transistor B Slide 29
30 Noise Sensitivity q Dynamic gates are very sensitive to noise Inputs: V IH V tn Outputs: floating output susceptible noise q Noise sources Capacitive crosstalk Charge sharing Power supply noise Feedthrough noise nd more! Slide 30
31 Domino Summary q Domino logic is attractive for highspeed circuits.5 2x faster than static CMOS But many challenges: Monotonicity Leakage Charge sharing Noise q Widely used in highperformance microprocessors Slide 3
32 Pass Transistor Circuits q Use pass transistors like switches to do logic q Inputs drive diffusion terminals as well as gates q CMOS + Transmission Gates: 2input multiplexer Gates should be restoring S S B S B S S S Slide 32
33 LEP q LEn integration with Pass transistors q Get rid of pmos transistors Use weak pmos feedback to pull fully high Ratio constraint S S L B Slide 33
34 CPL q Complementary Passtransistor Logic Dualrail form of pass transistor logic voids need for ratioed feedback Optional crosscoupling for railtorail swing S S L B S B S L Slide 34
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