CMOS Technology for Computer Architects


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1 CMOS Technology for Computer Architects Recap Technology Trends Lecture 2: Transistor Inverter Iakovos Mavroidis Giorgos Passas Manolis Katevenis FORTHICS (University of Crete) 1 2 Recap Threshold Voltage Concept Recap FinFET and Trigate V s V G V GS < V T V D V GS > V T V s V G V D Traditional Planar L G 3D Trigate third dimension! H fin L G W fin W G V B V B The value of V GS where strong inversion occurs is called the threshold voltage, V T 3 4 1
2 Lecture Contents Definitions (Voltages and Current) Transistor Operation Modes I D Inverter Static behavior V DS, GND V GS = V G  V S V DS = V D  V S V T I D 5 6 Channel Length and Width Channel Length and Width gate Top View gate Top View L Source W Drain Source W Drain H fin L eff L eff W fin L L L eff = L 2 * L eff = L 2 * L eff = L 2 * W eff = W fin + 2 * H fin 7 8 2
3 Channel Length and Width VoltageCurrent Relation: Cutoff gate Top View L Source W Drain H fin L eff W fin L L eff = L 2 * Source Cross section Drain L eff = L 2 * W eff = W fin + 2 * H fin C ox = ox /t ox V GS < V T 9 10 VoltageCurrent Relation: Cutoff VoltageCurrent Relation: Cutoff V T V T Subthreshold current Lower threshold voltage and lower supply voltage V GS < V T I D I 0 e [q (V GS V T )/nkt] V GS < V T I D I 0 e [q (V GS V T )/nkt]
4 Threshold Voltage Threshold Voltage small V DS small V DS large V DS S S V T,lin = Linear threshold voltage V T,lin = Linear threshold voltage V T,sat = Saturation Threshold Voltage V T,sat < V T,lin Trigate and Threshold Voltage Trigate and Corner Effect Simulated rolloff curve for a planar and TriGate transistor (WFin = 25 nm, HFin = 20 nm) T. Bauldauf et. al., Sem. Conf. Dresden Electron density in the channel Vd=1V, Vg=0.4 R = radii of curvature Lg=30nm B. Doyle et. al., VLSI Technology,
5 VoltageCurrent Relation: Linear Mode When V GS > V T and V DS (1κ) (V GS V T ) I D = k n W/L [(V GS V T )V DS V DS2 /2] where κ = 0 for long channel (L > 0.25 micron) and 0 < κ < 1 for short channel (SCE) k n = n C ox = n ox /t ox = is the process transconductance ( n is the carrier mobility) Voltage Current Relation : Saturation When a strong enough electric field is applied (i.e. V DS is high), the carrier velocity saturates V DS > (1κ) (V GS V T ) For small V DS, there is a linear dependence between V DS and I D ( k n W/L (V GS V T )V DS ), hence the name resistive or linear region The current remains constant (transistor saturates) Voltage Current Relation : Saturation Velocity Saturation Effects For long channel devices when V DS V GS V T 10 I DSAT = k n /2 W/L (V GS V T ) 2 I D For short channel devices when V DS (1  κ) (V GS V T ) I DSAT = κu SAT C ox W (V GS V T ) 0 V DS Velocity Saturation I DSAT has a linear dependence wrt V GS
6 Short Channel I D V D Characteristics (NMOS) Short Channel I D V GS Characteristics (1  κ) (V GS V T ) early saturation Linear V DS (V) Saturation (for 180nm TSMC process) current still increases X ,5 1 1,5 2 2,5 V GS (V) (for V DS = 2.5V, W/L = 1.5) V GS (V) (for 45nm technology, V DS = 250mV) Realov et.al. Symposium on VLSI Circuits, Velocitysaturation causes the shortchannel device to saturate at substantially smaller values of V DS Current Determinates CMOS Inverter: A First Look For a fixed V DS and V GS (> V T ), I DS is a function of the distance between the source and drain L the channel width W the threshold voltage V T the thickness of the SiO 2 t ox the dielectric of the gate insulator (e.g., SiO 2 ) ox the carrier mobility for nfets: n = 500 cm 2 /Vsec for pfets: p = 180 cm 2 /Vsec V S(PMOS) V D(PMOS) V D(NMOS) V S(NMOS) C L V S(PMOS) = V D(PMOS) = V D(NMOS) V S(NMOS) = 0 V GS(NMOS) = V DS(NMOS) = V GS(PMOS) =  V DS(NMOS) =
7 CMOS Inverter: Steady State Response The Ideal Inverter VDD Gain = 0 R p Gain =  = 1 = 0 R n Gain = 0 VDD/2 VDD = 0 = infinite gain in the transition region a gate threshold located in the middle of the logic swing high and low noise margins equal to half the swing input and output impedances of infinity and zero, resp = f( )? = f( )? V S(PMOS) V S(PMOS) = V D(PMOS) = V D(NMOS) V S(NMOS) = 0 V S(PMOS) I D(PMOS) V S(PMOS) = V D(PMOS) = V D(NMOS) V S(NMOS) = 0 V D(PMOS) V D(NMOS) C L V GS(NMOS) = V DS(NMOS) = V GS(PMOS) =  V DS(NMOS) =  V D(PMOS) V D(NMOS) I D(NMOS) C L V GS(NMOS) = V DS(NMOS) = V GS(PMOS) =  V DS(PMOS) =  V S(NMOS) V S(NMOS) At equilibrium point: I D(NMOS) =  I D(PMOS)
8 (V) Transforming PMOS IV Lines CMOS Inverter Load Lines I Dn V DSn V DS(NMOS) = = V DS(PMOS) + I Dp I Dp = 0 = 1.5 V DSp Move and mirror around xaxis V GSp = 1 V GSp = CMOS Inverter Load Lines CMOS Inverter VTC = Switching Threshold V M (V)
9 (V) CMOS Inverter VTC Simulated VTC NMOS off PMOS linear NMOS sat PMOS linear Saturation : V DS V GS V T NMOS sat PMOS sat NMOS linear PMOS sat NMOS linear PMOS off (V) 0.25um, W p /W n = Voltage Mapping Voltage Mapping g = 1 "1" undefined V IH g = 1 V IL "0" V IL V IH V IH and V IL that represent the points on the VTC curve where the gain =
10 V (volts) Noise Margins The Regenerative Property v 0 v 1 v 2 v 3 v 4 v 5 v 6 Noise Margin High Noise Margin Low Gnd Gate Output NM H =  V IH NM L = V IL  "1" V IH Undefined Region V IL "0" Gnd Gate Input For robust circuits, want the 0 and 1 intervals to be as large as possible v 0 v 1 v t (nsec) A gate with regenerative property ensure that a disturbed signal converges back to a nominal voltage level 39 Relative Transistor Sizing and V M Relative Transistor Sizing and V M V M is derived from the equation: I n ( =V M ) = I p ( = V M ) or k n /2 W n /L n (V M V T ) 2 = k p /2 W p /L p (V M V GS V T ) 2 Setting V M = / 2 and L n = L p we have: W p = (k n / k p ) W n 3 W n.1 ~3.4 (W/L) p /(W/L) n Note: xaxis is semilog V M is relatively insensitive to variations in device ratio: setting the ratio to 3, 2.5 and 2 gives V M s of 1.22V, 1.18V, and 1.13V Setting W n 2 W n is still ok and saves area
11 (V) (V) Impact of Sizing Impact of Process Variation on VTC Curve Wider PMOS Good PMOS Bad NMOS Wider NMOS Symmetrical Bad PMOS Good NMOS Nominal (V) Transistor sizing cause a shift in the switching threshold (V) Process variations cause a shift in the switching threshold Standard CMOS Properties Always a path to V dd or GND in steady state Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Full railtorail swing high noise margins Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steadystate input current No direct path steadystate between power and ground no static power dissipation Regenerative property Propagation delay function of load capacitance and resistance of transistors (next lecture) 44 11
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