ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN


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1 ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA Vishal Saxena
2 DESIGN PARAMETERS Analog circuit designers care about: Openloop Gain: g m r o Bandwidth (speed): C gs, C gd, f T, f max, etc. Power: V DD *I DD Voltage swing: V DS,sat Noise Linearity Mismatch (systematic and random) Layout Engineers care about: W/L sizing, layout matching, circuit isolation,.
3 SHORT CHANNEL CHARACTERISTICS Square law equations are no longer valid Intuition derived from classical analysis is still helpful i D = v sat WC ox (V GS V THN V DS,sat ) v sat =saturation velocity C ox =oxide capacitance per unit area Velocity saturation and overshoot effects Current analog technology is 14nm, typical designs in 65nm Requires NDA agreements CMOS Book uses 50nm process parameters V DD =1V, L min =50nm V THN =V THP =280mV
4 SHORT CHANNEL CHARACTERISTICS (2) Shortchannel devices appear to enter saturation as a lower voltage than predicted by the equation V DS,sat =V GS V THN V GS V THN V DS,sat V ov =V GS V THN The actual inversion layer charge distribution, Q I(y), is a function of V DS, in addition to V GS Q I(y) becomes zero at a lower V DS,sat
5 SHORT CHANNEL CHARACTERISTICS (3) Is a large range for the saturation region beneficial? We could really use the larger swing! Not really, need to look at the region where r o is large and that occurs when the device is deep into saturation :( V GS V THN
6 THRESHOLD VOLTAGE Strong function of L Use long channel for V TH matching Process variations Runtorun ~100mV Slow/nominal/fast Good design should be insensitive to the absolute value of V TH Should only depend upon the mismatch in V TH (~1mV) for good layout and large devices
7 SHORT CHANNEL CHARACTERISTICS For shortchannel design, the equation V DS,sat =V GS V THN is meaningless From now onwards, we'll talk in terms of the gate overdrive voltage V ov =V GS V THN > V DS,sat We can use V ov = 5% of V DD as a starting point for highspeed design (build your intuition) Vov = 70mV! VGS = 350mV A more robust method is to use constant g m /I D and current density (I D /W) across the design, instead of a constant V ov Refer to the slides Analog Design Using g m /I d and f t Metrics by Prof. Boser of UC Berkeley
8 TRANSCONDUCTANCE Triode Velocity saturation Weak Inversion Strong Inversion gm = (VGS VTHN) gmsub VT=ID/nVT
9 TRANSCONDUCTANCE Given V ov =2I D /g m, and a specified value of g m Pick I D and W based on Here, for a g m =150uA/V, we pick 10uA for sufficient current drive This leads to W=50 for NMOS and W=100 for PMOS VDS=100 mv g m =150uA/V V GS =350mV
10 OUTPUT RESISTANCE To determine V DS,sat, look at the point where the output resistance starts to increase (Here, V DS,sat = 50mV) We get considerably higher output resistances at a larger VDS(important!) Can t just model by a simple equation, r o = 1/I D,sat
11 OPENLOOP GAIN (g m r o ) g m r o is more useful than just r o Represents maximum attainable gain from a transistor Simulation Notes: Bias current idc sets V ov Use feedback to find the correct V GS while sweeping V DS Use relatively small erroramplifier gain (A=100) for fast DC convergence
12 OPENLOOP GAIN (g m r o ) The open loop gain is roughly g m r o = 150μAV 170k ~25 Considerably lower than the openloop gain in a longchannel process.
13 LONGCHANNEL CMOS, L MIN =1UM Figures from CMOS Circuit Design, Layout, and Simulation, Copyright WileyIEEE, CMOSedu.com Vishal Saxena
14 SHORTCHANNEL CMOS, L MIN =50NM Figures from CMOS Circuit Design, Layout, and Simulation, Copyright WileyIEEE, CMOSedu.com Vishal Saxena
15 BMR CIRCUIT IN 1UM CMOS Figures from CMOS Circuit Design, Layout, and Simulation, Copyright WileyIEEE, CMOSedu.com Vishal Saxena
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