# L ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling

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1 L ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling Scaling laws: Generalized scaling (GS) p. 610 Design steps p.613 Nanotransistor issues (page 626) Degradation mechanisms in NanoFETS (p ) Logic Gate Sizing NMOS CMOS Equivalent Circuits, Capacitance calculations 1

2 scaled-down potentials/voltages ϕ' = ϕ/k, here, k >1 scaled-down dimensions (x',y',z') = (x,y,z)/λ, here, λ >1 scaled-down concentrations (n',p',n' D,N' A ) = (n,p,n D,N A )/δ, δ = k/λ 2, Parameters LATV 1.3micron 0.25 micron QMDT* (IBM) 25nm SiGe (Home work) Scaling factor Comments Channel Length L( m) Gate Insulator Oxide t ox (nm) Junction Depth x j (nm) = (SiO 2 ) 0.5 (SiO 2 ) (e HfO2 /e SiO2 ) = 1.7nm Gives high Rs and Rd V TH (V) V TH =4x DV TH V TH =4x DV TH DV TH = V TH =4x DV TH DV TH =0.015 =4 DV TH =0.015V V DS = V DD (V) =4 V DD = 4 x V TH Band Bending (V) ? Doping N A (cm -3 ) 3x10 15 N A = N A = N A x 2 / =25 (Rs + Rd)ID IR Drop (mv) NA < 10mV < 1mV?? How to solve this RC Delay t (ps) Not appl. (NA) 100ps 2-5 ps???? How to solver this Generalized Scaling (Baccharini et al 1984) 2

3 Design steps using GS 1. Find dimensional scaling from existing channel dimensions and desired scaled- down 2. Using processing parameters, determine threshold variation DV TH Determine V TH (=~4 DV TH ) and V DD (V DD ~4*V TH ) 3. Find the scaling for voltages k 4. Compute the scaling factor d for doping. Verification of scaled-down design 1. Is the oxide thickness realistic in terms of gate leakage current? 2. Is supply voltage and threshold realistic in terms of source to drain tunneling? 3. Is the device to device fluctuation in a die and in dies in a wafer acceptable? 4. Is the drive current acceptable? Is the ID-VG and ID-VD characteristics ok in terms of fan-in and fan-out and logic noise margins? 3

4 DV TH V T = V FB - Q C SC o + 2 B = ms - Q C ox ox + 1 C o q N A 2e sre o 2 B q N A + 2 kt q ln N n i A q ms = q m - q Si - E 2 g - kt ln N n i A Dopant density variation (due to implant or in substrrate) Oxide or gate insulator thickness variation Oxide dielectric constant variation in thin films of 1-2nm Channel width and length variation, Oxide charge density variation 4

5 Nano-transistor scaling issues p. 626 FET operation as partially depleted or fully depleted Degradation Mechanisms: 1. Poly-Si gate depletion and increased gate capacitance 2. Source to drain tunneling, loss of gate control 3. Channel to gate tunneling for thin oxides: a. Fowler-Nordheim tunneling; b. Direct Tunneling 4. Gate induced drain leakage 5. Oxide breakdown Trapping of channel electron under gate ox Barrier Hopping Fowler-Nordheim Tunneling Direct Tunneling E f As FET dimensions are reduced, tunneling can occur 5

6 Degradation Mechanisms (627) 1.Poly-Si gate depletion and increased gate capacitance Poly silicon region: Poly-Si may be implanted during processing using ion implantation. However, with this method, some poly-si atoms will penetrate through the oxide, causing problems. This damage the gate insulator. The charge in poly-silicon gate depletion represents capacitance. 1 C =VDS 1 C ox 1 C Si C 1 PolySi Ec N + n P - Si n N + 2. Source to drain tunneling. N-Si Ef Ec' 30 A 6 Ev

7 Degradation Mechanisms 3. Channel to gate tunneling. 7

8 Degradation Mechanisms 4. GIDL. 8

9 Degradation Mechanisms (p.631) 5. Oxide Breakdown Oxide (dielectric) breakdown As we have seen, significant electron tunneling can occur when a large electric field is applied across an oxide layer. This tunneling can lead to a condition called dielectric breakdown, after which an oxide layer ceases to be a good electrical insulator. Dielectric breakdown can occur either softly (i.e. gradually) or abruptly. The physical mechanisms involved in, and leading to, dielectric breakdown involve: 1.impact ionization in the oxide layer 2.injection of holes 3.creation of electron-hole traps in the oxide 4.creation of sates at oxide-si interface 9

10 Degradation Mechanisms (631) 5. Oxide Breakdown Typical plot of charge to breakdown vs. oxide voltage for several oxide thickness values. (Ref: Taur & Ning) 10

11 Chapter 10 NMOS Inverter Fig. 1, p. 638 Id Vdd Vin Depletion mode (pull up) Vout Vin Enhancement mode (pull down) Vout Id Static or Ratioed Inverter t 11

12 NMOS Inverter (load and driver resistance ratios) p

13 NMOS Inverter Configurations 13

14 Device sizing in static (or ratioed) gates/networks V = V = V IN INV TEo V TE, dep W L W L Pd PU Eq. (8) p

15 V OUT V DD Inverter Gain V INV W pd increasing V INV VDD V IN Fig. 6. Output-Input voltage characteristics a a function of W pd The slope of the voltage transfer characteristics 15

16 Dynamic logic gates/networks p T 3 T 4 T 6 T 1 V out V IN T 2 C 2 T 5 C 1 C I Stage T 4 T 1 T 5 T 2 T 6 T 3 II Stage Fig. 7. A dynamic or two-phase ratio-less inverter 16

17 Fig. 13, p.649 Layout of NMOS Inverter (W/L) load = 1 10 m x 10 m (W/L) driver = 6 30 m x 5 m Fig. 10. (b) Schematic and (b) layout an NMOS inverter. 17

18 Sizing of FETs in a logic gate (p.647) 10/10 30/5 60/5 60/5 60/5 Fig. 11. NMOS gate with W/L ratios of various FETs. 18

19 B Circuit Model G C GSO C GDO C GBiF Fig. 14a. Capacitances Page 650 S C GS g m V GS C GD D g SD C BSj C BS g mb V BS C BD C BDj C SD B B Well C BODY-WELL (CMOS ONLY) Fig4 P.24 (Notes) Extrinsic Model G S C GSO g m gd V GS C GD I D C GDO D Fig. 14(b) Intrinsic model showing capacitances. C BSj g m V BS C BD C BDj 19

20 Capacitances are computed to find propagation delay(p ) 20

21 p.660 CMOS Inverter V DD I II V V DD V TPO = V DD V TPO V DD 2 III as V TPO 0 V 0 IV V TNO VDD 2 V TPO +V DD V DD p.661 Fig. 21 Voltage transfer characteristic V I 21

22 Fig. 33. Latch up in CMOS inverter (p672) Fig. 26. Sizing of CMOS transistors (p 668) 22

23 V DD A) B) V DD W L = 50 m 5 m PMOS m 5 m CMOS NOR gate W L V out = 10 m 5 m NMOS CMOS NAND gate 20 m 5 m 20 m 5 m V out Fig. 27 Sizing of 2-input NOR (p668) 2-input NAND CMOS inverter 23

24 FIN-FET Static RAM 24

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