ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120


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1 ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of 8, 20point problems of which you are to work only 6 for a total of 120 points. You must attempt problems 1 and 2. All other problems are optional. Please circle the number in the table above of the remaining three problems you wish graded. If you do not indicate the problems to be graded, then problems 1 through 6 will be graded regardless of whether they are worked or not. Be sure to turn in only the 6 problems you wish graded in proper numerical order. Please show your work leading to your answers so that maximum partial credit may be given where appropriate. Problem 1 (20 points This problem is required) If the foldedcascode op amp shown having a smallsignal voltage gain of 7464V/V is used as a comparator, find the dominant pole if C L = 5pF. If the input step is 10mV, determine whether the response is linear or slewing and find the propagation delay time. Assume the parameters of the NMOS transistors are K N =110V/µA 2, V TN = 0.7V, λ N =0.04V 1 and for the PMOS transistors are K P =50V/µA 2, V TP = 0.7V, λ P =0.05V 1. VBias M4 2.5V 80µm/1µm I 4 = 125µA 80µm/1µm I 5 = M5 125µA v in I 1 I 2 M6 M7 80µm/1µm 80µm/1µm M1 M2 I 6 I7 36µm 1.3V 1µm R 2 = I 9 2kΩ C L M8 M9 M3 I 3 = 36µm 36µm/1µm 100µA 1µm M10 M11 VBias 36µm/1µm 36µm/1µm 2.5V S02FEP1
2 ECE 6412, Spring 2002 Final Exam Page 2 Problem 2 (20 points This problem is required) A comparator consists of an amplifier cascaded with a latch as shown below. The amplifier has voltage gain of 10V/V and f 3dB = 100MHz and the latch has a time constant of 10ns. The maximum and minimum voltage swings of the amplifier and latch are V OH and V OL. When should the latch be enabled after the application of a step input to the amplifier of 0.05(V OH V OL ) to get minimum overall propagation time delay? What is the value of the minimum propagation time delay? It may useful to recall that the propagation time delay of the latch is given as t p = τ L ln V OH V OL 2v il where v il is the latch input ( V i of the text). v in = 0.05(V OH V OL ) t=0 v Amplifier oa A v (0)=10V/V f 3dB =100MHz v il Comparator Latch τ L =10ns Enable S02FEP2
3 ECE 6412, Spring 2002 Final Exam Page 3 Problem 3 (20 points This problem is optional) If R 1 = R 2 of the circuit shown, find an expression for the smallsignal output resistance R out ignoring R L. Repeat including the influence of R L on the output resistance. Let R 1 =R 2 and R L = 1kΩ, dc currents through M1 and M2 be 500µA, W 1 /L 1 = 100µm/1µm and W 2 /L 2 = 200µm/1µm. Find the value of R out. Assume the parameters of the NMOS transistors are K N =110V/µA 2, V TN = 0.7V, λ N =0.04V 1 and for the PMOS transistors are K P =50V/µA 2, V TP = 0.7V, λ P =0.05V 1. Assume that R 2 >>r ds1 or r ds2. V DD v IN M2 R 1 R 2 i OUT R out v OUT S02FEP3 C L M1 V SS R L
4 ECE 6412, Spring 2002 Final Exam Page 4 Problem 4 (20 points This problem is optional) A current mirror load, CMOS differential amplifier is shown. The current in M5 is 100µA. Assume the parameters of the NMOS transistors are K N =110V/µA 2, V TN = 0.7V, λ N =0.04V 1 and for the PMOS transistors are K P =50V/µA 2, V TP = 0.7V, λ P =0.05V 1. (a.) Find the smallsignal output resistance and voltage gain if the W/L ratio of M1 and M2 is 100µm/1µm. (b.) If the W/L ratio of M3 and M4 is 50µm/1µm and C ox = 24.7x10 4 F/m 2, and the effective output capacitance is 1pF, find all roots of this amplifier (ignore the influence of C gd4 ). Ony include the M1 M2 v in VBias V SS SO2FEP3 capacitors in this problem that you can calculate from the information given. (c.) What is the 3dB frequency in Hertz? M3 V DD M4 M5 1pf
5 ECE 6412, Spring 2002 Final Exam Page 5 Problem 5 (20 points This problem is optional) The simplified schematic of a feedback amplifier is shown. Use the method of feedback analysis to find v 2 /v 1, R in = v 1 /i 1, and R out = v 2 /i 2. Assume that all transistors are matched and that ß = 100, r π = 5kΩ and r o =. i 1 R 1 = 10kΩ R 3 = 10kΩ Q2 V CC Q1 R 4 = Q3 20kΩ i 2 v 1 R 1 = R 5 = R 6 = v2 1kΩ 10kΩ 1kΩ V EE S02FEP5
6 ECE 6412, Spring 2002 Final Exam Page 6 Problem 6 (20 points This problem is optional) A voltage follower feedback circuit is shown. For the MOS transistor, I D = 0.5mA, K = 180µA/V 2, r ds =, and W/L = 100. Although, the bulk effect should be considered, g mbs, for simplicity ignore the bulk effects in this problem. For the op amp, assume that R i = 1MΩ, R o = 10kΩ, and a v = Calculate the input resistance and output resistance using Blackman s formula given below. R out = R out (Controlled source =0) 1 RR(output port shorted) 1 RR(output port open) v in R in V DD I D R out S02FEP6 V SS
7 ECE 6412, Spring 2002 Final Exam Page 7 Problem 7 (20 points This problem is optional) A CMOS op amp capable of operating from 1.5V power supply is shown. All device lengths are 1µm and are to operate in the saturation region. Design all of the W values of every transistor of this op amp to meet the following specifications. I M9 Slew rate = ±10V/µs V out (max) = 1.25V V out (min) = 0.75V V ic (min) = 1V V ic (max) = 2V GB = 10MHz Phase margin = 60 when the output pole = 2GB and the RHP zero = 10GB. Keep the mirror pole 10GB (C ox = 0.5fF/µm 2 ). M10 M11 1.5I 1.5V M12 1.5I I M1 M2 I I M5 I M8 M3 M4 C c M7 M6 10I 10pF S02FEP7 Your design should meet or exceed these specifications. Ignore bulk effects in this problem and summarize your W values to the nearest micron, the value of C c (pf), and I(µA) in the following table. Use the following model parameters: K N =24µA/V 2, K P = 8µA/V 2, V TN = V TP = 0.75V, λ N = 0.01V 1 and λ P = 0.02V 1. C c I W1=W2 W3 = W4 W5 = W8 W6 W7 W9 = W10 W11 = W12 P diss
8 ECE 6412, Spring 2002 Final Exam Page 8 Problem 8 (20 points This problem is optional) A differential CMOS amplifier using depletion mode input devices is shown. Assume that the normal MOSFETs parameters are K N =110V/µA 2, V TN = 0.7V, λ N =0.04V 1 and for the PMOS transistors are K P =50V/µA 2, V TP = 0.7V, λ P =0.05V 1. For the depletion mode NMOS transistors, the parameters are the same as the normal NMOS except that V TN = 0.5V. (a.) What is the maximum input commonmode voltage, V icm (max)? (b.) What is the minimum input commonmode voltage, V icm (min)? (c.) What value of V DD gives an ICMR = 0.5V DD? V BiasP V DD M3 M4 10µm/1µm v M1 M2 1 v 2 100µm/1µm V BiasN M5 100µA 100µm/1µm S02FEP8
9 ECE 6412, Spring 2002 Final Exam Page 9 Extra Page
ECE 6412, Spring Final Exam Page 1
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