# EECS 105: FALL 06 FINAL

Size: px
Start display at page:

Transcription

1 University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 2-3:30 Wednesday December 13, 12:30-3:30pm EECS 105: FALL 06 FINAL NAME Last First SID Problem 1 (9): Problem 2 (13): Problem 3 (9): Problem 4 (12): Problem 5 (12): Total (55) Important Notice: To get credit for a problem or sub-problem, it is essential for you to show the steps you took to get to the answer. No credit will be given if you just show the answer without any further explanation. EECS 105: FALL 06 MIDTERM 2 1

2 PROBLEM 1: Bipolar Transistor (9 pts) An NPN transistor is biased in the forward-active region. Identify how the following parameters (forward current gain β F, collector current I C, and input resistance r π ) change as a result of an the increase of the model parameters or the bias point, as indicated in the table below. Fill in the blanks in the table with either + (increase), - (decrease), 0 (no change). I B V C Solution: Model Parameters/Bias Point Forward Gain β F Collector Current I C I B (Base Current) V C (Collector Voltage) W E (Emitter Width) W B (Base Width) N de (Emitter Donor Concentration) N ab (Base Acceptor Concentration) Input Resistance r π T (Temperature) Use the following relationship. β F = (Dnb Nde We/ Dpe Nab Wb) Ic = Is x exp [Vbe / (kt/q) ] (1+ Vc/VA) =β F x IB r π = β F /gm =β F /(Ic/VT)= β F x (kt/q) / Ic EECS 105: FALL 06 MIDTERM 2 2

3 PROBLEM 2: Frequency Domain Response (13 pts) Given amplifier shown on the right. You may assume that the MOSFET is operating in the constant current region. Assume the following values: R S = 20 kω; I SUP = - I BIAS = 0.2 ma; k n = 100 μ A /V 2, V tn = 1.0V, λ n = 0.05 V -1 C L = 10 ff; C gs = 20 ff; C gd = 10 ff; You may assume that the current sources I SUP and I BIAS are ideal. i SUP V DD i OUT C L i s R S I BIAS V SS (a) Draw the two port model of this current amplifier, and determine the value of the relevant parameters (do not include capacitors at this point). (3 points) i in i s R S R in -i in R OUT g m =(2W/Lμ n C ox I D ) 1/2 =0.2mS r o =1/(λ n I D )=100kΩ R in =1/g m =5kΩ R out =r o (1+g m R S )=500kΩ A i =-1 (b) Using the result from (a), draw the small signal model of the complete circuit, now including all relevant capacitances. (1 points) i out i in i s R S R in C gs -i in R OUT C gd C L EECS 105: FALL 06 MIDTERM 2 3

4 (c) Derive the expression for the transfer function I out /I s. Do not fill in any values yet. (3 points) Phasor analysis on the input side: Current divider, I in = I S (R S C gs )/( R in +(R S C gs )) = I S /((1+R in /R S )(1+jωC gs (R in R S ))) Phasor analysis on the output side: Current divider, I out = (- I in )(R out C gd )/( C L +(R out C gd )) = jωr out C L /(1+jωR out (C L +C gd ))(-I in ) Therefore, I out /I s = -(R S /( R S + R in ))( jωc L R out )/((1+jωC gs (R in R S ))(1+jω(C L +C gd )R out )) DC zero: 1/(C L R out ) = 2.0*10 8 rad/sec 1 st pole: 1/((C L +C gd )R out ) = 1.0*10 8 rad/sec 2 nd pole: 1/(C gs (R in R S )) = 1.25*10 10 rad/sec (d) Draw the Amplitude and Phase Bode plots corresponding to the transfer function derived above. Annotate all relevant values (pole and zero frequencies, amplitude and phase values) (4 points) log A db logω 20db/dec -20db/dec EECS 105: FALL 06 MIDTERM 2 4

5 ϕ logω (e) Lazy designer Tom figures out he does not want to do all this work, and decides to use the open-circuit timing constant approach instead to derive the ω 3db frequency. Determine the frequency obtained this way. (2 points) R Tgs = R in R S = 4kΩ R TL = R Tgd = R out = 500kΩ ω 3db = 1/(C gs (R in R S ) + (C L + C gd )R out ) = 0.992*10 8 rad/sec ω 3db = 0.992*10 8 rad/sec EECS 105: FALL 06 MIDTERM 2 5

6 PROBLEM 3: Multi-Stage BJT Amplifier (9 pts) For the bipolar transistors in the amplifier below, assume: β=100 and V A (early voltage) = 25V. (a) Determine the dc collector currents in Q1 and Q2. You may neglect the early effect for this part (V A = - V). (2 points) Solution: Q1 and Q2 share the same Vbe, so Ic1=Ic2=Iss/2. If you take β into account, the currents are actually α*iss/2. Credit was given for both. The current through roc = (VB-Vbe)/roc is negligible. IC1 = 1mA (or 0.99mA) IC2 = 1mA (or 0.99mA) (b) Choose the value of R L such that the dc value of V OUT equals 2.5V. (1 point) Solution: Ic2 = 1mA, so R L = 2.5V/1mA = 2.5 kohms. R L = 2.5 kohms EECS 105: FALL 06 MIDTERM 2 6

7 (c) Draw the small signal model for this amplifier. (3 points) Solution: r o2 (d) Derive an expression and calculate a numerical value for the voltage gain A v = v out /v in (3 points) Solution: View the amplifier as a cascade of a common collector stage into a common base stage. Av1 1, Rout1 1/gm1 Rin1 1/gm2 = 1/gm1 Therefore, Vs = Vin/2 Vout/Vs = +gm2*rl = 2*Vout/Vin (assuming RL << Rout2, which it is) Therefore Vout/Vin = Av = +1/2*gm*RL = 0.5*38.5e-3*2.5K = +48 Note that the sign of the gain is positive; this amp is non-inverting. A V = ½*gm*RL = +48 EECS 105: FALL 06 MIDTERM 2 7

8 PROBLEM 4: Miscellaneous (12 pts) (a) Determine an expression for the maximum voltage gain that can be obtained by this amplifier, the frequency at which it occurs, and its 3db bandwidth (4 points). VDD C R L At the resonant frequency, inductor and capacitor tune out and only the resistance is left at any other frequency, the impedance is lower. Hence the max gain equals g m R, with g m the transconductance of M (assuming that r o of M is much larger than R. It occurs at the resonant frequency ω vi 0 = sqr_root(1/lc). The 3db frequency is determined by the Q of the resonator. ω 3db = Δω/2 = R/2L. M vo Amax = ω max = ω 3db = (b) Find an expression for the trans-resistance of this famous bipolar circuit (3 points). V DD Each stage provides a current gain of (β F +1) (ass can be easily seen from the schematic). Hence the trans-resistance of the complete amplifier equals: v o /i in = (β F +1) 2 R L. i in Q1 Q2 v o EECS 105: FALL 06 MIDTERM 2 8

9 R m = (c) For the amplifier shown here, fill in how the signals v o1, v o2, v o1 -v o2, v x change (,, or -) as a function of the changes in v i1, v i2, V cc, and T (temperature). Changes in v i1 and v i2 (when happening simultaneously) are by equal amounts. (5 points) v o1 V cc V cc v o2 v i1 v x v i2 v i1 v i2 V cc T v o1 v o2 v o1 -v o2 v x or - (small increase) EECS 105: FALL 06 MIDTERM 2 9

10 PROBLEM 5: Biasing (12 points) VDD = 2.5V Iref = 100uA Vbias DC AC Rs M2 M1 M8 iout Iref1 RL M3 M5 Iref2 M4 M6 M7 VSS = -2.5V Consider the MOS amplifier given above, and assuming the following parameters: R L = 75K For NMOS transistors: μ ncox = 50 μ A /V 2, Vtn = 1.0V, λ n = 0.05 V -1 For PMOS transistors μ pcox = 25 μ A /V 2, Vtp = -1.0V, λ p = 0.05 V -1 Transistor sizes: M1: (W/L) 1 = 50/1 ( μ m / μm) M5: (W/L) 1 = 25/1 ( μ m / μm) M2: (W/L) 1 = 50/1 ( μ m / μm) M6: (W/L) 1 = 25/1 ( μ m / μm) M3: (W/L) 1 = 25/1 ( μ m / μm) M7: (W/L) 1 = 50/1 ( μ m / μm) M4: (W/L) 1 = 25/1 ( μ m / μm) M8: (W/L) 1 =? / 1 ( μ m / μm) a. Find the numerical value of the DC currents Iref1 and Iref2. (2 points) Iref1 = 100uA Iref2 = 200uA EECS 105: FALL 06 MIDTERM 2 10

11 b. Determine the DC bias voltage at the gate of M2 that maximizes the output (voltage) swing. (hint: the selected voltage should be such that the maximum output occurs when M1 and M2 are at the edge of saturation). (3 points) -Vg2 Vsg2 Vdsat1 + Vdd = 0 Vg2 = Vdd Vsg2 Vdsat1 Vg2 = Vdd Vdsat2 Vdsat1 - Vtp But, Vdsat1 = Vdsat2 = So Vdsat =.4V 2 * Iref 1 W Cox( ) L μp Vg2 = 2.5V -2*(.4)V 1.0V =.7V V G2 =.7V c. Size transistor M8 to accomplish the DC bias determined in b. (2 points) If you could not find the answer to b., you may assume that V G2 = 0.5V. We know that Vg2 = Vdd 2 Vdsat - Vtp Also, Iref2 = 1 W μ pcox( ) 8( Vsg Vtp )^2 2 L W 2* Iref 2 ( ) 8 = L μp Cox( Vsg Vtp )^2 W 2* Iref 2 ( ) 8 = L μpcox(2vdsatp)^2 Thus (W/L) 8 = (25/1) (W/L) 8 = (25/1) EECS 105: FALL 06 MIDTERM 2 11

12 d. Calculate the value of V BIAS so that I OUT (that is, the DC component of the output current) = 0. (you may ignore channel length modulation for this question). (2 points) Since Iout = 0A, all of Iref1 is flowing through the drain of M1. Thus, 1 W Also, Iref2 = μ pcox( ) 1( Vsg1 Vtp )^2 2 L Vsg1 = Vdsat1 + Vtp, Vg1 = Vbias = Vdd Vdsat1 - Vtp Vg1 = 1.1V V BIAS = 1.1V e. Find the maximum amplitude of the sinusoidal input small-signal voltage such that the output current is not clipped (again ignore channel length modulation). (3 points) We know that Vout min = Vss + Vtn + 2Vdsat = -.7V Vout max = Vg2 + Vtp =.7V + 1V = 1.7V Thus, if we bias the DC output to be at 0V, the maximum amplitude of.7v can be attained, which is limited by Vout min. v max =.7V EECS 105: FALL 06 MIDTERM 2 12

13 EECS 105: FALL 06 MIDTERM 2 13

### 6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

### Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal

### Biasing the CE Amplifier

Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th

### Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

### Lecture 37: Frequency response. Context

EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in

### 1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp)

HW 3 1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp) a) Obtain in Spice the transistor curves given on the course web page except do in separate plots, one for the npn

### ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may

### University of Toronto. Final Exam

University of Toronto Final Exam Date - Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last

### Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.

Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT-3 Department of Electrical and Computer Engineering Winter 2012 1. A common-emitter amplifier that can be represented by the following equivalent circuit,

### ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution

ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown

### EECS 141: FALL 05 MIDTERM 1

University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION

### ECE 546 Lecture 11 MOS Amplifiers

ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase

### Homework Assignment 08

Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance

### I. Frequency Response of Voltage Amplifiers

I. Frequency Response of Voltage Amplifiers A. Common-Emitter Amplifier: V i SUP i OUT R S V BIAS R L v OUT V Operating Point analysis: 0, R s 0, r o --->, r oc --->, R L ---> Find V BIAS such that I C

### Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER

Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER Outline. Introduction 2. CMOS multi-stage voltage amplifier 3. BiCMOS multistage voltage amplifier 4. BiCMOS current buffer 5. Coupling amplifier

### ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z

### Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)

### Amplifiers, Source followers & Cascodes

Amplifiers, Source followers & Cascodes Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 0-05 02 Operational amplifier Differential pair v- : B v + Current mirror

### 1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012

/3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F

### Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs

EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,

### Frequency Response Prof. Ali M. Niknejad Prof. Rikky Muller

EECS 105 Spring 2017, Module 4 Frequency Response Prof. Ali M. Niknejad Department of EECS Announcements l HW9 due on Friday 2 Review: CD with Current Mirror 3 Review: CD with Current Mirror 4 Review:

### EE 330. Lecture 35. Parasitic Capacitances in MOS Devices

EE 330 Lecture 35 Parasitic Capacitances in MOS Devices Exam 2 Wed Oct 24 Exam 3 Friday Nov 16 Review from Last Lecture Cascode Configuration Discuss V CC gm1 gm1 I B VCC V OUT g02 g01 A - β β VXX Q 2

### ECE 342 Solid State Devices & Circuits 4. CMOS

ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

### Circle the one best answer for each question. Five points per question.

ID # NAME EE-255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions

### ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120

ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of

Design of Analog Integrated Circuits Chapter 11: Introduction to Switched- Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4

### Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and cross-sectional area 100µm 2

### Electronics II. Midterm II

The University of Toledo f4ms_elct7.fm - Section Electronics II Midterm II Problems Points. 7. 7 3. 6 Total 0 Was the exam fair? yes no The University of Toledo f4ms_elct7.fm - Problem 7 points Given in

### EE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits

EE 330 Lecture 22 Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits Exam 2 Friday March 9 Exam 3 Friday April 13 Review Session for Exam 2: 6:00

### Practice 3: Semiconductors

Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given

### 55:041 Electronic Circuits The University of Iowa Fall Exam 2

Exam 2 Name: Score /60 Question 1 One point unless indicated otherwise. 1. An engineer measures the (step response) rise time of an amplifier as t r = 0.35 μs. Estimate the 3 db bandwidth of the amplifier.

### Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits

### Electronics II. Midterm #2

The University of Toledo EECS:3400 Electronics I Section sums_elct7.fm - StudentName Electronics II Midterm # Problems Points. 8. 3. 7 Total 0 Was the exam fair? yes no The University of Toledo sums_elct7.fm

### Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage v gs v i - v o V DD v bs - v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs - C

### ECE137B Final Exam. There are 5 problems on this exam and you have 3 hours There are pages 1-19 in the exam: please make sure all are there.

ECE37B Final Exam There are 5 problems on this exam and you have 3 hours There are pages -9 in the exam: please make sure all are there. Do not open this exam until told to do so Show all work: Credit

### EE105 - Fall 2006 Microelectronic Devices and Circuits. Some Administrative Issues

EE105 - Fall 006 Microelectronic evices and Circuits Prof. Jan M. Rabaey (jan@eecs Lecture 8: MOS Small Signal Model Some Administrative Issues REIEW Session Next Week Tu Sept 6 6:00-7:30pm; 060 alley

### Electronics II. Final Examination

The University of Toledo f6fs_elct7.fm - Electronics II Final Examination Problems Points. 5. 0 3. 5 Total 40 Was the exam fair? yes no The University of Toledo f6fs_elct7.fm - Problem 5 points Given is

### Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 LECTURE 310 OPEN-LOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop

### Electronics II. Final Examination

f3fs_elct7.fm - The University of Toledo EECS:3400 Electronics I Section Student Name Electronics II Final Examination Problems Points.. 3 3. 5 Total 40 Was the exam fair? yes no Analog Electronics f3fs_elct7.fm

### UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE 105: Microelectronic Devices and Circuits Spring 2008 MIDTERM EXAMINATION #1 Time

### Electronics II. Midterm #1

The University of Toledo EECS:3400 Electronics I su3ms_elct7.fm Section Electronics II Midterm # Problems Points. 5. 6 3. 9 Total 0 Was the exam fair? yes no The University of Toledo su3ms_elct7.fm Problem

### Homework Assignment 09

Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3-dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =

### Bipolar Junction Transistor (BJT) - Introduction

Bipolar Junction Transistor (BJT) - Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification

### ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

### Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier. December 1, 2005

6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 23 Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier December, 2005 Contents:. Introduction 2. Intrinsic frequency response

### Electronic Circuits Summary

Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent

### GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering

NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 First Exam Closed Book and Notes Fall 2002 September 27, 2002 General Instructions: 1. Write on one side of

### 6.012 Electronic Devices and Circuits

Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to

### ECE315 / ECE515 Lecture 11 Date:

ecture 11 Date: 15.09.016 MOS Differential Pair Quantitative Analysis differential input Small Signal Analysis MOS Differential Pair ECE315 / ECE515 M 1 and M are perfectly matched (at least in theory!)

### 6.012 Electronic Devices and Circuits

Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless

### UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences E. Alon Final EECS 240 Monday, May 19, 2008 SPRING 2008 You should write your results on the exam

### ECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3

ECE 523/42 - Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o

### Digital Integrated Circuits

Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Short-circuit current The CMOS inverter :

### 55:041 Electronic Circuits The University of Iowa Fall Final Exam

Final Exam Name: Score Max: 135 Question 1 (1 point unless otherwise noted) a. What is the maximum theoretical efficiency for a class-b amplifier? Answer: 78% b. The abbreviation/term ESR is often encountered

### Lecture 23 - Frequency Resp onse of Amplifiers (I) Common-Source Amplifier. May 6, 2003

6.0 Microelectronic Devices and Circuits Spring 003 Lecture 3 Lecture 3 Frequency Resp onse of Amplifiers (I) CommonSource Amplifier May 6, 003 Contents:. Intro duction. Intrinsic frequency resp onse of

### ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

### EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring

### The Physical Structure (NMOS)

The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two

### Charge-Storage Elements: Base-Charging Capacitance C b

Charge-Storage Elements: Base-Charging Capacitance C b * Minority electrons are stored in the base -- this charge q NB is a function of the base-emitter voltage * base is still neutral... majority carriers

### CMOS Analog Circuits

CMOS Analog Circuits L6: Common Source Amplifier-1 (.8.13) B. Mazhari Dept. of EE, IIT Kanpur 19 Problem statement : Design an amplifier which has the following characteristics: + CC O in R L - CC A 100

### EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University

EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar

### LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH ) Trip Point of an Inverter

Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page 380-1 LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH 445-461) Trip Point of an Inverter V DD In order to determine the propagation

### Section 1: Common Emitter CE Amplifier Design

ECE 3274 BJT amplifier design CE, CE with Ref, and CC. Richard Cooper Section 1: CE amp Re completely bypassed (open Loop) Section 2: CE amp Re partially bypassed (gain controlled). Section 3: CC amp (open

### MOS Transistor Theory

MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

### EE105 Fall 2015 Microelectronic Devices and Circuits Frequency Response. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)

EE05 Fall 205 Microelectronic Devices and Circuits Frequency Response Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Amplifier Frequency Response: Lower and Upper Cutoff Frequency Midband

### CMOS Inverter (static view)

Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:

### ECE137B Final Exam. Wednesday 6/8/2016, 7:30-10:30PM.

ECE137B Final Exam Wednesday 6/8/2016, 7:30-10:30PM. There are7 problems on this exam and you have 3 hours There are pages 1-32 in the exam: please make sure all are there. Do not open this exam until

### Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model

Content- MOS Devices and Switching Circuits Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model A Cantoni 2009-2013 Digital Switching 1 Content- MOS

### Lecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen

Lecture 5 Followers (1/11/4) Page 51 LECTURE 5 FOLLOWERS (READING: GHLM 344362, AH 221226) Objective The objective of this presentation is: Show how to design stages that 1.) Provide sufficient output

### 3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti

Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +

### Electronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline Announcements. Notes on Single Transistor Amplifiers

6.012 Electronic Devices and Circuits Lecture 18 Single Transistor Amplifier Stages Outline Announcements Handouts Lecture Outline and Summary Notes on Single Transistor Amplifiers Exam 2 Wednesday night,

### Lecture 18. Common Source Stage

ecture 8 OUTINE Basic MOSFET amplifier MOSFET biasing MOSFET current sources Common source amplifier eading: Chap. 7. 7.7. EE05 Spring 008 ecture 8, Slide Prof. Wu, UC Berkeley Common Source Stage λ =

### Refinements to Incremental Transistor Model

Refinements to Incremental Transistor Model This section presents modifications to the incremental models that account for non-ideal transistor behavior Incremental output port resistance Incremental changes

### EE105 Fall 2014 Microelectronic Devices and Circuits

EE05 Fall 204 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of BJT Amplifiers Emitter (CE) Collector (CC) Base (CB)

### ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

### and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

### EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

### BJT Biasing Cont. & Small Signal Model

BJT Biasing Cont. & Small Signal Model Conservative Bias Design (1/3, 1/3, 1/3 Rule) Bias Design Example Small-Signal BJT Models Small-Signal Analysis 1 Emitter Feedback Bias Design R B R C V CC R 1 R

### EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM

### ID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom

ID # NAME EE-255 EXAM 3 April 7, 1998 Instructor (circle one) Ogborn Lundstrom This exam consists of 20 multiple choice questions. Record all answers on this page, but you must turn in the entire exam.

### Chapter 10 Feedback. PART C: Stability and Compensation

1 Chapter 10 Feedback PART C: Stability and Compensation Example: Non-inverting Amplifier We are analyzing the two circuits (nmos diff pair or pmos diff pair) to realize this symbol: either of the circuits

### Microelectronics Main CMOS design rules & basic circuits

GBM8320 Dispositifs médicaux intelligents Microelectronics Main CMOS design rules & basic circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim mohamad.sawan@polymtl.ca M5418 6 & 7 September

### UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #2 EECS141 Due Thursday, September 9, 5pm, box in 240 Cory PROBLEM

### The Devices. Jan M. Rabaey

The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

### EE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow

EE 330 Lecture 16 MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow Review from Last Time Operation Regions by Applications Id I D 300 250 200 150

### Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,

### ECE 255, Frequency Response

ECE 255, Frequency Response 19 April 2018 1 Introduction In this lecture, we address the frequency response of amplifiers. This was touched upon briefly in our previous lecture in Section 7.5 of the textbook.

### P-MOS Device and CMOS Inverters

Lecture 23 P-MOS Device and CMOS Inverters A) P-MOS Device Structure and Oeration B) Relation of Current to t OX, µ V LIMIT C) CMOS Device Equations and Use D) CMOS Inverter V OUT vs. V IN E) CMOS Short

### Two-Port Noise Analysis

Berkeley Two-Port Noise Analysis Prof. Ali M. Niknejad U.C. Berkeley Copyright c 2015 by Ali M. Niknejad 1/26 Equivalent Noise Generators v 2 n Noisy Two-Port i 2 n Noiseless Two-Port Any noisy two port

### Electronics II. Midterm #2

The University of Toledo EECS:3400 Electronics I su4ms_elct7.fm Section Electronics II Midterm # Problems Points. 8. 7 3. 5 Total 0 Was the exam fair? yes no The University of Toledo su4ms_elct7.fm Problem

### Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

EE610: CMOS Analog Circuits L: MOS Models- (1 st Aug. 013) B. Mazhari Dept. of EE, IIT Kanpur 3 NMOS Models MOS MODEL Above Threshold Subthreshold ( GS > TN ) ( GS < TN ) Saturation ti Ti Triode ( DS >

### Semiconductor Physics fall 2012 problems

Semiconductor Physics fall 2012 problems 1. An n-type sample of silicon has a uniform density N D = 10 16 atoms cm -3 of arsenic, and a p-type silicon sample has N A = 10 15 atoms cm -3 of boron. For each

### EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors

EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )

### EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR

EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX = - 4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3

### EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET

EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: n-channel MOSFET Source Gate L Drain W L EFF Poly Gate oxide n-active p-sub depletion region (electrically

### MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

### Chapter 9 Frequency Response. PART C: High Frequency Response

Chapter 9 Frequency Response PART C: High Frequency Response Discrete Common Source (CS) Amplifier Goal: find high cut-off frequency, f H 2 f H is dependent on internal capacitances V o Load Resistance