EECS 105: FALL 06 FINAL


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1 University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 23:30 Wednesday December 13, 12:303:30pm EECS 105: FALL 06 FINAL NAME Last First SID Problem 1 (9): Problem 2 (13): Problem 3 (9): Problem 4 (12): Problem 5 (12): Total (55) Important Notice: To get credit for a problem or subproblem, it is essential for you to show the steps you took to get to the answer. No credit will be given if you just show the answer without any further explanation. EECS 105: FALL 06 MIDTERM 2 1
2 PROBLEM 1: Bipolar Transistor (9 pts) An NPN transistor is biased in the forwardactive region. Identify how the following parameters (forward current gain β F, collector current I C, and input resistance r π ) change as a result of an the increase of the model parameters or the bias point, as indicated in the table below. Fill in the blanks in the table with either + (increase),  (decrease), 0 (no change). I B V C Solution: Model Parameters/Bias Point Forward Gain β F Collector Current I C I B (Base Current) V C (Collector Voltage) W E (Emitter Width) W B (Base Width) N de (Emitter Donor Concentration) N ab (Base Acceptor Concentration) Input Resistance r π T (Temperature) Use the following relationship. β F = (Dnb Nde We/ Dpe Nab Wb) Ic = Is x exp [Vbe / (kt/q) ] (1+ Vc/VA) =β F x IB r π = β F /gm =β F /(Ic/VT)= β F x (kt/q) / Ic EECS 105: FALL 06 MIDTERM 2 2
3 PROBLEM 2: Frequency Domain Response (13 pts) Given amplifier shown on the right. You may assume that the MOSFET is operating in the constant current region. Assume the following values: R S = 20 kω; I SUP =  I BIAS = 0.2 ma; k n = 100 μ A /V 2, V tn = 1.0V, λ n = 0.05 V 1 C L = 10 ff; C gs = 20 ff; C gd = 10 ff; You may assume that the current sources I SUP and I BIAS are ideal. i SUP V DD i OUT C L i s R S I BIAS V SS (a) Draw the two port model of this current amplifier, and determine the value of the relevant parameters (do not include capacitors at this point). (3 points) i in i s R S R in i in R OUT g m =(2W/Lμ n C ox I D ) 1/2 =0.2mS r o =1/(λ n I D )=100kΩ R in =1/g m =5kΩ R out =r o (1+g m R S )=500kΩ A i =1 (b) Using the result from (a), draw the small signal model of the complete circuit, now including all relevant capacitances. (1 points) i out i in i s R S R in C gs i in R OUT C gd C L EECS 105: FALL 06 MIDTERM 2 3
4 (c) Derive the expression for the transfer function I out /I s. Do not fill in any values yet. (3 points) Phasor analysis on the input side: Current divider, I in = I S (R S C gs )/( R in +(R S C gs )) = I S /((1+R in /R S )(1+jωC gs (R in R S ))) Phasor analysis on the output side: Current divider, I out = ( I in )(R out C gd )/( C L +(R out C gd )) = jωr out C L /(1+jωR out (C L +C gd ))(I in ) Therefore, I out /I s = (R S /( R S + R in ))( jωc L R out )/((1+jωC gs (R in R S ))(1+jω(C L +C gd )R out )) DC zero: 1/(C L R out ) = 2.0*10 8 rad/sec 1 st pole: 1/((C L +C gd )R out ) = 1.0*10 8 rad/sec 2 nd pole: 1/(C gs (R in R S )) = 1.25*10 10 rad/sec (d) Draw the Amplitude and Phase Bode plots corresponding to the transfer function derived above. Annotate all relevant values (pole and zero frequencies, amplitude and phase values) (4 points) log A db logω 20db/dec 20db/dec EECS 105: FALL 06 MIDTERM 2 4
5 ϕ logω (e) Lazy designer Tom figures out he does not want to do all this work, and decides to use the opencircuit timing constant approach instead to derive the ω 3db frequency. Determine the frequency obtained this way. (2 points) R Tgs = R in R S = 4kΩ R TL = R Tgd = R out = 500kΩ ω 3db = 1/(C gs (R in R S ) + (C L + C gd )R out ) = 0.992*10 8 rad/sec ω 3db = 0.992*10 8 rad/sec EECS 105: FALL 06 MIDTERM 2 5
6 PROBLEM 3: MultiStage BJT Amplifier (9 pts) For the bipolar transistors in the amplifier below, assume: β=100 and V A (early voltage) = 25V. (a) Determine the dc collector currents in Q1 and Q2. You may neglect the early effect for this part (V A =  V). (2 points) Solution: Q1 and Q2 share the same Vbe, so Ic1=Ic2=Iss/2. If you take β into account, the currents are actually α*iss/2. Credit was given for both. The current through roc = (VBVbe)/roc is negligible. IC1 = 1mA (or 0.99mA) IC2 = 1mA (or 0.99mA) (b) Choose the value of R L such that the dc value of V OUT equals 2.5V. (1 point) Solution: Ic2 = 1mA, so R L = 2.5V/1mA = 2.5 kohms. R L = 2.5 kohms EECS 105: FALL 06 MIDTERM 2 6
7 (c) Draw the small signal model for this amplifier. (3 points) Solution: r o2 (d) Derive an expression and calculate a numerical value for the voltage gain A v = v out /v in (3 points) Solution: View the amplifier as a cascade of a common collector stage into a common base stage. Av1 1, Rout1 1/gm1 Rin1 1/gm2 = 1/gm1 Therefore, Vs = Vin/2 Vout/Vs = +gm2*rl = 2*Vout/Vin (assuming RL << Rout2, which it is) Therefore Vout/Vin = Av = +1/2*gm*RL = 0.5*38.5e3*2.5K = +48 Note that the sign of the gain is positive; this amp is noninverting. A V = ½*gm*RL = +48 EECS 105: FALL 06 MIDTERM 2 7
8 PROBLEM 4: Miscellaneous (12 pts) (a) Determine an expression for the maximum voltage gain that can be obtained by this amplifier, the frequency at which it occurs, and its 3db bandwidth (4 points). VDD C R L At the resonant frequency, inductor and capacitor tune out and only the resistance is left at any other frequency, the impedance is lower. Hence the max gain equals g m R, with g m the transconductance of M (assuming that r o of M is much larger than R. It occurs at the resonant frequency ω vi 0 = sqr_root(1/lc). The 3db frequency is determined by the Q of the resonator. ω 3db = Δω/2 = R/2L. M vo Amax = ω max = ω 3db = (b) Find an expression for the transresistance of this famous bipolar circuit (3 points). V DD Each stage provides a current gain of (β F +1) (ass can be easily seen from the schematic). Hence the transresistance of the complete amplifier equals: v o /i in = (β F +1) 2 R L. i in Q1 Q2 v o EECS 105: FALL 06 MIDTERM 2 8
9 R m = (c) For the amplifier shown here, fill in how the signals v o1, v o2, v o1 v o2, v x change (,, or ) as a function of the changes in v i1, v i2, V cc, and T (temperature). Changes in v i1 and v i2 (when happening simultaneously) are by equal amounts. (5 points) v o1 V cc V cc v o2 v i1 v x v i2 v i1 v i2 V cc T v o1 v o2 v o1 v o2 v x or  (small increase) EECS 105: FALL 06 MIDTERM 2 9
10 PROBLEM 5: Biasing (12 points) VDD = 2.5V Iref = 100uA Vbias DC AC Rs M2 M1 M8 iout Iref1 RL M3 M5 Iref2 M4 M6 M7 VSS = 2.5V Consider the MOS amplifier given above, and assuming the following parameters: R L = 75K For NMOS transistors: μ ncox = 50 μ A /V 2, Vtn = 1.0V, λ n = 0.05 V 1 For PMOS transistors μ pcox = 25 μ A /V 2, Vtp = 1.0V, λ p = 0.05 V 1 Transistor sizes: M1: (W/L) 1 = 50/1 ( μ m / μm) M5: (W/L) 1 = 25/1 ( μ m / μm) M2: (W/L) 1 = 50/1 ( μ m / μm) M6: (W/L) 1 = 25/1 ( μ m / μm) M3: (W/L) 1 = 25/1 ( μ m / μm) M7: (W/L) 1 = 50/1 ( μ m / μm) M4: (W/L) 1 = 25/1 ( μ m / μm) M8: (W/L) 1 =? / 1 ( μ m / μm) a. Find the numerical value of the DC currents Iref1 and Iref2. (2 points) Iref1 = 100uA Iref2 = 200uA EECS 105: FALL 06 MIDTERM 2 10
11 b. Determine the DC bias voltage at the gate of M2 that maximizes the output (voltage) swing. (hint: the selected voltage should be such that the maximum output occurs when M1 and M2 are at the edge of saturation). (3 points) Vg2 Vsg2 Vdsat1 + Vdd = 0 Vg2 = Vdd Vsg2 Vdsat1 Vg2 = Vdd Vdsat2 Vdsat1  Vtp But, Vdsat1 = Vdsat2 = So Vdsat =.4V 2 * Iref 1 W Cox( ) L μp Vg2 = 2.5V 2*(.4)V 1.0V =.7V V G2 =.7V c. Size transistor M8 to accomplish the DC bias determined in b. (2 points) If you could not find the answer to b., you may assume that V G2 = 0.5V. We know that Vg2 = Vdd 2 Vdsat  Vtp Also, Iref2 = 1 W μ pcox( ) 8( Vsg Vtp )^2 2 L W 2* Iref 2 ( ) 8 = L μp Cox( Vsg Vtp )^2 W 2* Iref 2 ( ) 8 = L μpcox(2vdsatp)^2 Thus (W/L) 8 = (25/1) (W/L) 8 = (25/1) EECS 105: FALL 06 MIDTERM 2 11
12 d. Calculate the value of V BIAS so that I OUT (that is, the DC component of the output current) = 0. (you may ignore channel length modulation for this question). (2 points) Since Iout = 0A, all of Iref1 is flowing through the drain of M1. Thus, 1 W Also, Iref2 = μ pcox( ) 1( Vsg1 Vtp )^2 2 L Vsg1 = Vdsat1 + Vtp, Vg1 = Vbias = Vdd Vdsat1  Vtp Vg1 = 1.1V V BIAS = 1.1V e. Find the maximum amplitude of the sinusoidal input smallsignal voltage such that the output current is not clipped (again ignore channel length modulation). (3 points) We know that Vout min = Vss + Vtn + 2Vdsat = .7V Vout max = Vg2 + Vtp =.7V + 1V = 1.7V Thus, if we bias the DC output to be at 0V, the maximum amplitude of.7v can be attained, which is limited by Vout min. v max =.7V EECS 105: FALL 06 MIDTERM 2 12
13 EECS 105: FALL 06 MIDTERM 2 13
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