University of Toronto. Final Exam


 Brittany Ryan
 3 years ago
 Views:
Transcription
1 University of Toronto Final Exam Date  Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer  D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last page of test.. Calculator type unrestricted 3. Grading indicated by [ ]. Attempt all questions since a blank answer will certainly get 0. Question Mark Last Name: 6 Total First Name: Student #: (max grade = 36) page 1 of 9
2 [6] Question 1: Each correct answer is worth 0.5 marks. For the questions below, circle one of True [T] or False [F]. T F In the 1970 s and 1980 s, CMOS digital circuits became more popular than bipolar digital circuits due to their higher speed. T F Two ways to add dopants to a silicon substrate are ion implantation and injection. T F For the detailed MOS gate capacitance model, the gatebulk capacitance is 0 when the transistor is in triode. T F Channel length modulation of digital circuits is important as it reduces the speed of digital circuits. T F Elmore delay is not necessarily accurate in absolute prediction of an RC tree delay but if one minimizes the Elmore delay, generally, the RC tree delay is also minimized. T F Since dynamic gates precharge high then fall low during evaluation, a dynamic bus will never see twice the crosstalk capacitance due opposite switching during evaluation. T F It is not possible to make a symmetric CMOS 3input nand gate. T F Most flash memory is built as NOR memory architecture. T F Hot carrier injection is a selflimiting mechanism when putting electrons on a floating gate. T F A DRAM memory cell should be refreshed after every read of that cell. T F The pmos transistors in a SRAM memory cell generally do not affect read or write speed. T F Bitline twists are used in SRAM memory to reduce capacitance coupling and therefore increase memory speed. page of 9
3 [6] Question : Transistor equivalency says that that transistors in series having the same width is equivalent to a single transistor with that width and the lengths added together as shown below. For the case below (voltage, width and lengths shown), show that this is indeed true (not using transistor equivalency) by finding I D1 and I D3 and also find V 1. (Ignore body effect and finite output impedance). 3V 3V 3V V 1 I D1 W L W L 1 3V I D3 W L 3 = W ( L 1 + L ) W = 1µm L 1 = 0.5µm L = 0.5µm (transistor parameters on last page) page 3 of 9
4 [6] Question 3: Consider the d register shown below. D I 5 T 1 I 1 I I 6 T 3 I 3 I 4 Q CK I 7 I 8 T T 4 Assuming that each Tgate turns on/off according to it controlling signal edge, and defining the following delays: is the delay through the i th inverter T Ii T Gi T Ti is the delay through the i thtgate from its control input to its output is the delay through the i thtgate from its data input to its output a) Find T setup in terms of T Ii, T Gi and T Ti (be specific in terms of i ). b) Find T pcq in terms of T Ii, T Gi and T Ti (be specific in terms of i ). page 4 of 9
5 [6] Question 4: a) Explain why when a single logic signal is crossing from clock domain 1 to clock domain, the last logic element in clock domain 1 should be a register. Give an example where an error occurs if the last element is NOT a register. (Show a timing diagram in your example). b) A 3register synchronizer (1 register in clock domain 1 and 3 registers in clock domain ) uses registers with τ s = 500ps and t rd = 00ps. Assuming the input toggles at 10MHz, what is the minium clock period for which the mean time between failures is 1000 years? (Your clock period answer only needs to be accurate to 0%). page 5 of 9
6 [6] Question 5: A single CMOS inverter is sized with minimum transistor lengths of 0.5um, NMOS width of 1um and PMOS width of um. This inverter is driving a fixed capacitive load of 50fF. However, the output wire of the inverter also has 50fF capacitive coupling to another signalling wire which may or may not switch when the inverter switches. Estimate the fastest delay (either t dr or t df ) and slowest delay (either t dr or t df ) through the inverter taking into account the adjacent signalling wire. Use parameters on last page. page 6 of 9
7 [6] Question 6: a) An embedded SRAM contains bit words. If it is physically arranged in a square fashion, how many bits will be used in the row decode and how many bits will be used in the column decode? (assume the cell aspect ratio is square). b) A dynamic memory cell has a worst case leakage current of na (independent of voltage) and is refreshed every 100µs. If the power supply is 3V and the cell voltage should not leak lower than 1.8V, find the required cell capacitance value. c) In a DRAM memory, the sense amps are connected directly to the bit lines. In a SRAM memory, the sense amps are connected to the bit lines through isolation PMOS transistors. Explain why the isolation transistors are needed in an SRAM. Also, explain why the isolation transistors should NOT be used in a DRAM. page 7 of 9
8 (blank sheet for scratch calculations) page 8 of 9
9 ECE334 Digital Electronics Equation Sheet Constants: k = JK 1 ; q = C ; V T = kt q 6mV at 300 K; ε 0 = F/m ; k ox = 3.9 ; caps: C ox = ( k ox ε 0 ) t ox ; C j C j0 ( 1 + V R 0 ) M j = ; NMOS: β I ;(active) I D = 0.5β n ( V GS V tn ) n = µ n C ox ( W L) ; V tn > 0 ; V DS 0 ; (triode) D = β n (( V GS V tn )V DS ( V DS ) ) ; (triode) V DS ( V GS V tn ) ;(active) V DS ( V GS V tn ) ; V tn = V tn0 + γ( V SB + s s ) ; (( (subthreshold) I D I D0 e V GS V tn ) ( nv T )) V DS V T = ( 1 e ) ; PMOS: β I ;(active) I D = 0.5β p ( V GS V tp ) p = µ p C ox ( W L) ; V tp < 0 ; V DS 0 ; (triode) D = β p (( V GS V tp )V DS ( V DS ) ) ; (triode) V DS ( V GS V tp ) ;(active) V DS ( V GS V tp ) ; Simple cap model: C g = C ox WL ;if L min ; C gu C ox L min ; C g = C gu W ; C d = C s = C du W ; CMOS inverter: V TH = ( V DD + V tp + V tn r) ( 1 + r) ; r = ( µ n ( W L) n ) ( µ p ( W L) p ) ; RC delay est: t dr = t df = 1.τ ; τ = R eq C ; R eqn =.5 ( µ n C ox ( W L) n ( V DD V tn )) ; R eqp =.5 ( µ p C ox ( W L) p ( V DD + V tp )) ; ( W p W n ) opt = µ n µ p Unit delay est: t df t df1 = ( C L C L1 ) (( W L) n1 ( W L) n ) Min delay: t delay = τ inv ( C out C in ) ; total delay = Nfτ inv ; f N = C out C in ; usually f = 4 Power diss: P dyn = P 1 0 fc L V DD ; P dp = 0.5P 1 0 fv DD I peak ( t r + t f ); I peak = 0.5β n ( V TH V tn ) ; Elmore Delay: τ i C k R ik ; dist RC, τ RC ; k Interconnect: R = ( ρl) ( tw) ; R = ρ t ; C = ( ε ox wl) t ; C = ε ox lw ( h ( w h) ( t h) 0.5 ) ; Max delay constraint: T c t pcq + t pd + t setup Min Delay constraint:t hold t ccq + t cd Metastability: MTBF e T τ s = ( t rd F D F CLK ) SRAM: M3 is cell access transistor, M1 is inverter NMOS, M5 is inverter PMOS, SRAM read: W 1 W 3 ( V DD V A V tn ) ( ( ( V DD V tn )V A V A ) ) ; I cell = (( µ n C ox ) ) ( W 3 L) ( V DD V tn ) V BL = ( I cell t) C BL SRAM write: W 3 W 5 ( µ p ( V DD + V tp ) ) ( µ n (( V DD V tn )V A V A ) ) MOS Transistor; CMOS basic parameters. Channel length = 0.5µm, m j = 0.5, o = 0.9V V T0 ( V) γ ( V 0.5 ) µc ox ( µa V ) λ ( V 1 ) C ox ( ff µm ) C o ( ff µm) C j ( ff µm ) C jsw ( ff µm) NMOS PMOS V T0 is the threshold voltage with zero bulksource voltage; γ is used to account for nonzero bulksource voltage; µc ox is the transistor current gain parameter; λ is to account for the transistor finite output impedance (channel length modulation); is the gate capacitance per unit area; is the gate overlap capacitance per unit length; is the drain/source junction C o capacitance per unit area; C jsw is the drain/source junction capacitance per unit length to account for drain/source perimeter capacitance. Assume this value is the same for all perimeters C ox C j page 9 of 9
Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
1 Introduction to TransistorLevel Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2018 Final Monday, Apr 0 5 Problems with point weightings shown.
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date  Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer  D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationName: Answers. Mean: 83, Standard Deviation: 12 Q1 Q2 Q3 Q4 Q5 Q6 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering CircuitLevel Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Final Tuesday, December 15 Problem weightings
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2016 Final Friday, May 6 5 Problems with point weightings shown.
More informationEEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
More informationEE141Fall 2011 Digital Integrated Circuits
EE4Fall 20 Digital Integrated Circuits Lecture 5 Memory decoders Administrative Stuff Homework #6 due today Project posted Phase due next Friday Project done in pairs 2 Last Lecture Last lecture Logical
More informationDigital Integrated Circuits A Design Perspective
Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures
More informationDigital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories
Digital Integrated Circuits A Design Perspective Semiconductor Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification
More informationCMOS Digital Integrated Circuits Lec 13 Semiconductor Memories
Lec 13 Semiconductor Memories 1 Semiconductor Memory Types Semiconductor Memories Read/Write (R/W) Memory or Random Access Memory (RAM) ReadOnly Memory (ROM) Dynamic RAM (DRAM) Static RAM (SRAM) 1. Mask
More informationSemiconductor Memories
Semiconductor References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian
More informationVLSI Design and Simulation
VLSI Design and Simulation Performance Characterization Topics Performance Characterization Resistance Estimation Capacitance Estimation Inductance Estimation Performance Characterization Inverter Voltage
More information3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C. 4. Design a layout diagram for the CMOS logic shown below [16]
Code No: RR420203 Set No. 1 1. (a) Find g m and r ds for an nchannel transistor with V GS = 1.2V; V tn = 0.8V; W/L = 10; µncox = 92 µa/v 2 and V DS = Veff + 0.5V The out put impedance constant. λ = 95.3
More informationPower Dissipation. Where Does Power Go in CMOS?
Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit
More informationCARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
More informationErrata of K Introduction to VLSI Systems: A Logic, Circuit, and System Perspective
Errata of K13126 Introduction to VLSI Systems: A Logic, Circuit, and System Perspective Chapter 1. Page 8, Table 11) The 0.35µm process parameters are from MOSIS, both 0.25µm and 0.18µm process parameters
More information5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
More informationThe Devices. Devices
The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ FieldOxyde (SiO 2 ) psubstrate p+ stopper Bulk Contact CROSSSECTION of NMOS Transistor CrossSection of CMOS Technology MOS transistors
More informationHw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today
EECS141 1 Hw 8 Posted Last one to be graded Due Friday April 30 Hw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today EECS141 2 1 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 Frequency
More informationSemiconductor Memory Classification
Semiconductor Memory Classification ReadWrite Memory NonVolatile ReadWrite Memory ReadOnly Memory Random Access NonRandom Access EPROM E 2 PROM MaskProgrammed Programmable (PROM) SRAM FIFO FLASH
More informationSemiconductor memories
Semiconductor memories Semiconductor Memories Data in Write Memory cell Read Data out Some design issues : How many cells? Function? Power consuption? Access type? How fast are read/write operations? Semiconductor
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 111:3 Thursday, October 6, 6:38:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationEEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " DLatch " Timing Constraints! Dynamic Logic " Domino
More informationC.K. Ken Yang UCLA Courtesy of MAH EE 215B
Decoders: Logical Effort Applied C.K. Ken Yang UCLA yang@ee.ucla.edu Courtesy of MAH 1 Overview Reading Rabaey 6.2.2 (Ratioed logic) W&H 6.2.2 Overview We have now gone through the basics of decoders,
More informationLecture 25. Semiconductor Memories. Issues in Memory
Lecture 25 Semiconductor Memories Issues in Memory Memory Classification Memory Architectures TheMemoryCore Periphery 1 Semiconductor Memory Classification RWM NVRWM ROM Random Access NonRandom Access
More informationDigital Integrated Circuits EECS 312
14 12 10 8 6 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) 0 1950 1960 1970 1980
More informationAnnouncements. EE141 Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power
 Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 123pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances
More informationInterconnects. Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters. ECE 261 James Morizio 1
Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 James Morizio 1 Introduction Chips are mostly made of wires called interconnect In stick diagram,
More informationGMU, ECE 680 Physical VLSI Design 1
ECE680: Physical VLSI Design Chapter VIII Semiconductor Memory (chapter 12 in textbook) 1 Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies
More informationTopics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
More informationLecture 34: Portable Systems Technology Background Professor Randy H. Katz Computer Science 252 Fall 1995
Lecture 34: Portable Systems Technology Background Professor Randy H. Katz Computer Science 252 Fall 1995 RHK.F95 1 Technology Trends: Microprocessor Capacity 100000000 10000000 Pentium Transistors 1000000
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationEECS 151/251A Homework 5
EECS 151/251A Homework 5 Due Monday, March 5 th, 2018 Problem 1: Timing The datapath shown below is used in a simple processor. clk rd1 rd2 0 wr regfile 1 0 ALU REG 1 The elements used in the design have
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2018 Memory Overview, Memory Core Cells Today! Charge Leakage/Charge Sharing " Domino Logic Design Considerations! Logic Comparisons!
More informationAnswers. Name: Grade: Q1 Q2 Q3 Q4 Total mean: 83, stdev: 14. ESE370 Fall 2017
University of Pennsylvania Department of Electrical and System Engineering CircuitLevel Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2017 Midterm 2 Monday, November 6 Point values
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More informationEE 434 Lecture 33. Logic Design
EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The twoinverter loop X Y X
More informationChapter 4 FieldEffect Transistors
Chapter 4 FieldEffect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 41 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationChapter Overview. Memory Classification. Memory Architectures. The Memory Core. Periphery. Reliability. Memory
SRAM Design Chapter Overview Classification Architectures The Core Periphery Reliability Semiconductor Classification RWM NVRWM ROM Random Access NonRandom Access EPROM E 2 PROM MaskProgrammed Programmable
More informationVLSI Design, Fall Logical Effort. Jacob Abraham
6. Logical Effort 6. Logical Effort Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 207 September 20, 207 ECE Department, University of
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: TwoInput NOR Gate (NOR2)
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 14: March 1, 2016 Combination Logic: Ratioed and Pass Logic Lecture Outline! CMOS Gates Review " CMOS Worst Case Analysis! Ratioed Logic Gates!
More informationSemiconductor Memories
!"#"$%&'()$*#+%$*,' "+./"$0 1'!*0"#)'2*+03*.$"4* Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Semiconductor Memories December 20, 2002 !"#$%&'()*&'*+&, Memory Classification Memory Architectures
More informationSpiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp
27.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 27.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance
More information! Charge Leakage/Charge Sharing. " Domino Logic Design Considerations. ! Logic Comparisons. ! Memory. " Classification. " ROM Memories.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing
EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104113) S R on D CMOS Manufacturing Process (pp. 3646) S S C GS G G C GD
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationEECS 312: Digital Integrated Circuits Final Exam Solutions 23 April 2009
Signature: EECS 312: Digital Integrated Circuits Final Exam Solutions 23 April 2009 Robert Dick Show your work. Derivations are required for credit; end results are insufficient. Closed book. You may use
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationCheck course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory
EE141 Fall 005 Lecture 6 MOS Capacitances, Propagation elay Important! Check course home page periodically for announcements Homework is due TOAY by 5pm In 40 Cory Homework 3 will be posted TOAY ue Thursday
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Oldham Fall 1999
UNIVERSITY OF CLIFORNI College of Engineering Department of Electrical Engineering and Computer Sciences Professor Oldham Fall 1999 EECS 40 FINL EXM 13 December 1999 Name: Last, First Student ID: T: Kusuma
More informationName: Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering CircuitLevel Modeling, Design, and Optimization for Digital Systems ESE370, Fall 205 Midterm Wednesday, November 4 Point values
More informationSEMICONDUCTOR MEMORIES
SEMICONDUCTOR MEMORIES Semiconductor Memory Classification RWM NVRWM ROM Random Access NonRandom Access EPROM E 2 PROM MaskProgrammed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 23, 2017 Energy and Power Optimization, Design Space Exploration, Synchronous MOS Logic Lecture Outline! Energy and Power Optimization
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 21: April 4, 2017 Memory Overview, Memory Core Cells Penn ESE 570 Spring 2017 Khanna Today! Memory " Classification " ROM Memories " RAM Memory
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay
More informationEE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR
EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX =  4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3
More informationECE321 Electronics I
ECE321 Electronics I Lecture 1: Introduction to Digital Electronics Payman ZarkeshHa Office: ECE Bldg. 230B Office hours: Tuesday 2:003:00PM or by appointment Email: payman@ece.unm.edu Slide: 1 Textbook
More informationEE141 Fall 2002 Lecture 27. Memory EE141. Announcements. We finished all the labs No homework this week Projects are due next Tuesday 9am EE141
 Fall 2002 Lecture 27 Memory Announcements We finished all the labs No homework this week Projects are due next Tuesday 9am 1 Today s Lecture Memory:» SRAM» DRAM» Flash Memory 2 Floatinggate transistor
More informationEE241  Spring 2000 Advanced Digital Integrated Circuits. References
EE241  Spring 2000 Advanced Digital Integrated Circuits Lecture 26 Memory References Rabaey, Digital Integrated Circuits Memory Design and Evolution, VLSI Circuits Short Course, 1998.» Gillingham, Evolution
More informationF14 Memory Circuits. Lars Ohlsson
Lars Ohlsson 20181018 F14 Memory Circuits Outline Combinatorial vs. sequential logic circuits Analogue multivibrator circuits Noise in digital circuits CMOS latch CMOS SR flip flop 6T SRAM cell 1T DRAM
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, AddisonWesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationP. R. Nelson 1 ECE418  VLSI. Midterm Exam. Solutions
P. R. Nelson 1 ECE418  VLSI Midterm Exam Solutions 1. (8 points) Draw the crosssection view for AA. The crosssection view is as shown below.. ( points) Can you tell which of the metal1 regions is the
More informationS No. Questions Bloom s Taxonomy Level UNITI
GROUPA (SHORT ANSWER QUESTIONS) S No. Questions Bloom s UNITI 1 Define oxidation & Classify different types of oxidation Remember 1 2 Explain about Ion implantation Understand 1 3 Describe lithography
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More information! Memory. " RAM Memory. ! Cell size accounts for most of memory array size. ! 6T SRAM Cell. " Used in most commercial chips
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec : April 3, 8 Memory: Core Cells Today! Memory " RAM Memory " Architecture " Memory core " SRAM " DRAM " Periphery Penn ESE 57 Spring 8  Khanna
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationVLSI GATE LEVEL DESIGN UNIT  III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI UNIT  III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationTopics to be Covered. capacitance inductance transmission lines
Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
More informationECE 342 Electronic Circuits. Lecture 34 CMOS Logic
ECE 34 Electronic Circuits Lecture 34 CMOS Logic Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 De Morgan s Law Digital Logic  Generalization ABC... ABC...
More informationExam 2Solutions ECE 410
NME: Exam Solutions ECE 40 uring this exam you are allowed to use a calculator and the equations sheet provided. You are not allowed to speak to or exchange books, papers, calculators, etc. with other
More informationObjective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components
Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the
More informationEE 330 Lecture 37. Digital Circuits. Other Logic Families. Propagation Delay basic characterization Device Sizing (Inverter and multipleinput gates)
EE 330 Lecture 37 Digital Circuits Other Logic Families Static Power Dissipation Propagation Delay basic characterization Device Sizing (Inverter and multipleinput gates) Review from Last Time Inverter
More informationInterconnects. Introduction
Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 Krish Chakrabarty 1 Introduction Chips are mostly made of ires called interconnect In stick diagram,
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationFloating Point Representation and Digital Logic. Lecture 11 CS301
Floating Point Representation and Digital Logic Lecture 11 CS301 Administrative Daily Review of today s lecture w Due tomorrow (10/4) at 8am Lab #3 due Friday (9/7) 1:29pm HW #5 assigned w Due Monday 10/8
More informationHightoLow Propagation Delay t PHL
HightoLow Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (nchannel) immediately switches from cutoff to saturation; the pchannel pullup switches from triode to
More informationUniversity of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA
University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm 3 @
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 26, 2019 Energy Optimization & Design Space Exploration Penn ESE 570 Spring 2019 Khanna Lecture Outline! Energy Optimization! Design
More informationSemiconductor Memories
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Semiconductor Memories December 20, 2002 Chapter Overview Memory Classification Memory Architectures
More informationVery Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. MadianVLSI Contents Delay estimation Simple RC model PenfieldRubenstein Model Logical effort Delay
More information6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) OPEN BOOK Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
More information2007 Fall: Electronic Circuits 2 CHAPTER 10. DeogKyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits DeogKyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
More informationMOS Transistor IV Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor IV Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationL ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling
L13 04202017 ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling Scaling laws: Generalized scaling (GS) p. 610 Design steps p.613 Nanotransistor issues (page 626) Degradation
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Total Power. Energy and Power Optimization. Worksheet Problem 1
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 20, 2018 Energy and Power Optimization, Design Space Exploration Lecture Outline! Energy and Power Optimization " Tradeoffs! Design
More informationEE 330 Lecture 36. Digital Circuits. Transfer Characteristics of the Inverter Pair One device sizing strategy Multipleinput gates
EE 330 Lecture 36 Digital Circuits Transfer Characteristics of the Inverter Pair One device sizing strategy Multipleinput gates Review from Last Time The basic logic gates It suffices to characterize
More information