Lecture 06: Current Mirrors

Transcription

1 Lecture 06: Current Mirrors Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture VI 1 / 26

2 Lowered Resistance Looking into Source The functional description of a current mirror is that it should copy a current. A current mirror can also have a gain α I out = αi in I out = I in Dr. Ryan Robucci Lecture VI 2 / 26

3 Dependence on Output Voltage A good current mirror will have only a small dependence on Vout: I out = αi in + βv out where β is ideally ZERO. If β is small, Rout does not depend on the load. Dr. Ryan Robucci Lecture VI 3 / 26

4 Basic Current Mirror Key Characteristics: Current Input, Current output Rin, Rout Input Voltage Range, Output Voltage Range Gain Linearity Dr. Ryan Robucci Lecture VI 4 / 26

5 Behavior Two transistors with the same build and the same gate, drain, source, and bulk potentials conduct the same current. The gate and drain voltages both have an impact on current, but the gate matters more. Dr. Ryan Robucci Lecture VI 5 / 26

6 Mirror Node Behavior Mirror Node Behavior: dv M dt = I in I ds1 C M DC condition: assume sat, λ = 0 ( I in = I ds1 = k WL ) 2 2I V ov1 = in k ( W L ) 1 1 V 2 ov1 Feedback Computes Inverse of I DS (V g ) Function! Answers: What gate voltage is required to conduct a specied current? Computed Gate Voltage Applied to M2: Dene: V M = V ov1 + V TH1 I out = k 2 I out = k 2 I out = k 2 I out = k 2 ( WL ) 2 ( WL ) ( WL )2 (V M V TH2 ) 2 2 V 2 ov2 ( WL )2 (V ov1 + V TH1 V TH2 ) 2 ( 2I in k ( W L ) 1 + V TH1 V TH2 If V TH1 == V TH2, ) 2 I out = ( W L ) 2 ( W L ) 1 I in Dr. Ryan Robucci Lecture VI 6 / 26

7 Saturation assumptions Revisit the assumptions of saturation. M1: V d1 > V g1 V TH1 (1) Note V d1 = V g1 (2) V d1 > V d1 V TH1 (obviously true if V TH1 > 0) V d1 > V g1 V TH1 Key Analog Knowledge on Diode-Connected FETs: Diode connected transistor in above-vt operation mode is always in saturation M2: V d2 > V g1 V TH2 V out > V ov2 (V ov2 determined by I out,w 2,L 2 ) 2I V out > out = V k ( W L ) out,min 2 Saturation condition constrains allowable output range Dr. Ryan Robucci Lecture VI 7 / 26

8 Eect of Channel Length Modulation (Eect of Drain Voltage) Now considering Channel Length Modulation and computing V M then I out as before: ( W ) L λv I out = I in ) ds2 1 + λv ds1 ( W L Even if λ 1 == λ 2 and can have 1+λV ds2 1+λV ds1 1 since there is no guarantee that V ds1 == V ds2. 2 Dr. Ryan Robucci Lecture VI 8 / 26

9 Eect of Channel Length Modulation (Eect of Drain Voltage) Assume: W 1 = W 2 = W ; L 1 = L 2 = L ;λ 1 = λ 2 = λ Examine λ 1 eect with V DS2 held xed: R in (determines V M in DC): di out di in = di out dv M }{{} G M2 dv M di in }{{} R IN i in = v M g m1 + 1 R in = v M 1 iin = g m1 +g sd1 R in 1 g m1 if g m1 1 r ds1 G M2 : G m2 = g m2 r ds1 }{{} g ds1 Dr. Ryan Robucci Lecture VI 9 / 26

10 Eect of Channel Length Modulation (Eect of Drain Voltage) di out di in = di out dv M }{{} G M2 dv M di in }{{} R IN di out di in = g m2 g m1 +g ds1? g m2 g m1 }{{} ( W L ) ideally 2 ( W L ) 1 Ideally g ds1 is small so that we can ignore it: g ds I λ g m L = λ ( ) 0 1 2I 0 L 2 Ik W L k ( W L ) by keeping W L constant and increasing L, the eect of g ds on the V M calculation is reduced otherwise, the current mirror gain is K ( W L ) 2 ( W L ) 1 where K = g m1 g m1 +g and sd1 0 < K < 1 Dr. Ryan Robucci Lecture VI 10 / 26

11 Eect of Channel Length Modulation (Eect of Drain Voltage) Intuitive Explanation for K: ideal V M is calculated according to inverse of g m1 when V M is calculated according to inverse of g m1 + g ds1, V M is smaller So, g ds1 causes reduction in output current Now examine the current mirror's behavioral dependence on output voltage Dr. Ryan Robucci Lecture VI 11 / 26

12 Eect of Channel Length Modulation (Eect of Drain Voltage) Examine dependence on output voltage with input current (and V M ) xed: di out dv out = (R out ) 1 = (r ds1 ) 1 to make I out independent of R L and V out R out should be large, making L 2 large helps: R out = r ds2 = 1 L λ 2 I ; λ 2 = λ 0 0 L 2 Dr. Ryan Robucci Lecture VI 12 / 26

13 Drain Voltage Matching : represents known load resistor or known output voltage For best current matching, want V d1 = V d2 and L 1 = L 2 in addition to V g1 = V g2. Several non-ideal second-order behaviors are better matched in parallel when transistor dimensions and all voltages match. as I in increases, V m increases => V d1 increases V out decreases if set by resistor or is xed by another load I out = I in ( W L ) 1 ( W L ) 2 1+λV ds2 1+λV ds1 predicts degraded behavior Dr. Ryan Robucci Lecture VI 13 / 26

14 Drain Voltage Matching ( I out = I W L ) 1 1+λV ds2 in ( W L ) 1+λV ds1 2 Since V DS2 and V DS1 can't match at all currents, may at least achieve V D1 = V D2 at some bas point given V out,bias design V ov1 : V M = V ov1 + V TH1 = V out,bias V ov1 = V out,bias V TH1 ( 2I ) = V W out,bias V TH1 k L 1 }{{} design W L Dr. Ryan Robucci Lecture VI 14 / 26

15 Cascoded-Output Mirrors To increase output resistance, and make the output current less sensitive to output voltage, a cascode can be used: R out g s rds 2 (good) R in 1 g m This R out is good, but lets study the current to current transfer function: Dr. Ryan Robucci Lecture VI 15 / 26

16 Current-to-current Transfer Function As I in increases, V M increases to support the additional current in M1 V S4 decreases to support the additional current in M4 as a result V d1 increases yet V d2 decreases ( I out = I W L ) 1 1+λV ds2 in ( W L ) 1+λV predicts poor behavior (but not as bad as ds1 2 prev.) As before, we can at least design M3 to get V D2 = V D1 at a specied bias current V D1 V ov1 + V TH1 = V M V D2 V cas V TH3 V ov3 so, set V cas = [V M ] + V TH3 + V ov3 = [V ov1 + V TH1 ] + V TH3 + V Dr. Ryan Robucci Lecture VI ov3 16 / 26

17 Output Range For precision matching biasing: V cas = 2V ov + 2V TH (big O) V out,min = V cas V TH3 V out,min = 2V ov + V TH (big O) if high R out is needed rather than precision matching, may set V cas = V ov2 + V TH3 + V OV 3 V out,min = V cas V TH3 = V ov2 + V OV 3 V out,min = 2V ov (big O) Dr. Ryan Robucci Lecture VI 17 / 26

18 Self Biasing Easy design that generates V c Since V gs3 V gs4 and V g3 = V g4 V x V M => The varying V c keeps lower drain voltages matched V C = 2V on + 2V TH (big O) V out,min = 2V on + V TH (big O) R in 2 1 g m Input Voltage:V TH1 + V OV 1 + V TH3 + V OV 3 2V TH + 2V OV (big O) ( I out = I W L ) 1 1+λV ds2 in ( W L ) 1+λV ds1 2 predicts good current matching behavior Dr. Ryan Robucci Lecture VI 18 / 26

19 Wide-Range Biasing Output Resistance: R out g s4 r ds4 r ds2 R out g s rds 2 (big O) Input Resistance: R in 1 g m1 Why? :Super FET with eective drain conductance (g m3 r ds3 )r ds1 1 R in = 1 g m1 + (g m3 r ds3 )r ds1 Eect of V g1 of on current is much larger than that of a changing V d3 on the cascode structure Dr. Ryan Robucci Lecture VI 19 / 26

20 Wide-Range Biasing Lower R in is good for current input port less dependence on V in holds V in xed lowers input node time constant Output Range: V out > V cas V TH3 = V out,min if V cas = V OV 3 + V TH2 + V OV 4 + V TH4 Input Voltage: V out,min = V ov2 + V TH2 + V OV 4 V out,min = 2V ov + V TH (big O) V in = V ov1 + V TH1 For both transistors to be in saturation (above-threshold) a lower bound on the input voltage is V in > V ov1 + V ov3 So, we requirev ov3 < V TH1. Design ( ) W L 3 AND V cas accordingly Design ( ) W L,V 3 cas according to maximum input current Dr. Ryan Robucci Lecture VI 20 / 26

21 Other Biasing Circuits (1) Want V cas V M V TH1 + V TH3 + V OV 3 V CAS V M = V TH1 + V TH3 + V OV 3 = V R so, set R = V TH1+V TH3 +V OV 3 I in then, R in R + 1 g m1 (derive as practice) Input voltage: V TH1 + V OV 1 + V TH3 + V OV 3 Dr. Ryan Robucci Lecture VI 21 / 26

22 Other biasing Circuits (2) Dr. Ryan Robucci Lecture VI 22 / 26

23 Other Biasing Circuits (3) V cas = (V TH5 + V OV 5 ) + (V TH6 + V OV 6 ) (V TH7 + V OV 7 ) make ( ) W L 7 large, so large that V ov7 0 then V cas V ov + 2V TH Dr. Ryan Robucci Lecture VI 23 / 26

24 Multiplying Mirrors Multiplying W's in output leg creates a current multiplication: Multiply W 2 & W 4 by M let I out = M I in 2I V ov1 = in k ( W L ) 1 2I V ov2 = out 2[M I = in ] k ( W L ) 2 k [M ( W L ) 1 ] biasing is maintained as output leg widths are increased Dr. Ryan Robucci Lecture VI 24 / 26

25 Bidirectional Current Mirror I out = I 1 + I in I 2 =that of the mirror I out I in Dr. Ryan Robucci Lecture VI 25 / 26

26 Active Cascode Current Mirror Uses feedback to increase output resistance (derived in HW) Will discuss feedback later. Dr. Ryan Robucci Lecture VI 26 / 26