Chapter 2. Introduction. Chapter 2 :: Topics. Circuits. Nodes. Circuit elements. Introduction

Transcription

1 hapter 2 Introduction igital esign and omputer rchitecture, 2 nd Edition avid Money Harris and Sarah L. Harris logic circuit is composed of: Inputs Outputs Functional specification Timing specification inputs functional spec timing spec outputs hapter 2 <> hapter 2 <3> hapter 2 :: Topics ircuits Introduction oolean Equations oolean lgebra From Logic to Gates Multilevel ombinational Logic s and Z s, Oh My Karnaugh Maps ombinational uilding locks Timing Nodes Inputs:,, Outputs:, Z Internal: n ircuit elements E, E2, E3 Each a circuit E E2 n E3 Z hapter 2 <2> hapter 2 <4>

2 Types of Logic ircuits ombinational Logic Memoryless Outputs determined by current values of inputs Sequential Logic Has memory Outputs determined by previous and current values of inputs inputs functional spec timing spec outputs oolean Equations Functional specification of outputs in terms of inputs Example: S = F(,, in ) out = F(,, in ) S L out in S = in out = + in + in hapter 2 <5> hapter 2 <7> Rules of ombinational omposition Every element is combinational Every node is either an input or connects to exactly one output The circuit contains no cyclic paths Example: hapter 2 <6> Some efinitions omplement: variable with a bar over it,, Literal: variable or its complement,,,,, Implicant: product of literals,, Minterm: product that includes all input variables,, Maxterm: sum that includes all input variables (++), (++), (++) hapter 2 <8> 2

3 Sum of Products (SOP) Form ll equations can be written in SOP form Each row has a minterm minterm is a product (N) of literals Each minterm is TRUE for that row (and only that row) Form function by ORing minterms where the output is TRUE Thus, a sum (OR) of products (N terms) minterm minterm name m m m 2 m 3 Sum of Products (SOP) Form ll equations can be written in SOP form Each row has a minterm minterm is a product (N) of literals Each minterm is TRUE for that row (and only that row) Form function by ORing minterms where the output is TRUE Thus, a sum (OR) of products (N terms) minterm minterm name m m m 2 m 3 = F(, ) = hapter 2 <9> = F(, ) = + = Σ(, 3) hapter 2 <> Sum of Products (SOP) Form Product of Sums (POS) Form ll equations can be written in SOP form Each row has a minterm minterm is a product (N) of literals Each minterm is TRUE for that row (and only that row) Form function by ORing minterms where the output is TRUE Thus, a sum (OR) of products (N terms) = F(, ) = minterm minterm name m m m 2 m 3 hapter 2 <> ll oolean equations can be written in POS form Each row has a maxterm maxterm is a sum (OR) of literals Each maxterm is FLSE for that row (and only that row) Form function by Ning the maxterms for which the output is FLSE Thus, a product (N) of sums (OR terms) maxterm maxterm name + M + M + M 2 + M 3 = F(, ) = ( + )( + )= Π(, 2) hapter 2 <2> 3

4 oolean Equations Example ou are going to the cafeteria for lunch ou won t eat lunch (E) If it s not open (O) or If they only serve corndogs () Write a truth table for determining if you will eat lunch (E). O E hapter 2 <3> SOP & POS Form SOP sum of products O E POS product of sums O minterm O O O O maxterm O + O + O + O + hapter 2 <5> oolean Equations Example SOP & POS Form ou are going to the cafeteria for lunch ou won t eat lunch (E) If it s not open (O) or If they only serve corndogs () Write a truth table for determining if you will eat lunch (E). O E hapter 2 <4> SOP sum of products O E POS product of sums O E minterm O O O O maxterm O + O + O + O + = O = Σ(2) = (O + )(O + )(O + ) = Π(,, 3) hapter 2 <6> 4

5 oolean lgebra xioms and theorems to simplify oolean equations Like regular algebra, but simpler: variables have only two values ( or ) uality in axioms and theorems: Ns and ORs, s and s interchanged T: Identity Theorem = + = hapter 2 <7> hapter 2 <9> oolean xioms T: Identity Theorem = + = = = hapter 2 <8> hapter 2 <2> 5

6 T2: Null Element Theorem = + = T3: Idempotency Theorem = + = hapter 2 <2> hapter 2 <23> T2: Null Element Theorem = + = T3: Idempotency Theorem = + = = = = = hapter 2 <22> hapter 2 <24> 6

7 T4: Identity Theorem = T5: omplement Theorem = + = hapter 2 <25> hapter 2 <27> T4: Identity Theorem = T5: omplement Theorem = + = = = = hapter 2 <26> hapter 2 <28> 7

8 oolean Theorems Summary Simplifying oolean Equations Example : = + hapter 2 <29> hapter 2 <3> oolean Theorems of Several Vars Simplifying oolean Equations Example : = + = ( + ) T8 = () T5 = T hapter 2 <3> hapter 2 <32> 8

9 Simplifying oolean Equations emorgan s Theorem Example 2: = ( + ) = = + = + = hapter 2 <33> hapter 2 <35> Simplifying oolean Equations ubble Pushing Example 2: = ( + ) = (( + )) T8 = (()) T2 ackward: ody changes dds bubbles to inputs = () T = () T7 = T3 Forward: ody changes dds bubble to output hapter 2 <34> hapter 2 <36> 9

10 ubble Pushing What is the oolean expression for this circuit? ubble Pushing Rules egin at output, then work toward inputs Push bubbles on final output back raw gates in a form so bubbles cancel hapter 2 <37> hapter 2 <39> ubble Pushing ubble Pushing Example What is the oolean expression for this circuit? = + hapter 2 <38> hapter 2 <4>

11 ubble Pushing Example ubble Pushing Example no output bubble no output bubble no bubble on input and output = + bubble on input and output hapter 2 <4> hapter 2 <43> ubble Pushing Example From Logic to Gates no output bubble Two level logic: Ns followed by ORs Example: = + + bubble on input and output minterm: minterm: minterm: hapter 2 <42> hapter 2 <44>

12 ircuit Schematics Rules Multiple Output ircuits Inputs on the left (or top) Outputs on right (or bottom) Gates flow from left to right Straight wires are best Example: Priority ircuit Output asserted corresponding to most significant TRUE input 3 2 PRIORIT iiruit hapter 2 <45> hapter 2 <47> ircuit Schematic Rules (cont.) Multiple Output ircuits Wires always connect at a T junction dot where wires cross indicates a connection between the wires Wires crossing without a dot make no connection wires connect at a T junction wires connect at a dot wires crossing without a dot do not connect Example: Priority ircuit Output asserted corresponding to most significant TRUE input 3 2 PRIORIT iiruit hapter 2 <46> hapter 2 <48> 2

13 Priority ircuit Hardware ontention: ontention: circuit tries to drive output to and ctual value somewhere in between ould be,, or in forbidden zone Might change with voltage, temperature, time, noise Often causes excessive power dissipation = = = Warnings: ontention usually indicates a bug. is used for don t care and contention look at the context to tell them apart hapter 2 <49> hapter 2 <5> on t ares Floating: Z hapter 2 <5> 3 2 Floating, high impedance, open, high Z Floating output might be,, or somewhere in between voltmeter won t indicate whether a node is floating Tristate uffer E E Z Z hapter 2 <52> 3

14 Tristate usses Floating nodes are used in tristate busses Many different drivers Exactly one is active at once processor en to bus from bus video en2 to bus from bus Ethernet en3 to bus from bus memory en4 to bus from bus shared bus K Map ircle s in adjacent squares In oolean expression, include only literals whose true and complement form are not in the circle = hapter 2 <53> hapter 2 <55> Karnaugh Maps (K Maps) 3 Input K Map oolean expressions can be minimized by combining terms K maps minimize equations graphically P + P = P Truth Table K-Map hapter 2 <54> hapter 2 <56> 4

15 3 Input K Map Truth Table K-Map = + hapter 2 <57> K Map Rules Every must be circled at least once Each circle must span a power of 2 (i.e., 2, 4) squares in each direction Each circle must be as large as possible circle may wrap around the edges don't care () is circled only if it helps minimize the equation hapter 2 <59> K Map efinitions 4 Input K Map omplement: variable with a bar over it,, Literal: variable or its complement,,,,, Implicant: product of literals,, Prime implicant: implicant corresponding to the largest circle in a K map hapter 2 <58> hapter 2 <6> 5

16 4 Input K Map K Maps with on t ares hapter 2 <6> hapter 2 <63> 4 Input K Map K Maps with on t ares = hapter 2 <62> hapter 2 <64> 6

17 K Maps with on t ares Multiplexer (Mux) = + + hapter 2 <65> Selects between one of N inputs to connect to output log 2 N bit select input control input Example: 2: Mux S S S hapter 2 <67> ombinational uilding locks Multiplexer Implementations Multiplexers ecoders Logic gates Sum of products form S Tristates For an N-input mux, use N tristates Turn on exactly one to select the appropriate input S = S + S S hapter 2 <66> hapter 2 <68> 2 <68> 7

18 Logic using Multiplexers Using the mux as a lookup table = hapter 2 <69> ecoders N inputs, 2 N outputs One-hot outputs: only one output HIGH at once 2:4 ecoder hapter 2 <7> Logic using Multiplexers ecoder Implementation Reducing the size of the mux = 3 2 hapter 2 <7> hapter 2 <72> 8

19 Logic Using ecoders Propagation & ontamination elay OR minterms 2:4 ecoder Minterm Propagation delay: t pd = max delay from input to output ontamination delay: t cd = min delay from input to output t pd = + = t cd Time hapter 2 <73> hapter 2 <75> Timing elay between input change and output changing How to build fast circuits? delay Propagation & ontamination elay elay is caused by apacitance and resistance in a circuit Speed of light limitation Reasons why t pd and t cd may be different: ifferent rising and falling delays Multiple inputs and outputs, some of which are faster than others ircuits slow down when hot and speed up when cold Time hapter 2 <74> hapter 2 <76> 9

20 ritical (Long) & Short Paths n ritical Path Short Path n2 ritical (Long) Path: t pd = 2t pd_n + t pd_or Short Path: t cd = t cd_n Glitch Example What happens when =, =, falls? = + hapter 2 <77> hapter 2 <79> Glitches Glitch Example (cont.) When a single input change causes multiple output changes = = = Short Path ritical Path n = n2 n2 n hapter 2 <78> Time glitch hapter 2 <8> 2

21 Fixing the Glitch = + + = = = = hapter 2 <8> Why Understand Glitches? Glitches don t cause problems because of synchronous design conventions (see hapter 3) It s important to recognize a glitch: in simulations or on oscilloscope an t get rid of all glitches simultaneous transitions on multiple inputs can also cause glitches hapter 2 <82> 2