K-map Definitions. abc

Size: px
Start display at page:

Download "K-map Definitions. abc"

Transcription

1 K-map efinitions b a bc Implicant ny single or any group of s is called an implicant of F. ny possible grouping of s is an implicant. b a Prime Implicant implicant that cannot be combined with some other implicant to eliminate a variable 3 Minimum Sum-Of-Products (SOP) The minimum SOP expression consists of some (but not necessarily all) of the prime implicants of a function. If a SOP expression contains a term which is NOT a prime implicant, then it NNOT be minimum. 2

2 Prime Implicants EH of these coverings is a PRIME IMPLINT (i.e. cannot be reduced) b, d, d Minimum SOP will have some or all of these prime implicants. The included prime implicants must cover all of the ONEs. F(,,,) = b + d (minimum set of PIs) = b + d + d (valid set of PIs, but not minimum) d + d (both PI s, but all s not included!) 3 Non-Essential vs. Essential Prime Implicants EH of the coverings is a PRIME IMPLINT. b, d, d F(,,,) = b + d (minimum # of PIs) NON-ESSENTIL prime implicant Prime Implicant d is non-essential because its s are covered by other PIs. PI is ESSENTIL if it covers a MINTERM that cannot be covered by any other PI. 4 2

3 n example with more than one solution EH of the coverings is a PRIME IMPLINT. acd bd bcd Recall that a covering is a Prime Implicant if it cannot be combined with another covering to eliminate a variable. 5 Two Solutions EH solution is equally valid. F(,,,) = + acd + bd Essential PIs 6 Non-Essential PIs F(,,,) = + acd + bcd 3

4 Minimal Solution minimal SOP will consist of prime implicants. minimal SOP equation will have all of the essential prime implicants on the map. y definition, these cover a minterm that may not be covered by some other prime implicant. The minimal SOP equation may or may not include nonessential prime implicants. It will include non-essential prime implicants if there are s remaining that have not been covered by an essential prime implicant. 7 Row F(,,,) x x 2 x 3 x 4 x 5 x on t ares on t ares are labeled as X s in truth table. an treat X s as either s or s F() Recognize numbers: 2,3,6 Non numbers are don t cares because they will never be applied as inputs! F(..) 8 4

5 on t ares treated as s or s X X X X X X Treat X s as s to make larger groupings. ll X s do not have to be covered. F(,,,) = c + c 9 Minimizing s Grouping s produces an equation for F. F(,,) = F(,,) = c 5

6 Minimize s, then omplement to get POS X X X X X X F (,,,) = + bd Take inverse of both sides F(,,,) = ( + bd) = c (bd) = c (+) Minimizing zeros, then applying inverse to both sides is a way to get to minimum POS form K-Map example esign Example: Two it omparator omparator F F 2 F 3 lock iagram = < > Truth Table F F 2 F 3 4-Variable K-map for each of the 3 output functions 2 6

7 K-Map example esign Example: Two it omparator K-map for F K-map for F 2 K-map for F 3 F = F2 = F3 = 3 6- Variable K-Maps EF = djacencies EF = EF = EF = f(,,,,e,f) = Σm(2,8,,8,24, 26,34,37,42,45,5, 53,58,6) = e F + a d E f + c F EF = EF = EF = EF = 4 7

8 EF = EF = Six-Variable K-Map F= d + bf + ace EF = EF = 5 More K-Map Method Examples, 3 Variables F(,,) = Σm(,4,5,7) F = F' simply replace 's with 's and vice versa F(,,) = Σm(,2,3,6) F = 6 8

9 K-map Method Examples: 4 variables F(,,,) = Σm(,2,3,5,6,7,8,,,4,5) F = 7 K-map Example: on't ares on't ares can be treated as 's or 's if it is advantageous to do so X X X minterms on t cares F(,,,) = Σm(,3,5,7,9) + Σd(6,2,3) without don't cares F = with don't cares F = 8 9

10 Variable-Entered Karnaugh Maps (VEM) K-maps are cumbersome for 5 or more variables The variable entered map method allows 8 to 6 variable maps to be represented as 3 to 5 variable maps Needed because typical oolean design problem involves 8 or more oolean variables onventional logic minimization: Time consuming Error-prone VEM Key idea: Represent values of function in terms of its variables (called mapentered variables) within Karnaugh map framework Group like variables in Karnaugh map cells 9 VEM example 5-variable karnaugh map,,, go, wait ells can now contain variables, as well as,,or X. on t care go go wait X wait F Minimisation approach Map all s onvert s to X s (i.e. don t cares) Map SIMILR components 2

11 Phase Map s with any don t cares VEM example go go wait X wait F f = (c + ab) +. 2 Phase 2 VEM example onvert s to X s and map like entries go go X wait X X wait F f = ( c + a b ) +. ( go + b go + a wait) 22

12 VEM example 2 5-variable karnaugh map,,, P, Q Q + p p + P p + P = X Q Q + p F X Q f = ( + ) +.. F 23 5-variable karnaugh map,,, P, Q VEM example 2 XX XX Q + p XX X Q F f = ( + ) + bq + p 24 2

13 Example using VEM Example function F(a,b,c) = + bc + a + ac rbitrarily choose as map entered variable or choose least used variable Insert map entries as follows F(a,b,c) = No minterm (i.e ) X (don t care) ondition --- = = = or --- Map entry c (c + ) or X 25 3

Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal

More information

Logic and Computer Design Fundamentals. Chapter 2 Combinational Logic Circuits. Part 2 Circuit Optimization

Logic and Computer Design Fundamentals. Chapter 2 Combinational Logic Circuits. Part 2 Circuit Optimization Logic and omputer Design Fundamentals hapter 2 ombinational Logic ircuits Part 2 ircuit Optimization harles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode)

More information

UNIT 5 KARNAUGH MAPS Spring 2011

UNIT 5 KARNAUGH MAPS Spring 2011 UNIT 5 KRNUGH MPS Spring 2 Karnaugh Maps 2 Contents Minimum forms of switching functions Two- and three-variable Four-variable Determination of minimum expressions using essential prime implicants Five-variable

More information

Advanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011

Advanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011 Problem 2-1 Recall that a minterm is a cube in which every variable appears. A Boolean expression in SOP form is canonical if every cube in the expression has a unique representation in which all of the

More information

The Karnaugh Map COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals

The Karnaugh Map COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals The Karnaugh Map COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Boolean Function Minimization The Karnaugh Map (K-Map) Two, Three,

More information

ﻮﻧﺭﺎﮐ ﺔﺸﻘﻧ ﺎﺑ ﻱﺯﺎﺳ ﻪﻨﻴﻬﺑ

ﻮﻧﺭﺎﮐ ﺔﺸﻘﻧ ﺎﺑ ﻱﺯﺎﺳ ﻪﻨﻴﻬﺑ بهينه سازي با نقشة کارنو Karnaugh Map Karnaugh Map Method of graphically representing the truth table that helps visualize adjacencies 2-variable K-map 3-variable K-map 2 3 2 3 6 7 4 5 D 3 2 4 5 7 6 2

More information

Lecture 7: Karnaugh Map, Don t Cares

Lecture 7: Karnaugh Map, Don t Cares EE210: Switching Systems Lecture 7: Karnaugh Map, Don t Cares Prof. YingLi Tian Feb. 28, 2019 Department of Electrical Engineering The City College of New York The City University of New York (CUNY) 1

More information

14:332:231 DIGITAL LOGIC DESIGN

14:332:231 DIGITAL LOGIC DESIGN :: DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall Lecture #: Combinational Circuit Synthesis II hat if we have input variables? V = V = of Example with variables

More information

Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Charles Kime & Thomas Kaminski 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active

More information

DIGITAL ELECTRONICS & it0203 Semester 3

DIGITAL ELECTRONICS & it0203 Semester 3 DIGITAL ELECTRONICS & it0203 Semester 3 P.Rajasekar & C.M.T.Karthigeyan Asst.Professor SRM University, Kattankulathur School of Computing, Department of IT 8/22/2011 1 Disclaimer The contents of the slides

More information

Simplification of Boolean Functions. Dept. of CSE, IEM, Kolkata

Simplification of Boolean Functions. Dept. of CSE, IEM, Kolkata Simplification of Boolean Functions Dept. of CSE, IEM, Kolkata 1 Simplification of Boolean Functions: An implementation of a Boolean Function requires the use of logic gates. A smaller number of gates,

More information

CHAPTER 5 KARNAUGH MAPS

CHAPTER 5 KARNAUGH MAPS CHAPTER 5 1/36 KARNAUGH MAPS This chapter in the book includes: Objectives Study Guide 5.1 Minimum Forms of Switching Functions 5.2 Two- and Three-Variable Karnaugh Maps 5.3 Four-Variable Karnaugh Maps

More information

Karnaugh Maps ف ر آ ا د : ا ا ب ا م آ ه ا ن ر ا

Karnaugh Maps ف ر آ ا د : ا ا ب ا م آ ه ا ن ر ا Karnaugh Maps مخطط آارنوف اعداد:محمد اسماعيل آلية علوم الحاسوب جامعة امدرمان الاهلية الاهداء الي آل من يسلك طريق العلم والمعرفة في هذا المجال Venn Diagrams Venn diagram to represent the space of minterms.

More information

Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps

Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps EE210: Switching Systems Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps Prof. YingLi Tian Feb. 21/26, 2019 Department of Electrical Engineering The City College of New York

More information

ELEC Digital Logic Circuits Fall 2015 Logic Minimization (Chapter 3)

ELEC Digital Logic Circuits Fall 2015 Logic Minimization (Chapter 3) ELE 2200-002 igital Logic ircuits Fall 205 Logic Minimization (hapter 3) Vishwani. grawal James J. anaher Professor epartment of Electrical and omputer Engineering uburn University, uburn, L 36849 http://www.eng.auburn.edu/~vagrawal

More information

Optimizations and Tradeoffs. Combinational Logic Optimization

Optimizations and Tradeoffs. Combinational Logic Optimization Optimizations and Tradeoffs Combinational Logic Optimization Optimization & Tradeoffs Up to this point, we haven t really considered how to optimize our designs. Optimization is the process of transforming

More information

for Digital Systems Simplification of logic functions Tajana Simunic Rosing Sources: TSR, Katz, Boriello & Vahid

for Digital Systems Simplification of logic functions Tajana Simunic Rosing Sources: TSR, Katz, Boriello & Vahid SE140: omponents and Design Techniques for Digital Systems Simplification of logic functions Tajana Simunic Rosing 1 What we covered thus far: Number representations Where we are now inary, Octal, Hex,

More information

ELEC Digital Logic Circuits Fall 2014 Logic Minimization (Chapter 3)

ELEC Digital Logic Circuits Fall 2014 Logic Minimization (Chapter 3) ELE 2200-002 Digital Logic ircuits Fall 204 Logic Minimization (hapter 3) Vishwani D. grawal James J. Danaher Professor Department of Electrical and omputer Engineering uburn University, uburn, L 36849

More information

COM111 Introduction to Computer Engineering (Fall ) NOTES 6 -- page 1 of 12

COM111 Introduction to Computer Engineering (Fall ) NOTES 6 -- page 1 of 12 COM111 Introduction to Computer Engineering (Fall 2006-2007) NOTES 6 -- page 1 of 12 Karnaugh Maps In this lecture, we will discuss Karnaugh maps (K-maps) more formally than last time and discuss a more

More information

ELC224C. Karnaugh Maps

ELC224C. Karnaugh Maps KARNAUGH MAPS Function Simplification Algebraic Simplification Half Adder Introduction to K-maps How to use K-maps Converting to Minterms Form Prime Implicants and Essential Prime Implicants Example on

More information

Minimization techniques

Minimization techniques Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NSIK - 4 Minimization techniques By Prof. nand N. Gharu ssistant Professor Computer Department Combinational Logic Circuits Introduction Standard representation

More information

Boolean cubes EECS150. Mapping truth tables onto cubes. Simplification. The Uniting Theorem. Three variable example

Boolean cubes EECS150. Mapping truth tables onto cubes. Simplification. The Uniting Theorem. Three variable example EES5 Section 5 Simplification and State Minimization Fall 2 -cube X oolean cubes Visual technique for indentifying when the uniting theorem can be applied n input variables = n-dimensional "cube" Y 2-cube

More information

L4: Karnaugh diagrams, two-, and multi-level minimization. Elena Dubrova KTH / ICT / ES

L4: Karnaugh diagrams, two-, and multi-level minimization. Elena Dubrova KTH / ICT / ES L4: Karnaugh diagrams, two-, and multi-level minimization Elena Dubrova KTH / ICT / ES dubrova@kth.se Combinatorial system a(t) not(a(t)) A combinatorial system has no memory - its output depends therefore

More information

Gate-Level Minimization

Gate-Level Minimization Gate-Level Minimization Dr. Bassem A. Abdullah Computer and Systems Department Lectures Prepared by Dr.Mona Safar, Edited and Lectured by Dr.Bassem A. Abdullah Outline 1. The Map Method 2. Four-variable

More information

This form sometimes used in logic circuit, example:

This form sometimes used in logic circuit, example: Objectives: 1. Deriving of logical expression form truth tables. 2. Logical expression simplification methods: a. Algebraic manipulation. b. Karnaugh map (k-map). 1. Deriving of logical expression from

More information

Midterm1 Review. Jan 24 Armita

Midterm1 Review. Jan 24 Armita Midterm1 Review Jan 24 Armita Outline Boolean Algebra Axioms closure, Identity elements, complements, commutativity, distributivity theorems Associativity, Duality, De Morgan, Consensus theorem Shannon

More information

Unit 2 Session - 6 Combinational Logic Circuits

Unit 2 Session - 6 Combinational Logic Circuits Objectives Unit 2 Session - 6 Combinational Logic Circuits Draw 3- variable and 4- variable Karnaugh maps and use them to simplify Boolean expressions Understand don t Care Conditions Use the Product-of-Sums

More information

CSE 140: Components and Design Techniques for Digital Systems

CSE 140: Components and Design Techniques for Digital Systems Lecture 4: Four Input K-Maps CSE 4: Components and Design Techniques for Digital Systems CK Cheng Dept. of Computer Science and Engineering University of California, San Diego Outlines Boolean Algebra

More information

CHAPTER III BOOLEAN ALGEBRA

CHAPTER III BOOLEAN ALGEBRA CHAPTER III- CHAPTER III CHAPTER III R.M. Dansereau; v.. CHAPTER III-2 BOOLEAN VALUES INTRODUCTION BOOLEAN VALUES Boolean algebra is a form of algebra that deals with single digit binary values and variables.

More information

Lecture 4: Four Input K-Maps

Lecture 4: Four Input K-Maps Lecture 4: Four Input K-Maps CSE 4: Components and Design Techniques for Digital Systems Fall 24 CK Cheng Dept. of Computer Science and Engineering University of California, San Diego Outlines Boolean

More information

Unit 6. Quine-McClusky Method. Unit 6 1

Unit 6. Quine-McClusky Method. Unit 6 1 Unit 6 Quine-McClusky Method Unit 6 1 Outline Determination of prime implicants The prime implicant chart Petrick s method Simplification of incompletely specified functions Unit 6 2 Overview (1/2) A systematic

More information

Karnaugh Map & Boolean Expression Simplification

Karnaugh Map & Boolean Expression Simplification Karnaugh Map & Boolean Expression Simplification Mapping a Standard POS Expression For a Standard POS expression, a 0 is placed in the cell corresponding to the product term (maxterm) present in the expression.

More information

Simplifying Logic Circuits with Karnaugh Maps

Simplifying Logic Circuits with Karnaugh Maps Simplifying Logic Circuits with Karnaugh Maps The circuit at the top right is the logic equivalent of the Boolean expression: f = abc + abc + abc Now, as we have seen, this expression can be simplified

More information

SIMPLIFICATION OF BOOLEAN ALGEBRA. Presented By: Ms. Poonam Anand

SIMPLIFICATION OF BOOLEAN ALGEBRA. Presented By: Ms. Poonam Anand SIMPLIFITION OF OOLEN LGER Presented y: Ms. Poonam nand SIMPLIFITION USING OOLEN LGER simplified oolean expression uses the fewest gates possible to implement a given expression. ()() SIMPLIFITION USING

More information

3. PRINCIPLES OF COMBINATIONAL LOGIC

3. PRINCIPLES OF COMBINATIONAL LOGIC Principle of ombinational Logic -. PRINIPLES OF OMINTIONL LOGI Objectives. Understand the design & analysis procedure of combinational logic.. Understand the optimization of combinational logic.. efinitions

More information

CHAPTER III BOOLEAN ALGEBRA

CHAPTER III BOOLEAN ALGEBRA CHAPTER III- CHAPTER III CHAPTER III R.M. Dansereau; v.. CHAPTER III-2 BOOLEAN VALUES INTRODUCTION BOOLEAN VALUES Boolean algebra is a form of algebra that deals with single digit binary values and variables.

More information

Combinational Logic (mostly review!)

Combinational Logic (mostly review!) ombinational Logic (mostly review!)! Logic functions, truth tables, and switches " NOT, N, OR, NN, NOR, OR,... " Minimal set! xioms and theorems of oolean algebra " Proofs by re-writing " Proofs by perfect

More information

Karnaugh Maps Objectives

Karnaugh Maps Objectives Karnaugh Maps Objectives For Karnaugh Maps of up to 5 variables Plot a function from algebraic, minterm or maxterm form Obtain minimum Sum of Products and Product of Sums Understand the relationship between

More information

Ex: Boolean expression for majority function F = A'BC + AB'C + ABC ' + ABC.

Ex: Boolean expression for majority function F = A'BC + AB'C + ABC ' + ABC. Boolean Expression Forms: Sum-of-products (SOP) Write an AND term for each input combination that produces a 1 output. Write the input variable if its value is 1; write its complement otherwise. OR the

More information

Chapter 4 Optimized Implementation of Logic Functions

Chapter 4 Optimized Implementation of Logic Functions Chapter 4 Optimized Implementation of Logic Functions Logic Minimization Karnaugh Maps Systematic Approach for Logic Minimization Minimization of Incompletely Specified Functions Tabular Method for Minimization

More information

Digital Logic Design. Combinational Logic

Digital Logic Design. Combinational Logic Digital Logic Design Combinational Logic Minterms A product term is a term where literals are ANDed. Example: x y, xz, xyz, A minterm is a product term in which all variables appear exactly once, in normal

More information

Chapter 2. Introduction. Chapter 2 :: Topics. Circuits. Nodes. Circuit elements. Introduction

Chapter 2. Introduction. Chapter 2 :: Topics. Circuits. Nodes. Circuit elements. Introduction hapter 2 Introduction igital esign and omputer rchitecture, 2 nd Edition avid Money Harris and Sarah L. Harris logic circuit is composed of: Inputs Outputs Functional specification Timing specification

More information

211: Computer Architecture Summer 2016

211: Computer Architecture Summer 2016 211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Review: cache hit rate - Project3 - Digital Logic: - truth table => SOP - simplification: Boolean

More information

CSE 140 Midterm I - Solution

CSE 140 Midterm I - Solution CSE 140 Midterm I - Solution 1. Answer the following questions given the logic circuit below. (15 points) a. (5 points) How many CMOS transistors does the given (unsimplified) circuit have. b. (6 points)

More information

Spiral 1 / Unit 5. Karnaugh Maps

Spiral 1 / Unit 5. Karnaugh Maps -. Spiral / Unit Karnaugh Maps -. Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve

More information

Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps

Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps -. -. Spiral / Unit Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve

More information

Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University

Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University Original Source: Aby K George, ECE Department, Wayne State University Contents The Map method Two variable

More information

Principles of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents

Principles of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents B-1 Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix B: Reduction of Digital Logic B-2 Chapter Contents B.1 Reduction of Combinational Logic and Sequential Logic B.2 Reduction

More information

Karnaugh Maps (K-Maps)

Karnaugh Maps (K-Maps) Karnaugh Maps (K-Maps) Boolean expressions can be minimized by combining terms P + P = P K-maps minimize equations graphically Put terms to combine close to one another B C C B B C BC BC BC BC BC BC BC

More information

Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps

Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps -. -. Spiral / Unit Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve

More information

Review for B33DV2-Digital Design. Digital Design

Review for B33DV2-Digital Design. Digital Design Review for B33DV2 The Elements of Modern Behaviours Design Representations Blocks Waveforms Gates Truth Tables Boolean Algebra Switches Rapid Prototyping Technologies Circuit Technologies TTL MOS Simulation

More information

Working with Combinational Logic. Design example: 2x2-bit multiplier

Working with Combinational Logic. Design example: 2x2-bit multiplier Working with ombinational Logic Simplification two-level simplification exploiting don t cares algorithm for simplification Logic realization two-level logic and canonical forms realized with NNs and NORs

More information

9.1. Unit 9. Implementing Combinational Functions with Karnaugh Maps or Memories

9.1. Unit 9. Implementing Combinational Functions with Karnaugh Maps or Memories . Unit Implementing Combinational Functions with Karnaugh Maps or Memories . Outcomes I can use Karnaugh maps to synthesize combinational functions with several outputs I can determine the appropriate

More information

Review. EECS Components and Design Techniques for Digital Systems. Lec 06 Minimizing Boolean Logic 9/ Review: Canonical Forms

Review. EECS Components and Design Techniques for Digital Systems. Lec 06 Minimizing Boolean Logic 9/ Review: Canonical Forms Review EECS 150 - Components and Design Techniques for Digital Systems Lec 06 Minimizing Boolean Logic 9/16-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley

More information

MODULAR CIRCUITS CHAPTER 7

MODULAR CIRCUITS CHAPTER 7 CHAPTER 7 MODULAR CIRCUITS A modular circuit is a digital circuit that performs a specific function or has certain usage. The modular circuits to be introduced in this chapter are decoders, encoders, multiplexers,

More information

CS221: Digital Design. Dr. A. Sahu. Indian Institute of Technology Guwahati

CS221: Digital Design. Dr. A. Sahu. Indian Institute of Technology Guwahati CS221: Digital Design QMLogicMinimization Minimization Dr. A. Sahu DeptofComp.Sc.&Engg. Indian Institute of Technology Guwahati 1 Outline Quine McCluskey(QM) Logic Minimization Examples Writing C/C++ program

More information

Computer Organization I. Lecture 13: Design of Combinational Logic Circuits

Computer Organization I. Lecture 13: Design of Combinational Logic Circuits Computer Organization I Lecture 13: Design of Combinational Logic Circuits Overview The optimization of multiple-level circuits Mapping Technology Verification Objectives To know how to optimize the multiple-level

More information

Simlification of Switching Functions

Simlification of Switching Functions Simlification of Switching unctions ( ) = ( 789 5) Quine-Mc luskey Original nonminimized oolean function m i m i m n m i [] m m m m m 4 m 5 m 6 m 7 m 8 m 9 m m m m m 4 m 5 m m m 7 m 8 m 9 m m 5 The number

More information

Logical Design of Digital Systems

Logical Design of Digital Systems Lecture 4 Table of Content 1. Combinational circuit design 2. Elementary combinatorial circuits for data transmission 3. Memory structures 4. Programmable logic devices 5. Algorithmic minimization approaches

More information

Ch 2. Combinational Logic. II - Combinational Logic Contemporary Logic Design 1

Ch 2. Combinational Logic. II - Combinational Logic Contemporary Logic Design 1 Ch 2. Combinational Logic II - Combinational Logic Contemporary Logic Design 1 Combinational logic Define The kind of digital system whose output behavior depends only on the current inputs memoryless:

More information

Lecture 2. Notes. Notes. Notes. Boolean algebra and optimizing logic functions. BTF Electronics Fundamentals August 2014

Lecture 2. Notes. Notes. Notes. Boolean algebra and optimizing logic functions. BTF Electronics Fundamentals August 2014 Lecture 2 Electronics ndreas Electronics oolean algebra and optimizing logic functions TF322 - Electronics Fundamentals ugust 24 Exercise ndreas ern University of pplied Sciences Rev. 946f32 2. of oolean

More information

Chapter 2 : Boolean Algebra and Logic Gates

Chapter 2 : Boolean Algebra and Logic Gates Chapter 2 : Boolean Algebra and Logic Gates By Electrical Engineering Department College of Engineering King Saud University 1431-1432 2.1. Basic Definitions 2.2. Basic Theorems and Properties of Boolean

More information

Learning Objectives. Boolean Algebra. In this chapter you will learn about:

Learning Objectives. Boolean Algebra. In this chapter you will learn about: Ref. Page Slide /78 Learning Objectives In this chapter you will learn about: oolean algebra Fundamental concepts and basic laws of oolean algebra oolean function and minimization Logic gates Logic circuits

More information

Show that the dual of the exclusive-or is equal to its compliment. 7

Show that the dual of the exclusive-or is equal to its compliment. 7 Darshan Institute of ngineering and Technology, Rajkot, Subject: Digital lectronics (2300) GTU Question ank Unit Group Questions Do as directed : I. Given that (6)0 = (00)x, find the value of x. II. dd

More information

Digital Logic & Computer Design CS Professor Dan Moldovan Spring Copyright 2007 Elsevier 2-<101>

Digital Logic & Computer Design CS Professor Dan Moldovan Spring Copyright 2007 Elsevier 2-<101> Digital Logic & Computer Design CS 434 Professor Dan Moldovan Spring 2 Copyright 27 Elsevier 2- Chapter 2 :: Combinational Logic Design Digital Design and Computer Architecture David Money Harris and

More information

WEEK 3.1 MORE ON KARNAUGH MAPS

WEEK 3.1 MORE ON KARNAUGH MAPS WEEK 3. MORE ON KARNAUGH MAPS Don t Cares Sometimes, we might have inputs and it doesn t matter what the output is; i.e., we don t care what the output is. These situations are called don t cares. Rather

More information

Why digital? Overview. Number Systems. Binary to Decimal conversion

Why digital? Overview. Number Systems. Binary to Decimal conversion Why digital? Overview It has the following advantages over analog. It can be processed and transmitted efficiently and reliably. It can be stored and retrieved with greater accuracy. Noise level does not

More information

Digital Logic & Computer Design CS Professor Dan Moldovan Spring 2010

Digital Logic & Computer Design CS Professor Dan Moldovan Spring 2010 Digital Logic & Computer Design CS 434 Professor Dan Moldovan Spring 2 Copyright 27 Elsevier 2- Chapter 2 :: Combinational Logic Design Digital Design and Computer rchitecture David Money Harris and

More information

ENG2410 Digital Design Combinational Logic Circuits

ENG2410 Digital Design Combinational Logic Circuits ENG240 Digital Design Combinational Logic Circuits Fall 207 S. Areibi School of Engineering University of Guelph Binary variables Binary Logic Can be 0 or (T or F, low or high) Variables named with single

More information

Boolean Algebra and Logic Simplification

Boolean Algebra and Logic Simplification S302 Digital Logic Design Boolean Algebra and Logic Simplification Boolean Analysis of Logic ircuits, evaluating of Boolean expressions, representing the operation of Logic circuits and Boolean expressions

More information

Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions

Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions EE210: Switching Systems Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions Prof. YingLi Tian Feb. 15, 2018 Department of Electrical Engineering The City College of New York The

More information

UNIT 4 MINTERM AND MAXTERM EXPANSIONS

UNIT 4 MINTERM AND MAXTERM EXPANSIONS UNIT 4 MINTERM AND MAXTERM EXPANSIONS Spring 2 Minterm and Maxterm Expansions 2 Contents Conversion of English sentences to Boolean equations Combinational logic design using a truth table Minterm and

More information

Possible logic functions of two variables

Possible logic functions of two variables ombinational logic asic logic oolean algebra, proofs by re-writing, proofs by perfect induction logic functions, truth tables, and switches NOT, ND, OR, NND, NOR, OR,..., minimal set Logic realization

More information

CHAPTER 7. Solutions for Exercises

CHAPTER 7. Solutions for Exercises CHAPTER 7 Solutions for Exercises E7.1 (a) For the whole part we have: Quotient Remainders 23/2 11 1 11/2 5 1 5/2 2 1 2/2 1 0 1/2 0 1 Reading the remainders in reverse order we obtain: 23 10 = 10111 2

More information

Number System conversions

Number System conversions Number System conversions Number Systems The system used to count discrete units is called number system. There are four systems of arithmetic which are often used in digital electronics. Decimal Number

More information

Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 1 Gate Circuits and Boolean Equations Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active

More information

Minimierung. Wintersemester 2018/19. Folien basierend auf Material von F. Vahid und S. Werner Vorlesender: Dr. Ing.

Minimierung. Wintersemester 2018/19. Folien basierend auf Material von F. Vahid und S. Werner Vorlesender: Dr. Ing. Minimierung Grundlagen der technischen Informatik Wintersemester 28/9 Folien basierend auf Material von F. Vahid und S. Werner Wintersemester 28/9 Review - Boolean Algebra Properties Commutative (Kommutativgesetz)

More information

MC9211 Computer Organization

MC9211 Computer Organization MC92 Computer Organization Unit : Digital Fundamentals Lesson2 : Boolean Algebra and Simplification (KSB) (MCA) (29-2/ODD) (29 - / A&B) Coverage Lesson2 Introduces the basic postulates of Boolean Algebra

More information

Chap 2. Combinational Logic Circuits

Chap 2. Combinational Logic Circuits Overview 2 Chap 2. Combinational Logic Circuits Spring 24 Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard Forms Part 2 Circuit Optimization Two-Level Optimization

More information

L2: Combinational Logic Design (Construction and Boolean Algebra)

L2: Combinational Logic Design (Construction and Boolean Algebra) L2: Combinational Logic Design (Construction and oolean lgebra) cknowledgements: Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University of

More information

Textbook: Digital Design, 3 rd. Edition M. Morris Mano

Textbook: Digital Design, 3 rd. Edition M. Morris Mano : 25/5/ P-/70 Tetbook: Digital Design, 3 rd. Edition M. Morris Mano Prentice-Hall, Inc. : INSTRUCTOR : CHING-LUNG SU E-mail: kevinsu@yuntech.edu.tw Chapter 3 25/5/ P-2/70 Chapter 3 Gate-Level Minimization

More information

CHAPTER 7. Exercises 17/ / /2 2 0

CHAPTER 7. Exercises 17/ / /2 2 0 CHAPTER 7 Exercises E7. (a) For the whole part, we have: Quotient Remainders 23/2 /2 5 5/2 2 2/2 0 /2 0 Reading the remainders in reverse order, we obtain: 23 0 = 0 2 For the fractional part we have 2

More information

ECE/Comp Sci 352 Digital System Fundamentals Quiz # 1 Solutions

ECE/Comp Sci 352 Digital System Fundamentals Quiz # 1 Solutions Last (Family) Name: KIME First (Given) Name: Student I: epartment of Electrical and omputer Engineering University of Wisconsin - Madison EE/omp Sci 352 igital System Fundamentals Quiz # Solutions October

More information

Logic Design I (17.341) Fall Lecture Outline

Logic Design I (17.341) Fall Lecture Outline Logic Design I (17.341) Fall 2011 Lecture Outline Class # 06 October 24, 2011 Dohn Bowden 1 Today s Lecture Administrative Main Logic Topic Homework 2 Course Admin 3 Administrative Admin for tonight Syllabus

More information

Chapter 5. Karnaugh Map and Minimization Procedures

Chapter 5. Karnaugh Map and Minimization Procedures hapter 5 Karnaugh Map and Minimization Procedures Lesson 1 KARNAUGH MAP h05l1-"digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline Three variable Karnaugh map Four variable Karnaugh

More information

Logic Design Combinational Circuits. Digital Computer Design

Logic Design Combinational Circuits. Digital Computer Design Logic Design Combinational Circuits Digital Computer Design Topics Combinational Logic Karnaugh Maps Combinational uilding locks Timing 2 Logic Circuit logic circuit is composed of: Inputs Outputs Functional

More information

CPE100: Digital Logic Design I

CPE100: Digital Logic Design I Chapter 2 Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu http://www.ee.unlv.edu/~b1morris/cpe100/ CPE100: Digital Logic Design I Section 1004: Dr. Morris Combinational Logic Design Chapter

More information

Working with combinational logic

Working with combinational logic Working with combinational logic Simplification two-level simplification exploiting don t cares algorithm for simplification Logic realization two-level logic and canonical forms realized with NNs and

More information

Reduction of Logic Equations using Karnaugh Maps

Reduction of Logic Equations using Karnaugh Maps Reduction of Logic Equations using Karnaugh Maps The design of the voting machine resulted in a final logic equation that was: z = (a*c) + (a*c) + (a*b) + (a*b*c) However, a simple examination of this

More information

Boolean Algebra and Logic Design (Class 2.2 1/24/2013) CSE 2441 Introduction to Digital Logic Spring 2013 Instructor Bill Carroll, Professor of CSE

Boolean Algebra and Logic Design (Class 2.2 1/24/2013) CSE 2441 Introduction to Digital Logic Spring 2013 Instructor Bill Carroll, Professor of CSE Boolean Algebra and Logic Design (Class 2.2 1/24/2013) CSE 2441 Introduction to Digital Logic Spring 2013 Instructor Bill Carroll, Professor of CSE Today s Topics Boolean algebra applications in logic

More information

Combinational Logic Circuits Part II -Theoretical Foundations

Combinational Logic Circuits Part II -Theoretical Foundations Combinational Logic Circuits Part II -Theoretical Foundations Overview Boolean Algebra Basic Logic Operations Basic Identities Basic Principles, Properties, and Theorems Boolean Function and Representations

More information

L2: Combinational Logic Design (Construction and Boolean Algebra)

L2: Combinational Logic Design (Construction and Boolean Algebra) L2: Combinational Logic Design (Construction and oolean lgebra) cknowledgements: Lecture material adapted from Chapter 2 of R. Katz, G. orriello, Contemporary Logic Design (second edition), Pearson Education,

More information

Week-I. Combinational Logic & Circuits

Week-I. Combinational Logic & Circuits Week-I Combinational Logic & Circuits Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other logic operators IC families and

More information

1. Expand each of the following functions into a canonical sum-of-products expression.

1. Expand each of the following functions into a canonical sum-of-products expression. CHAPTER 4 PROLEMS 1. Expand each of the following functions into a canonical sum-of-products expression. (a) F(x, y, z) = xy + y z + x (b) F(w, x, y, z) = x y + wxy + w yz (c) F(A,,C,D) = AC + CD + C D

More information

Chapter 2 Combinational logic

Chapter 2 Combinational logic Chapter 2 Combinational logic Chapter 2 is very easy. I presume you already took discrete mathemtics. The major part of chapter 2 is boolean algebra. II - Combinational Logic Copyright 24, Gaetano Borriello

More information

CS221: Digital Design. Indian Institute of Technology Guwahati

CS221: Digital Design. Indian Institute of Technology Guwahati CS221: Digital Design KMap LogicMinimizationContd.. Minimization Dr. A. Sahu DeptofComp.Sc.&Engg. Indian Institute of Technology Guwahati 1 Outline Karnoughmap simplification 4 variable karnaughmap Don

More information

Digital Fundamentals

Digital Fundamentals Digital Fundamentals Tenth Edition Floyd hapter 5 Modified by Yuttapong Jiraraksopakun Floyd, Digital Fundamentals, 10 th 2008 Pearson Education ENE, KMUTT ed 2009 2009 Pearson Education, Upper Saddle

More information

Goals for Lecture. Binary Logic and Gates (MK 2.1) Binary Variables. Notation Examples. Logical Operations

Goals for Lecture. Binary Logic and Gates (MK 2.1) Binary Variables. Notation Examples. Logical Operations Introduction to Electrical Engineering, II LETURE NOTES #2 Instructor: Email: Telephone: Office: ndrew. Kahng (lecture) abk@ucsd.edu 858-822-4884 office 3802 P&M lass Website: http://vlsicad.ucsd.edu/courses/ece20b/wi04/

More information

Introduction to Karnaugh Maps

Introduction to Karnaugh Maps Introduction to Karnaugh Maps Review So far, you (the students) have been introduced to truth tables, and how to derive a Boolean circuit from them. We will do an example. Consider the truth table for

More information

CMSC 313 Lecture 19 Combinational Logic Components Programmable Logic Arrays Karnaugh Maps

CMSC 313 Lecture 19 Combinational Logic Components Programmable Logic Arrays Karnaugh Maps CMSC 33 Lecture 9 Combinational Logic Components Programmable Logic rrays Karnaugh Maps UMC, CMSC33, Richard Chang Last Time & efore Returned midterm exam Half adders & full adders Ripple

More information