CHAPTER 7. Exercises 17/ / /2 2 0

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1 CHAPTER 7 Exercises E7. (a) For the whole part, we have: Quotient Remainders 23/2 /2 5 5/2 2 2/2 0 /2 0 Reading the remainders in reverse order, we obtain: 23 0 = 0 2 For the fractional part we have = = + 0 Thus we have = Finally, the answer is = 0. 2 (b) For the whole part we have: Quotient Remainders 7/2 8 8/ / /2 0 /2 0 Reading the remainders in reverse order we obtain: 7 0 = For the fractional part we have = = + 0 Thus we have = Finally, the answer is =

2 (c) For the whole part we have: Quotient Remainders 4/ /2 0 /2 0 Reading the remainders in reverse order we obtain: 4 0 = 00 2 For the fractional part, we have = = = = = = Thus we have = Finally, the answer is = E7.2 (a) 0. 2 = = (b) = = E7.3 (a) Using the procedure of Exercise 7., we have 97 0 = Then adding two leading zeros and forming groups of three bits we have = 4 8 Adding a leading zero and forming groups of four bits we obtain = 6 6 (b) Similarly = = = E5 6 E7.4 (a) 72 8 = 00 = 00 2 (b) FA6 6 = = E = = BCD 243

3 E7.6 To represent a distance of 20 inches with a resolution of 0.0 inches, we need 20/0.0 = 2000 code words. The number of code words in a Gray code is 2 L in which L is the length of the code words. Thus we need L =, which produces 2048 code words. E7.7 (a) First we convert to binary 22 0 = = 00 2 Because an eight-bit representation is called for, we append three leading zeros. Thus +22 becomes in two s complement notation. (b) First we convert +30 to binary form 30 0 = = 0 2 Attaching leading zeros to make an eight-bit result we have 30 0 = Then we take the ones complement and add to find the two s complement: one s complement: 0000 add Thus the eight-bit two s complement representation for is E7.8 First we convert 9 0 and -4 0 to eight-bit two s complement form then we add the results Notice that we neglect the carry out of the left-most bit. E7.9 See Tables 7.3 and 7.4 in the book. E7.0 See Table 7.5 in the book. E7. (a) To apply De Morgan s laws to the expression AB + B C first we replace each logic variable by its inverse 244

4 A B + BC then we replace AND operations by OR operations and vice versa (A + B )( B + C ) finally we invert the entire expression so we have D = AB + B C = ( A + B )( B + C ) (b) Following the steps of part (a) we have [F ( G + H ) + FG ] [F ( G + H ) + F G ] [(F + G H )( F + G )] E = [ F ( G + H ) + FG ] = [( F + G H )( F + G )] E7.2 For the AND gate we use De Morgan s laws to write AB = ( A + B ) See Figure 7.2 in the book for the logic diagrams. E7.3 The truth table for the exclusive-or operation is A B A B Focusing on the rows in which the result is, we can write the SOP expression A B = A B + AB The corresponding logic diagram is shown in Figure 7.25a in the book. Focusing on the rows in which the result is 0, we can write the POS expression A B = ( A + B)( A + B ) The corresponding logic diagram is shown in Figure 7.25b in the book. 245

5 E7.4 The truth table is shown in Table 7.7 in the book. Focusing on the rows in which the result is, we can write the SOP expression A = m(3, 6, 7, 8, 9, 2) = F D GR + F DGR + F DGR + FD G R + FD G R + FDG R Focusing on the rows in which the result is 0, we can write the POS expression A = M(0,, 2, 4, 5, 0,, 3, 4, 5) = ( F + D + G + R)( F + D + G + R )( F + D + G + R ) L( F + D + G + R ) E7.5 The Truth table is shown in Table 7.8. E7.6 (a) A B C D (b) A B C D E7.7 See Figure 7.34 in the book. E7.8 See Figure 7.35 in the book. E7.9 Because S is high at t = 0, Q is high and remains so until R becomes high at t = 3. Q remains low until S becomes high at t = 7. Then Q remains high until R becomes high at t =. E7.20 See Table 7.9. E7.2 See Figure 7.49 in the book. Problems P7.*. When noise is added to a digital signal, the logic levels can still be exactly determined, provided that the noise is not too large in amplitude. Usually, noise cannot be completely removed from an analog signal. 2. Component values in digital circuits do not need to be as precise as in analog circuits. 3. Very complex digital logic circuits (containing millions of components) can be economically produced. Analog circuits often call for large 246

6 capacitances and/or precise component values that are impossible to manufacture as large-scale integrated circuits. P7.2 A bit is a binary symbol that can assume values of 0 or. A byte is a word consisting of eight bits. A nibble is a four-bit word. P7.3 In positive logic, the logic value is represented by a higher voltage range than the voltage range for logic 0. The reverse is true for negative logic. P7.4 The noise margins for a logic circuit are defined as NM L = V IL V OL and NM H = V OH V IH in which V IL is the highest input voltage accepted as logic 0, V IH is the lowest input voltage accepted as logic, V OL is the highest logic-0 output voltage, and V OH is the lowest logic- output voltage. Large values for the noise margins are important so noise added to or subtracted from logic signals in the interconnects does not change the operation of the logic circuit. P7.5 In serial transmission, the bits of a word are transmitted one after another over a single pair of wires. In parallel transmission, multiple bits are transmitted simultaneously over a parallel set of wires. P7.6 (a)* (b) 7.75 (c) 0.25 (d) (e) (f)* P7.7 (a) 7 0 = = 0000 BCD (b) = = BCD (c)* = = BCD (d) = = BCD (e) = = BCD 247

7 P7.8 Seven-bit words are needed to express the decimal integers 0 through 00 in binary form (because 2 7 = 28). Ten-bit words are needed to express the decimal integers 0 through 000 in binary form (because 2 0 = 024). Twenty-bit words are needed to express the decimal integers 0 through 0 6 in binary form (because 2 20 = ). P7.9 (a)* = 00.0 (b) = 0000 (c) = P7.0 (a)* BCD BCD = = = BCD (b) BCD BCD = = = BCD P7. (a) 73 0 = = = AD 6 (b) = = = 2B.8 6 (c) = = = 2DF.C 6 (d)* = = = (e) = = = P7.2 (a) 9 = (eight-bit signed two s complement) (b) -9 = 00 (c)* 75 = 0000 (d)* -87 = 0000 (e) -95 = (f) 99 = 0000 P7.3 (a) FA.F 6 = = = (b) 2A. 6 = = = (c) = = = P7.4 (a) =. 2 = FF.E 6 = (b) = = 53.A 6 = (c) = =

8 P7.5 (a) Counting in decimal, 778 follows 777. (b) Counting in octal, 000 follows 777. (c) Counting in hexadecimal, 778 follows 777. P7.6 (a) A 3-bit binary number can represent the decimal integers 0 through 7. (b) A 3-digit octal number can represent the decimal integers 0 through 5. (c) A 3-digit hexadecimal number can represent the decimal integers 0 through P7.7* Write the 3-bit code shown in Figure 7.9. Then, extend the list by writing the 3-bit code in reverse order. Finally, prepend a 0 to each word in top half of the list and prepend a to each word in the bottom half. The resulting four-bit Gray code is: The Gray code is used for coding positions of movable parts. In a Gray code, each code word differs in only one bit from its neighboring code words, so that erroneous position indications are avoided during transitions. P7.8 (a)* FA5.6 6 = (b)* = (c) 3F4.8 6 =

9 (d) = (e) FF.F0 6 = P7.9 (a) * One's Complement Two's Complement (b) (c) (d) (e) P7.20 (a) (b) (c)* (d) (e) P7.2 Overflow and underflow are not possible if the two numbers to be added have opposite signs. If the two numbers to be added have the same sign and the result has the opposite sign, underflow or overflow has occurred. P7.22 A truth table lists all of the combinations of the variables in a logic expression as well as the value of the expression. P7.23* If the variables in a logic expression are replaced by their inverses, the AND operation is replaced by OR, the OR operation is replaced by AND, 250

10 and the entire expression is inverted, the resulting logic expression yields the same values as before the changes. In equation form, we have: ABC = A + B + C ( A + B + C ) = A B C P7.24 AND gate: AB C OR gate: AB C Inverter: A A 0 0 NAND gate: AB C NOR gate: 25

11 AB C Exclusive OR gate: AB C P7.25 One method to prove the validity of a Boolean identity is to list the truth table and show that both sides of the identity give the same result for each combination of logic variables. P7.26 (a) D = ABC + AB A B C D (b)* E = AB + ABC + CD A B C D E

12 (c) Z = WX + ( W + Y ) X Y W Z (d) D = A + AB + C A B C D (e) D = ( A + BC ) A B C D

13 P7.27 (a) (b) (c) F = ( A + B )C F = A + B + ( BC ) F = A B + ( BC ) + D P7.28* A B C ( A + B )(A + C) A + BC P7.29 A B A + B A + AB ( A + B)( A + AB ) Notice that the column for B matches that for ( A + B)( A + AB ). P7.30 A B A + AB A + B

14 P7.3 A B C ( ABC + ABC + AB C + ABC ) P7.32 (a) F = A + BC (b) F = ABC + ABC + ABC (c)* F = ( A + B + C )( A + B + C )( A + B + C ) 255

15 P7.33 (a) ( C + A) D = ( A + B )( C A D ) F = AB + + (b) F = A( B + C ) + D = ( A + BC )D (c) F ABC + A( B + C ) = ( A + B + C = )( A + B C ) (d)* F = ( A + B + C )( A + B + C )( A + B + C ) = A B C + A BC + AB C (e)* F = ABC + AB C + A BC = ( A + B + C )( A + B + C )( A + B + C ) P7.34 NAND gates are said to be sufficient for combinatorial logic because any Boolean expression can be implemented solely with NAND gates. Simila rly, NOR gate s are suffici ent. P7.35 In this circuit, if switch C is closed and if either of the other two switch es is closed, the output is high. Thus, we can write: D = (A + B ) C The truth table is: A B C D P7.36 In this circuit, the output is high only if switch A is open (A low) and if eit her of the other two switches is open. Thus, we can write D = A (C + B) The truth table is: A B C D

16 P7.37 (a) Applying DeMorgan's laws to the output, we have C = A + B = AB Thus, the gate shown is equivalent to a NAND gate. (b) Applying DeMorgan's laws to the output, we have F = D E = D + E Thus, the gate shown is equivalent to a NOR gate. P7.38 In synthesizing a logic expression as a sum of products, we focus on the lines of the truth table for which the result is. A logical product of logic variables and their inverses is written that yields for each of these lines. Then the products are summed. In synthesizing a logic expression as a product of sums, we focus on the lines of the truth table for which the result is 0. A logical sum of logic variables and their inverses is written that yields 0 for each of these lines. Then the sums are combined in an AND gate. P7.39 An example of a decoder is a circuit that uses a BCD input to produce the logic signals needed to drive the elements of a seven-segment display. An other example is the three-to-eight-line decoder that has a three-bit input and eight output lines. The 3-bit input word selects one of the output lines and that output becomes high. P7.40* F = A B C + ABC + ABC + ABC ( 0,2,5, ) = m 7 ( A + B + C )( A + B + C )( A + B + C )( A + B C ) F = + (,3,4, ) = M 6 257

17 P7.4 G = A B C + ABC = m( 0,3) G = ( A + B + C )( A + B + C )( A + B + C )( A + B + C )( A + B + C )( A + B + C ) (,2,4,5,6, ) = M 7 P7.42 H = A B C + A B C + A BC + AB C + AB C + ABC + ABC ( 0,,2,4,5,6, ) = m 7 ( A + B + C ) M( 3) H = = P7.43 I = A BC + ABC + ABC = m (3,6,7 ) I = ( A + B + C )( A + B + C )( A + B + C )( A + B + C )( A + B + C ) = M (0,,2,4,5 ) P7.44 J = A B C + A BC + AB C + ABC + ABC = m (,3,5,6,7 ) J = ( A + B + C )( A + B + C )( A + B + C ) = M (0,2,4 ) P7.45 K = A B C + A B C + ABC + ABC = m (0,,6,7 ) K = ( A + B + C )( A + B + C )( A + B + C )( A + B + C ) = M (2,3,4,5 ) P7.46 Applying DeMorgan's Laws to the output of the circuit, we have AB + CD = AB CD Thus, the circuit is 258

18 P7.47 Applying DeMorgan's Laws to the output of the circuit, we have (A + B )( C + D) = ( A + B) + ( C + D) Thus, the circuit is P7.48 (a) The truth table is: B E F G I (b) I = m( 4,5,8,2, 3) (c) I = M( 0,,2,3,6,7,9,0,,4, 5) (d) I = E F + BF G 259

19 P7.49* The truth table is: A B A B Thus, we can write the product of sums expression and apply DeMorgan s Laws to obtain: A B = AB + AB = The circuit is: ( AB ) ( A B) P7.50 The truth table is: A B A B Thus, we can write the product of sums expression and apply DeMorgan s Laws to obtain: A B = ( A + B)( A + B ) = ( A + B) + ( A + B ) The circuit is: 260

20 P7.5 The truth table (x = don't cares) is: B 8 B 4 B 2 B A B x x 0 x x 0 0 x x 0 x x x x The circuits are: ( ) ( ) A = M,4, 6 B = M 5, 6 26

21 P7.52* (a) S S 2 S T E (b) m(,6) = S S2ST + (c) Circuit diagram: E = SS2ST P7.53* (a) The Karnaugh map is: 262

22 (b) F = BC + A CD (c) Inverting the map, and writing the minimum SOP expression yields F = AC + B C + CD. Then applying DeMorgan's laws gives F = ( A + C )( B + C )( C + D ) P7.54 (a) The Karnaugh map is: (b) D = B C + A BC (c) Inverting the map, and writing the minimum SOP expression yields two possibilities: D = AC + BC + B C and D = AB + BC + B C Then, applying DeMorgan's laws gives the POS expressions: D = ( A + C )( B + C )( B + C ) and D = ( A + B )( B + C )( B + C ) P7.55 (a) The Karnaugh map is: (b) D = A C + AC (c) D = A C + AC D = ( A + C )( A + C ) 263

23 P7.56 (a) The Karnaugh map is: (b) D = AB + BC (c) Inverting the map, and writing the minimum SOP expression yields D = B + A C. Then applying DeMorgan's laws gives D = B( A + C ) = AB + BC which is the same as the expression found in part (b) so the implementation is the same. P7.57 (a) The Karnaugh map is: (b) (c) F = ABD + BCD The circuit is: 264

58* (a) The Karnaugh map is: (b) F = AB + CD (c) The circuit is: (d) Inverting the map, and

24 (d) Inverting the map, and writing the minimum SOP expression yieldsf = A D + B + C D. Then applying DeMorgan's laws gives F = ( A + D) B( C + D ) P7.58* (a) The Karnaugh map is: (b) F = AB + CD (c) The circuit is: (d) Inverting the map, and writing the minimum SOP expression yields F = A C + A D + B C + B D. Then, applying DeMorgan's laws gives F = ( A + C )( A + D)( B + C )( B + D) 265

25 P7.59 (a) The Karnaugh map is: (b) (c) G = ABC + BCD The circuit is: (d) Inverting the map, and writing the minimum SOP expression yields G = A D + B + C. Then, applying DeMorgan's laws gives G = ( A + D) BC P7.60 (a) The Karnaugh map is: (b) H = BC + AD 266

26 (c) The circuit is: (d) Inverting the map, and writing the minimum SOP expression yields H = A B + A C + B D + C D. Then, applying DeMorgan's laws gives H = ( A + B)( A + C )( B + D)( C + D). P7.6 (a) The Karnaugh map is: (b) I = A C + A D (c) The circuit is: (d) Inverting the map, and writing the minimum SOP expression yields I = A + CD. Then, applying DeMorgan's laws gives I = A ( C + D ). 267

27 P7.62 The Karnaugh map (with the decimal equivalent of each word in the upper right hand corner of each square) is: By inspection the minimal SOP expression is: X = B B 8 P7.63 The Karnaugh map (with the decimal equivalent of each word in the upper right hand corner of each square) is: By inspection, the minimal SOP expression is: X = B B + B 8 4 8B2 Inverting the map, and writing the minimum SOP expression yields X = B +. Then, applying DeMorgan's laws gives 8 B2B B X = B ( B + )

28 P7.64 The Karnaugh map (with the hexadecimal equivalent of each word in the upper right hand corner of each square) is: By inspection the minimal SOP expression is: X = B B 4 Inverting the map, and writing the minimum SOP expression yields X = B + B 4. Then, applying DeMorgan's laws gives X = B B. 4 P7.65 The truth table is: S I I 2 O O The Karnaugh maps are: 269

29 The logic circuit is: P7.66 The Karnaugh map for a three-member council is: By inspection, we see that three two-cubes are needed and the minimal SOP expression is X = AB + AC + BC Clearly, the minimal SOP checks to see if at least one group of two members has voted yes. For a five-member council, the Karnaugh map consists of two fourvariable maps, one for A = and one for A =

Notice that six four-cubes are needed to cover the A = part of the map. Think of the A = 0 map as being (over or under) the A = map. Four two cubes are needed to cover the A = 0 part of the map.

30 Notice that six four-cubes are needed to cover the A = part of the map. Think of the A = 0 map as being (over or under) the A = map. Four two cubes are needed to cover the A = 0 part of the map. However each of these cubes can be combined with corresponding cubes in the A = part of the map to form four 4-cubes. The minimum SOP expression is: X = ABC + ABD + ABE + ADE + ACD + ACE + BCD + BCE + BDE + CDE Here the minimal SOP expression checks to see if at least one group of three members has voted yes. P7.67 The Karnaugh map is By inspection, we see that six one cubes are needed. Thus the minimal SOP expression is: X = ABC D + AB CD + AB C D + A BCD + A BC D + A B CD 27

31 P7.68 (a) The truth table for the circuit of Figure P7.68 is A B C D P (b) The Karnaugh map for P is: From the map, we see that no simplification is possible and the minimum SOP is actually the sum of minterms: P = m(, 2, 4, 7, 8,, 3, 4) (c) The parity check can be performed by the same method as used in Figure P7.68, namely to XOR all of the bits. The circuit is: 272

32 P7.69 By inspection, we see that X = A The Karnaugh maps for Y and Z are: Y = A B + AB Z = BC + B C P7.70 By inspection, we see that A = X The Karnaugh maps for B and C are: B = X Y + XY C = X Y Z + X YZ + XY Z + XYZ 273

33 P7.7* (a) F = A + BC + BD (b) G = A + BD + BC (c) H = A + B C + BC D 274

34 (d) I = D P7.72 (a) A = FH (b) B = F G + FH 275

35 (c) C = GH + G H (d) D = I P7.73 (a) W = A + BC + BD 276

36 (b) X = B C + B D + BC D (c) Y = CD + C D (d) Z = D 277

37 P7.74 (a) A = WX + WZ (b) B = X Y + XYZ + WYZ (c) C = Y Z + YZ 278

(d) D = Z P7.75 P7.76 See Figure 7.39 in the text. P7.77 See Figure 7.44 in the text. P7.78 Asynchronous inputs are recognized independently of the clock signal.

79 In edge triggering, the input values present immediately prior to a transition of the clock signal are

38 (d) D = Z P7.75 P7.76 See Figure 7.39 in the text. P7.77 See Figure 7.44 in the text. P7.78 Asynchronous inputs are recognized independently of the clock signal. Synchronous inputs are recognized only if the clock is high. P7.79 In edge triggering, the input values present immediately prior to a transition of the clock signal are recognized. Input values (and changes in input values) at other times are ignored. P7.80 See Figure 7.47 in the text. 279

39 P7.8* The successive states are: Q 0 Q Q (repeats) Thus, the register returns to the initial state after seven shifts. P7.82 (a) With an OR gate, we have: Q 0 Q Q After the register reaches the state, it remains in that state and never returns to the starting state. (b) With an AND gate, we have: Q 0 Q Q After the register reaches the 000 state, it remains in that state and never returns to the starting state. 280

40 P7.83 The period of the Q 0 waveform is double that of V IN. Similarly, the period ofq is twice that of Q 0. Thus, flip flops connected in this manner divide the frequency of an input signal by two and by four. P7.84 Q becomes high at t = 7 and quickly resets all four flip flops. 3 28

41 P7.85* Q J K D memory reset set 0 0 toggle 0 memory 0 0 reset 0 0 set 0 toggle 0 D = QJ K + QJK + QJ K + QJ K ( K + K ) + QK ( J J ) = Q J + = Q J + QK P

42 P7.87 (a) The logic diagram for the counter is: (b) The truth table for the encoder is: Q 3 Q 2 Q D D 2 D 3 D 4 D 5 D 6 D x x x x x x x x x x x x x x The Karnaugh maps are: 283

43 From the maps we can write: D D = Q + D D = = 7 2 Q3 2 = 6 Q3 4 Q The logic diagram is: D = and D 3 = D5 = Q2Q 3 P7.88 (a) There are four diodes and to make one revolution in two seconds each diode must be on for 0.5 s. Thus, the frequency of the clock is 2 Hz. (b) The modulo-4 counter is: 284

44 (c) The truth table is S Q 2 Q D D 2 D 3 D The minimimal SOP expressions are: D = Q Q S Q Q S QQ 2 D2 = QQ 2 D = = QQ S QQ S D

CHAPTER 7. Solutions for Exercises

CHAPTER 7. Solutions for Exercises CHAPTER 7 Solutions for Exercises E7.1 (a) For the whole part we have: Quotient Remainders 23/2 11 1 11/2 5 1 5/2 2 1 2/2 1 0 1/2 0 1 Reading the remainders in reverse order we obtain: 23 10 = 10111 2