Simlification of Switching Functions
|
|
- Olivia Phillips
- 5 years ago
- Views:
Transcription
1 Simlification of Switching unctions ( ) = ( 789 5) Quine-Mc luskey Original nonminimized oolean function m i m i m n m i [] m m m m m 4 m 5 m 6 m 7 m 8 m 9 m m m m m 4 m 5 m m m 7 m 8 m 9 m m 5 The number of 's 4 m m m m 8 m 9 m m 7 m 5
2 Simlification of Switching unctions Quine-Mc luskey n 4 m i m m m m 8 m 9 m m 7 m 5 Prime implicants (8) (89) (75) [] m m m m 7 m 8 m 9 m m 5 Essential prime implicants m i m j m m m m m 8 m 9 m m m m m 8 m m m 8 m m 8 m m 9 m m 9 m m 8 m m m m m 8 m 9 m 8 m m m 7 m 5 (75) overing Table ll minterms of the function must be covered ( ) = + + m i m j m k m l (89) (8) (75) (89) (8) m 4 m m m m m 5 7 m6 m m m 5 m4 m 8 m9 m m (89) (8)
3 Simlification of Switching unctions ( ) m( 56 7 ) d( ) = + Quine-Mc luskey ( simplification with don't care terms) d d d d mi () () () (5) (6) () () (7) () (mimj) () () (6) () (7) () (57) (67) () (mimj) (67) () (67) () prime implicants (67) () () (57) 5 6 overing Table 7 ( ) = + + +
4 Simlification of Switching unctions Quine-Mc luskey ( ) m( 56 7 ) d( ) = + We skip these ( simplification without don't care terms) mi () (5) (6) () (7) (mimj) (57) (67) prime implicants () () (57) (67) 5 6 overing Table 7 ( ) =
5 Simlification of Switching unctions ecause of propagation delay of gate the minimum SOP or POS epression is often modified to avoid undesirable events hazards. Propagation delay of gate depends on a local loading effects. t L N inputs gate t L t + t gate t + t gate wire wire N inputs Total signal traveling time from gate input to the net gate input includes wiring delay and propagation delay of the first gate. 5
6 Simlification of Switching unctions Two types of hazards Static ynamic Static -hazard Static -hazard ynamic hazards Third type (Essential Hazards) 6
7 Simlification of Switching unctions t = t t = = + t = t t = t = + Static hazard Static hazard Simple eamples of static hazard 7
8 Simlification of Switching unctions ssumption: Only one variable change value in each time. { } { } llowed transition { } { } { } { } Not allowed transition { } { } { } { } 8
9 Simlification of Switching unctions undamental Mode Only one input signal change at a time and only when the circuit is in the stable state. verage switching time of oolean variables > propagation delay of oolean function and individual gates. (>>) ombinational logic can be used as an eitation functions in (asynchronous) sequential circuits. (If it satisfied five requirements for proper operation : John. Wakerly page 68) 9
10 Simlification of Switching unctions ( ) = + + = m t f f f f ( ) = = m SOP f f ( f ) t ( f ) t > Simulated timing for transition : ()= to. f f Truth table
11 Simlification of Switching unctions SOP Static hazard can be prevented by adding a third product term which covers minterms: = and f f ( f ) t ( f ) t > Product term f covers transition to f f f f f In general with arbitrary functions : ( f ) > t ( f ) or t ( f ) t ( f ) t < The direction of transition during glitch generation depends on timing. f f Truth table f
12 Simlification of Switching unctions POS Eample (four variables: ) M i f f f f ( ) = M ( ) m m m m m 4 m m m 8 m5 m 7 m6 m 5 m9 m m ( ) = ( + )( + )( + )( + ) + f f f f4 m 4
13 Simlification of Switching unctions POS ( ) = ( + )( + )( + )( + ) + f f f f4 f f f f4
14 ( ) ( ) ( ) ( ) ( ) ( ) = = = = + + = + = Simplified functions: find common product terms Multiple Output Implementation Simlification of Switching unctions 4
15 Simlification of Switching unctions Multiple Output Implementation m m m m m 4 m m 5 7 m6 m m m 5 m4 m 8 m9 m m m m m m m 4 m5 m 7 m6 m m m 5 4 m 8 m m m m m m9 m m m 4 m m 5 7 m6 m m m 5 m4 m 8 m9 m m = + + = + + =
16 The End 6
Principles of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents
B-1 Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix B: Reduction of Digital Logic B-2 Chapter Contents B.1 Reduction of Combinational Logic and Sequential Logic B.2 Reduction
More informationKarnaugh Maps (K-Maps)
Karnaugh Maps (K-Maps) Boolean expressions can be minimized by combining terms P + P = P K-maps minimize equations graphically Put terms to combine close to one another B C C B B C BC BC BC BC BC BC BC
More information12/31/2010. Overview. 10-Combinational Circuit Design Text: Unit 8. Limited Fan-in. Limited Fan-in. Limited Fan-in. Limited Fan-in
Overview 10-ombinational ircuit esign Text: Unit 8 Gates with elays and Timing Other Hazards GR/ISS 201 igital Operations and omputations Winter 2011 r. Louie 2 Practical logic gates are limited by the
More informationUnit 8 Problem Solutions
Unit 8 Problem Solutions Unit 8 Solutions 8. W X Y V Z 5 5 2 25 3 35 4 t (ns) 8.2 (a) = '' + + ' Static -hazards: and 8.2 (a) (contd) 8.2 (b) = ( + ') (+ + ) ( + + ') Static -hazards are: and t = '' +
More informationThe Karnaugh Map COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals
The Karnaugh Map COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Boolean Function Minimization The Karnaugh Map (K-Map) Two, Three,
More informationCMSC 313 Lecture 19 Homework 4 Questions Combinational Logic Components Programmable Logic Arrays Introduction to Circuit Simplification
CMSC 33 Lecture 9 Homework 4 Questions Combinational Logic Components Programmable Logic rrays Introduction to Circuit Simplification UMC, CMSC33, Richard Chang CMSC 33, Computer Organization
More informationTextbook: Digital Design, 3 rd. Edition M. Morris Mano
: 25/5/ P-/70 Tetbook: Digital Design, 3 rd. Edition M. Morris Mano Prentice-Hall, Inc. : INSTRUCTOR : CHING-LUNG SU E-mail: kevinsu@yuntech.edu.tw Chapter 3 25/5/ P-2/70 Chapter 3 Gate-Level Minimization
More informationChapter 4 Optimized Implementation of Logic Functions
Chapter 4 Optimized Implementation of Logic Functions Logic Minimization Karnaugh Maps Systematic Approach for Logic Minimization Minimization of Incompletely Specified Functions Tabular Method for Minimization
More informationUNIT III Design of Combinational Logic Circuits. Department of Computer Science SRM UNIVERSITY
UNIT III Design of ombinational Logic ircuits Department of omputer Science SRM UNIVERSITY Introduction to ombinational ircuits Logic circuits for digital systems may be ombinational Sequential combinational
More informationChapter 2. Introduction. Chapter 2 :: Topics. Circuits. Nodes. Circuit elements. Introduction
hapter 2 Introduction igital esign and omputer rchitecture, 2 nd Edition avid Money Harris and Sarah L. Harris logic circuit is composed of: Inputs Outputs Functional specification Timing specification
More informationLecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University
Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University Original Source: Aby K George, ECE Department, Wayne State University Contents The Map method Two variable
More informationWorking with Combinational Logic. Design example: 2x2-bit multiplier
Working with ombinational Logic Simplification two-level simplification exploiting don t cares algorithm for simplification Logic realization two-level logic and canonical forms realized with NNs and NORs
More informationVidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution
S.E. Sem. III [ETRX] Digital Circuits and Design Prelim uestion Paper Solution. (a) Static Hazard Static hazards have two cases: static and static. static- hazard exists when the output variable should
More informationDigital Logic & Computer Design CS Professor Dan Moldovan Spring Copyright 2007 Elsevier 2-<101>
Digital Logic & Computer Design CS 434 Professor Dan Moldovan Spring 2 Copyright 27 Elsevier 2- Chapter 2 :: Combinational Logic Design Digital Design and Computer Architecture David Money Harris and
More informationCombinational logic. Possible logic functions of two variables. Minimal set of functions. Cost of different logic functions.
Combinational logic Possible logic functions of two variables Logic functions, truth tables, and switches NOT, ND, OR, NND, NOR, OR,... Minimal set xioms and theorems of oolean algebra Proofs by re-writing
More informationCMSC 313 Lecture 19 Combinational Logic Components Programmable Logic Arrays Karnaugh Maps
CMSC 33 Lecture 9 Combinational Logic Components Programmable Logic rrays Karnaugh Maps UMC, CMSC33, Richard Chang Last Time & efore Returned midterm exam Half adders & full adders Ripple
More informationDigital Logic & Computer Design CS Professor Dan Moldovan Spring 2010
Digital Logic & Computer Design CS 434 Professor Dan Moldovan Spring 2 Copyright 27 Elsevier 2- Chapter 2 :: Combinational Logic Design Digital Design and Computer rchitecture David Money Harris and
More informationENGR 303 Introduction to Logic Design Lecture 3. Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College
Introduction to Logic Design Lecture 3 Dr. Chuck rown Engineering and Computer Information Science Folsom Lake College Outline for Todays Lecture Logic Circuits SOP / POS oolean Theorems DeMorgan s Theorem
More informationLecture 4: More Boolean Algebra
Lecture 4: More Boolean Algebra Syed M. Mahmud, Ph.D ECE Department Wayne State University Original Source: Prof. Russell Tessier of University of Massachusetts Aby George of Wayne State University ENGIN2
More informationUNIT 5 KARNAUGH MAPS Spring 2011
UNIT 5 KRNUGH MPS Spring 2 Karnaugh Maps 2 Contents Minimum forms of switching functions Two- and three-variable Four-variable Determination of minimum expressions using essential prime implicants Five-variable
More informationCPE/EE 422/522. Chapter 1 - Review of Logic Design Fundamentals. Dr. Rhonda Kay Gaede UAH. 1.1 Combinational Logic
CPE/EE 422/522 Chapter - Review of Logic Design Fundamentals Dr. Rhonda Kay Gaede UAH UAH Chapter CPE/EE 422/522. Combinational Logic Combinational Logic has no control inputs. When the inputs to a combinational
More information3. PRINCIPLES OF COMBINATIONAL LOGIC
Principle of ombinational Logic -. PRINIPLES OF OMINTIONL LOGI Objectives. Understand the design & analysis procedure of combinational logic.. Understand the optimization of combinational logic.. efinitions
More informationLecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps
EE210: Switching Systems Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps Prof. YingLi Tian Feb. 21/26, 2019 Department of Electrical Engineering The City College of New York
More informationLogic and Computer Design Fundamentals. Chapter 2 Combinational Logic Circuits. Part 2 Circuit Optimization
Logic and omputer Design Fundamentals hapter 2 ombinational Logic ircuits Part 2 ircuit Optimization harles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode)
More informationUniversity of Minnesota Department of Electrical and Computer Engineering
University of Minnesota Department of Electrical and Computer Engineering EE2301 Fall 2008 Introduction to Digital System Design L. L. Kinney Final Eam (Closed Book) Solutions Please enter your name, ID
More information( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function
Question Paper Digital Electronics (EE-204-F) MDU Examination May 2015 1. (a) represent (32)10 in (i) BCD 8421 code (ii) Excess-3 code (iii) ASCII code (b) Design half adder using only NAND gates. ( c)
More informationCombinational Logic (mostly review!)
ombinational Logic (mostly review!)! Logic functions, truth tables, and switches " NOT, N, OR, NN, NOR, OR,... " Minimal set! xioms and theorems of oolean algebra " Proofs by re-writing " Proofs by perfect
More informationOptimizations and Tradeoffs. Combinational Logic Optimization
Optimizations and Tradeoffs Combinational Logic Optimization Optimization & Tradeoffs Up to this point, we haven t really considered how to optimize our designs. Optimization is the process of transforming
More informationChapter # 3: Multi-Level Combinational Logic
hapter # 3: Multi-Level ombinational Logic ontemporary Logic esign Randy H. Katz University of alifornia, erkeley June 993 No. 3- hapter Overview Multi-Level Logic onversion to NN-NN and - Networks emorgan's
More informationfor Digital Systems Simplification of logic functions Tajana Simunic Rosing Sources: TSR, Katz, Boriello & Vahid
SE140: omponents and Design Techniques for Digital Systems Simplification of logic functions Tajana Simunic Rosing 1 What we covered thus far: Number representations Where we are now inary, Octal, Hex,
More informationThis form sometimes used in logic circuit, example:
Objectives: 1. Deriving of logical expression form truth tables. 2. Logical expression simplification methods: a. Algebraic manipulation. b. Karnaugh map (k-map). 1. Deriving of logical expression from
More informationWhy digital? Overview. Number Systems. Binary to Decimal conversion
Why digital? Overview It has the following advantages over analog. It can be processed and transmitted efficiently and reliably. It can be stored and retrieved with greater accuracy. Noise level does not
More informationDIGITAL ELECTRONICS & it0203 Semester 3
DIGITAL ELECTRONICS & it0203 Semester 3 P.Rajasekar & C.M.T.Karthigeyan Asst.Professor SRM University, Kattankulathur School of Computing, Department of IT 8/22/2011 1 Disclaimer The contents of the slides
More informationPossible logic functions of two variables
ombinational logic asic logic oolean algebra, proofs by re-writing, proofs by perfect induction logic functions, truth tables, and switches NOT, ND, OR, NND, NOR, OR,..., minimal set Logic realization
More informationGoals for Lecture. Binary Logic and Gates (MK 2.1) Binary Variables. Notation Examples. Logical Operations
Introduction to Electrical Engineering, II LETURE NOTES #2 Instructor: Email: Telephone: Office: ndrew. Kahng (lecture) abk@ucsd.edu 858-822-4884 office 3802 P&M lass Website: http://vlsicad.ucsd.edu/courses/ece20b/wi04/
More information2009 Spring CS211 Digital Systems & Lab CHAPTER 2: INTRODUCTION TO LOGIC CIRCUITS
CHAPTER 2: INTRODUCTION TO LOGIC CIRCUITS What will we learn? 2 Logic functions and circuits Boolean Algebra Logic gates and Synthesis CAD tools and VHDL Read Section 2.9 and 2.0 Terminology 3 Digital
More informationLogic Design Combinational Circuits. Digital Computer Design
Logic Design Combinational Circuits Digital Computer Design Topics Combinational Logic Karnaugh Maps Combinational uilding locks Timing 2 Logic Circuit logic circuit is composed of: Inputs Outputs Functional
More informationL4: Karnaugh diagrams, two-, and multi-level minimization. Elena Dubrova KTH / ICT / ES
L4: Karnaugh diagrams, two-, and multi-level minimization Elena Dubrova KTH / ICT / ES dubrova@kth.se Combinatorial system a(t) not(a(t)) A combinatorial system has no memory - its output depends therefore
More informationUnit 2 Session - 6 Combinational Logic Circuits
Objectives Unit 2 Session - 6 Combinational Logic Circuits Draw 3- variable and 4- variable Karnaugh maps and use them to simplify Boolean expressions Understand don t Care Conditions Use the Product-of-Sums
More informationSimplifying Logic Circuits with Karnaugh Maps
Simplifying Logic Circuits with Karnaugh Maps The circuit at the top right is the logic equivalent of the Boolean expression: f = abc + abc + abc Now, as we have seen, this expression can be simplified
More informationDigital Design 2. Logic Gates and Boolean Algebra
Digital Design 2. Logic Gates and oolean lgebra József Sütő ssistant Lecturer References: [1] D.M. Harris, S.L. Harris, Digital Design and Computer rchitecture, 2nd ed., Elsevier, 213. [2] T.L. Floyd,
More informationK-map Definitions. abc
K-map efinitions b a bc Implicant ny single or any group of s is called an implicant of F. ny possible grouping of s is an implicant. b a Prime Implicant implicant that cannot be combined with some other
More information14:332:231 DIGITAL LOGIC DESIGN
14:332:231 IGITL LOGI ESIGN Ivan Marsic, Rutgers University Electrical & omputer Engineering all 2013 Lecture #17: locked Synchronous -Machine nalysis locked Synchronous Sequential ircuits lso known as
More informationSimplification of Boolean Functions. Dept. of CSE, IEM, Kolkata
Simplification of Boolean Functions Dept. of CSE, IEM, Kolkata 1 Simplification of Boolean Functions: An implementation of a Boolean Function requires the use of logic gates. A smaller number of gates,
More informationCOSC3330 Computer Architecture Lecture 2. Combinational Logic
COSC333 Computer rchitecture Lecture 2. Combinational Logic Instructor: Weidong Shi (Larry), PhD Computer Science Department University of Houston Today Combinational Logic oolean lgebra Mux, DeMux, Decoder
More informationShow that the dual of the exclusive-or is equal to its compliment. 7
Darshan Institute of ngineering and Technology, Rajkot, Subject: Digital lectronics (2300) GTU Question ank Unit Group Questions Do as directed : I. Given that (6)0 = (00)x, find the value of x. II. dd
More informationQuality of Minimal Sets of Prime Implicants of Boolean Functions
INTL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS, 2017, VOL. 63, NO. 2, PP. 165-169 Manuscript received October 9, 2016; revised April, 2017. DOI: 10.1515/eletel-2017-0022 Quality of Minimal Sets of
More informationTheory of Logic Circuits. Laboratory manual. Exercise 1
Zakład Mikroinformatyki i Teorii utomatów Cyfrowych Theory of Logic Circuits Laboratory manual Eercise Combinational switching circuits 008 Urszula Stańczyk, Piotr Czekalski (edt. E.. Combinational switching
More informationFYSE420 DIGITAL ELECTRONICS
FYSE42 IGITAL ELECTRONICS Lecture 4 [] [2] [3] IGITAL LOGIC CIRCUIT ANALYSIS & ESIGN Nelson, Nagle, Irvin, Carrol ISBN -3-463894-8 IGITAL ESIGN Morris Mano Fourth edition ISBN -3-98924-3 igital esign Principles
More information211: Computer Architecture Summer 2016
211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Review: cache hit rate - Project3 - Digital Logic: - truth table => SOP - simplification: Boolean
More informationLOGIC GATES (PRACTICE PROBLEMS)
LOGIC GTES (PRCTICE PROLEMS) Key points and summary First set of problems from Q. Nos. 1 to 9 are based on the logic gates like ND, OR, NOT, NND & NOR etc. First four problems are basic in nature. Problems
More informationAdvanced Digital Logic Design EECS 303. Multi-level example. Two-level form. Multi-level form A B C. Multi-level logic
dvanced igital Logic esign S 33 http://ziyang.eecs.northwestern.edu/eecs33/ Multi-level example Teacher: Robert ick Office: L477 Tech mail: dickrp@northwestern.edu Phone: 847 467 2298 So far, we have talked
More informationName. ECE-200 Intelligent Systems
Name Spring 2003 EE-200 Intelligent Systems Pracice Final Solution ll problems have the same weight Problem 1. We are working with a multiplexor that is to switch between four sources (inputs), each one
More informationCSE140: Components and Design Techniques for Digital Systems. Logic minimization algorithm summary. Instructor: Mohsen Imani UC San Diego
CSE4: Components and Design Techniques for Digital Systems Logic minimization algorithm summary Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing & Dr.Pietro Mercati Definition
More informationCHAPTER III BOOLEAN ALGEBRA
CHAPTER III- CHAPTER III CHAPTER III R.M. Dansereau; v.. CHAPTER III-2 BOOLEAN VALUES INTRODUCTION BOOLEAN VALUES Boolean algebra is a form of algebra that deals with single digit binary values and variables.
More informationZ = F(X) Combinational circuit. A combinational circuit can be specified either by a truth table. Truth Table
Lesson Objectives In this lesson, you will learn about What are combinational circuits Design procedure of combinational circuits Examples of combinational circuit design Combinational Circuits Logic circuit
More informationLecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions
EE210: Switching Systems Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions Prof. YingLi Tian Feb. 15, 2018 Department of Electrical Engineering The City College of New York The
More informationCOMP2611: Computer Organization. Introduction to Digital Logic
1 OMP2611: omputer Organization ombinational Logic OMP2611 Fall 2015 asics of Logic ircuits 2 its are the basis for binary number representation in digital computers ombining bits into patterns following
More informationGate-Level Minimization
Gate-Level Minimization Dr. Bassem A. Abdullah Computer and Systems Department Lectures Prepared by Dr.Mona Safar, Edited and Lectured by Dr.Bassem A. Abdullah Outline 1. The Map Method 2. Four-variable
More informationCS/EE 181a 2008/09 Lecture 4
CS/EE 181a 28/9 Lecture 4 General topic of today s lecture: Logic Optimization Karnaugh maps. Quine-McCluskey tabulation method (not in detail). Non series-parallel networks (some care is required). Reference
More informationSynthesizing Asynchronous Burst-Mode Machines without the Fundamental-Mode Timing Assumption
Synthesizing synchronous urst-mode Machines without the Fundamental-Mode Timing ssumption Gennette Gill Montek Singh Univ. of North Carolina Chapel Hill, NC, US Contribution Synthesize robust asynchronous
More informationEECS Variable Logic Functions
EECS150 Section 1 Introduction to Combinational Logic Fall 2001 2-Variable Logic Functions There are 16 possible functions of 2 input variables: in general, there are 2**(2**n) functions of n inputs X
More informationComputer Organization I. Lecture 13: Design of Combinational Logic Circuits
Computer Organization I Lecture 13: Design of Combinational Logic Circuits Overview The optimization of multiple-level circuits Mapping Technology Verification Objectives To know how to optimize the multiple-level
More informationWorking with combinational logic
Working with combinational logic Simplification two-level simplification exploiting don t cares algorithm for simplification Logic realization two-level logic and canonical forms realized with NNs and
More informationBoolean Algebra and Logic Simplification
S302 Digital Logic Design Boolean Algebra and Logic Simplification Boolean Analysis of Logic ircuits, evaluating of Boolean expressions, representing the operation of Logic circuits and Boolean expressions
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Charles Kime & Thomas Kaminski 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active
More information14:332:231 DIGITAL LOGIC DESIGN. Combinational Circuit Synthesis
:: DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering all Lecture #: Combinational Circuit Synthesis I Combinational Circuit Synthesis Recall: Combinational circuit
More informationCHAPTER III BOOLEAN ALGEBRA
CHAPTER III- CHAPTER III CHAPTER III R.M. Dansereau; v.. CHAPTER III-2 BOOLEAN VALUES INTRODUCTION BOOLEAN VALUES Boolean algebra is a form of algebra that deals with single digit binary values and variables.
More informationCMSC 313 Preview Slides
CMSC 33 Preview Slies These are raft slies. The actual slies presente in lecture may be ifferent ue to last minute changes, scheule slippage,... UMBC, CMSC33, Richar Chang CMSC 33 Lecture
More informationCMSC 313 Lecture 16 Announcement: no office hours today. Good-bye Assembly Language Programming Overview of second half on Digital Logic DigSim Demo
CMSC 33 Lecture 6 nnouncement: no office hours today. Good-bye ssembly Language Programming Overview of second half on Digital Logic DigSim Demo UMC, CMSC33, Richard Chang Good-bye ssembly
More informationELEC Digital Logic Circuits Fall 2015 Logic Minimization (Chapter 3)
ELE 2200-002 igital Logic ircuits Fall 205 Logic Minimization (hapter 3) Vishwani. grawal James J. anaher Professor epartment of Electrical and omputer Engineering uburn University, uburn, L 36849 http://www.eng.auburn.edu/~vagrawal
More informationEXPERIMENT #4: SIMPLIFICATION OF BOOLEAN FUNCTIONS
EXPERIMENT #4: SIMPLIFICATION OF BOOLEAN FUNCTIONS OBJECTIVES: Simplify Boolean functions using K-map method Obtain Boolean expressions from timing diagrams Design and implement logic circuits Equipment
More informationS.E. Sem. III [ETRX] Digital Circuit Design. t phl. Fig.: Input and output voltage waveforms to define propagation delay times.
S.E. Sem. III [ETRX] Digital ircuit Design Time : 3 Hrs.] Prelim Paper Solution [Marks : 80. Solve following : [20].(a) Explain characteristics of logic families. [5] haracteristics of logic families are
More informationCh 2. Combinational Logic. II - Combinational Logic Contemporary Logic Design 1
Ch 2. Combinational Logic II - Combinational Logic Contemporary Logic Design 1 Combinational logic Define The kind of digital system whose output behavior depends only on the current inputs memoryless:
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal
More informationProve that if not fat and not triangle necessarily means not green then green must be fat or triangle (or both).
hapter : oolean lgebra.) Definition of oolean lgebra The oolean algebra is named after George ool who developed this algebra (854) in order to analyze logical problems. n example to such problem is: Prove
More informationOutcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps
-. -. Spiral / Unit Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve
More informationMidterm1 Review. Jan 24 Armita
Midterm1 Review Jan 24 Armita Outline Boolean Algebra Axioms closure, Identity elements, complements, commutativity, distributivity theorems Associativity, Duality, De Morgan, Consensus theorem Shannon
More informationReview for B33DV2-Digital Design. Digital Design
Review for B33DV2 The Elements of Modern Behaviours Design Representations Blocks Waveforms Gates Truth Tables Boolean Algebra Switches Rapid Prototyping Technologies Circuit Technologies TTL MOS Simulation
More informationSpiral 1 / Unit 5. Karnaugh Maps
-. Spiral / Unit Karnaugh Maps -. Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve
More informationCombinational Logic Design
PEN 35 - igital System esign ombinational Logic esign hapter 3 Logic and omputer esign Fundamentals, 4 rd Ed., Mano 2008 Pearson Prentice Hall esign oncepts and utomation top-down design proceeds from
More informationLecture 7: Karnaugh Map, Don t Cares
EE210: Switching Systems Lecture 7: Karnaugh Map, Don t Cares Prof. YingLi Tian Feb. 28, 2019 Department of Electrical Engineering The City College of New York The City University of New York (CUNY) 1
More informationOutcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps
-. -. Spiral / Unit Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve
More informationLecture 5. Karnaugh-Map
Lecture 5 - Lecture 5 Karnaugh-Map Lecture 5-2 Karnaugh-Map Set Logic Venn Diagram K-map Lecture 5-3 K-Map for 2 Variables Lecture 5-4 K-Map for 3 Variables C C C Lecture 5-5 Logic Expression, Truth Table,
More informationAdministrative Notes. Chapter 2 <9>
Administrative Notes Note: New homework instructions starting with HW03 Homework is due at the beginning of class Homework must be organized, legible (messy is not), and stapled to be graded Chapter 2
More information6 Simplification of. Boolean Functions
6 Simplification of Boolean Functions This experiment demonstrates the relationship between a Boolean function and the corresponding logic diagram. The Boolean functions and their complements are simplified
More informationFault Equivalence, Dominance & Collapsing. Fault Equivalence
Fault Equivalence, Dominance & ollapsing Definition: If T a is the set of LL TVs which Detect Fault a, and T b is the set of LL TVs which Detect some other Fault b; the Two Faults a, and b are said to
More informationOutcomes. Spiral 1 / Unit 3. The Problem SYNTHESIZING LOGIC FUNCTIONS
-3. -3.2 Outcomes Spiral / Unit 3 Minterm and Materms Canonical Sums and Products 2 and 3 Variable oolean lgebra Theorems emorgan's Theorem unction Snthesis use Canonical Sums/Products Mark Redekopp I
More informationELEC Digital Logic Circuits Fall 2014 Logic Minimization (Chapter 3)
ELE 2200-002 Digital Logic ircuits Fall 204 Logic Minimization (hapter 3) Vishwani D. grawal James J. Danaher Professor Department of Electrical and omputer Engineering uburn University, uburn, L 36849
More informationContents. Chapter 3 Combinational Circuits Page 1 of 36
Chapter 3 Combinational Circuits Page of 36 Contents Combinational Circuits...2 3. Analysis of Combinational Circuits...3 3.. Using a Truth Table...3 3..2 Using a Boolean Function...6 3.2 Synthesis of
More informationCPE100: Digital Logic Design I
Chapter 2 Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu http://www.ee.unlv.edu/~b1morris/cpe100/ CPE100: Digital Logic Design I Section 1004: Dr. Morris Combinational Logic Design Chapter
More informationCMSC 313 Lecture 15 Good-bye Assembly Language Programming Overview of second half on Digital Logic DigSim Demo
CMSC 33 Lecture 5 Good-bye ssembly Language Programming Overview of second half on Digital Logic DigSim Demo UMC, CMSC33, Richard Chang Good-bye ssembly Language What a pain! Understand
More informationDIGITAL CIRCUIT LOGIC BOOLEAN ALGEBRA
DIGITAL CIRCUIT LOGIC BOOLEAN ALGEBRA 1 Learning Objectives Understand the basic operations and laws of Boolean algebra. Relate these operations and laws to circuits composed of AND gates, OR gates, INVERTERS
More informationLogic Minimization. Two-Level. University of California. Prof. Srinivas Devadas. Prof. Richard Newton Prof. Sanjit Seshia. Prof.
Two-Level Logic Minimization Prof. Srinivas Devadas MIT Prof. Kurt Keutzer Prof. Richard Newton Prof. Sanjit Seshia University of California Berkeley, CA 1 Topics Motivation Boolean functions & notation
More informationSynchronous Sequential Circuit
Synchronous Sequential Circuit The change of internal state occurs in response to the synchronized clock pulses. Data are read during the clock pulse (e.g. rising-edge triggered) It is supposed to wait
More informationWEEK 3.1 MORE ON KARNAUGH MAPS
WEEK 3. MORE ON KARNAUGH MAPS Don t Cares Sometimes, we might have inputs and it doesn t matter what the output is; i.e., we don t care what the output is. These situations are called don t cares. Rather
More informationCPE100: Digital Logic Design I
Chapter 2 Professor Brendan Morris, SEB 326, brendan.morris@unlv.edu http://www.ee.unlv.edu/~bmorris/cpe/ CPE: Digital Logic Design I Section 4: Dr. Morris Combinational Logic Design Chapter 2 Chapter
More informationDepartment of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals
Department of Electrical and Computer Engineering Universit of Wisconsin - Madison ECE/C 352 Digital stem Fundamentals Quiz #2 olution Thursda, Octoer 26, 2000, 7:15--8:30PM 1. (15 points) (a). (5 points)
More informationMC9211 Computer Organization
MC92 Computer Organization Unit : Digital Fundamentals Lesson2 : Boolean Algebra and Simplification (KSB) (MCA) (29-2/ODD) (29 - / A&B) Coverage Lesson2 Introduces the basic postulates of Boolean Algebra
More informationLearning Objectives 10/7/2010. CE 411 Digital System Design. Fundamental of Logic Design. Review the basic concepts of logic circuits. Dr.
/7/ CE 4 Digital ystem Design Dr. Arshad Aziz Fundamental of ogic Design earning Objectives Review the basic concepts of logic circuits Variables and functions Boolean algebra Minterms and materms ogic
More information