Working with Combinational Logic. Design example: 2x2-bit multiplier
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1 Working with ombinational Logic Simplification two-level simplification exploiting don t cares algorithm for simplification Logic realization two-level logic and canonical forms realized with NNs and NORs multi-level logic, converting between Ns and ORs Winter 2010 SE370 - VI - Logic Minimization 1 esign example: 2x2-bit multiplier block diagram and truth table P1 P2 P4 P P8 P4 P2 P variable K-map for each of the 4 output functions Winter 2010 SE370 - VI - Logic Minimization 2
2 esign example: 2x2-bit multiplier (activity) 2 K-map for P8 K-map for P K-map for P2 K-map for P Winter 2010 SE370 - VI - Logic Minimization 3 efinition of terms for two-level simplification Implicant single element of ON-set or -set or any group of these elements that can be combined to form a subcube Prime implicant implicant that can't be combined with another to form a larger subcube Essential prime implicant prime implicant is essential if it alone covers an element of ON-set will participate in LL possible covers of the ON-set -set used to form prime implicants but not to make implicant essential Objective: grow implicant into prime implicants (minimize literals per term) cover the ON-set with as few prime implicants as possible (minimize number of product terms) Winter 2010 SE370 - VI - Logic Minimization 4
3 Examples to illustrate terms 0 X 6 prime implicants: '', ',, '',, ' essential minimum cover: + ' + '' 5 prime implicants:, ',, ', '' essential minimum cover: 4 essential implicants Winter 2010 SE370 - VI - Logic Minimization 5 lgorithm for two-level simplification lgorithm: minimum sum-of-products expression from a Karnaugh map Step 1: choose an element of the ON-set Step 2: find "maximal" groupings of 1s and Xs adjacent to that element consider top/bottom row, left/right column, and corner adjacencies this forms prime implicants (number of elements always a power of 2) Repeat Steps 1 and 2 to find all prime implicants Step 3: revisit the 1s in the K-map if covered by single prime implicant, it is essential, and participates in final cover 1s covered by essential prime implicant do not need to be revisited Step 4: if there remain 1s not covered by essential prime implicants select the smallest number of prime implicants that cover the remaining 1s Winter 2010 SE370 - VI - Logic Minimization 6
4 lgorithm for two-level simplification (example) 0 X X 0 2 primes around ''' 2 primes around ' 3 primes around ''' 2 essential primes minimum cover (3 primes) Winter 2010 SE370 - VI - Logic Minimization 7 ctivity List all prime implicants for the following K-map: X 0 X 0 0 X X 0 Which are essential prime implicants? What is the minimum cover? Winter 2010 SE370 - VI - Logic Minimization 8
5 Implementations of two-level logic Sum-of-products N gates to form product terms (minterms) OR gate to form sum Product-of-sums OR gates to form sum terms (maxterms) N gates to form product Winter 2010 SE370 - VI - Logic Minimization 9 Two-level logic using NN gates (cont d) OR gate with inverted inputs is a NN gate de Morgan s: + = ( ) Two-level NN-NN network inverted inputs are not counted in a typical circuit, inversion is done once and signal distributed Winter 2010 SE370 - VI - Logic Minimization 10
6 Two-level logic using NOR gates (cont d) N gate with inverted inputs is a NOR gate de Morgan s: = ( + ) Two-level NOR-NOR network inverted inputs are not counted in a typical circuit, inversion is done once and signal distributed Winter 2010 SE370 - VI - Logic Minimization 11 Multi-level logic x = + E + + E + + E + G reduced sum-of-products form already simplified 6 x 3-input N gates + 1 x 7-input OR gate (that may not even exist!) 25 wires (19 literals plus 6 internal wires) x = ( + + ) ( + E) + G factored form not written as two-level S-o-P 1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input N gate 10 wires (7 literals plus 3 internal wires) E G Winter 2010 SE370 - VI - Logic Minimization 12 X
7 onversion of multi-level logic to NN gates = ( + ) + original N-OR network \ Level 1 Level 2 Level 3 Level 4 introduction and conservation of bubbles \ redrawn in terms of conventional NN gates \ \ Winter 2010 SE370 - VI - Logic Minimization 13 onversion of multi-level logic to NORs = ( + ) + introduction and conservation of bubbles original N-OR network \ Level 1 Level 2 Level 3 Level 4 \ redrawn in terms of conventional NOR gates \ \ \ \ Winter 2010 SE370 - VI - Logic Minimization 14
8 Summary for multi-level logic dvantages circuits may be smaller gates have smaller fan-in circuits may be faster isadvantages more difficult to design tools for optimization are not as good as for two-level analysis is more complex Winter 2010 SE370 - VI - Logic Minimization 15
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