Combinational logic. Possible logic functions of two variables. Minimal set of functions. Cost of different logic functions

Transcription

1 ombinational logic Possible logic functions of two variables asic logic oolean algebra, proofs by re-writing, proofs by perfect induction Logic functions, truth tables, and switches NOT, N, OR, NN,, OR,..., minimal set Logic realization two-level logic and canonical forms, incompletely specified functions multi-level logic, converting between Ns and ORs Simplification uniting theorem transformations on networks of oolean functions Time behavior Hardware description languages There are 16 possible functions of 2 input variables: in general, there are 2**(2**n) functions of n inputs Y 16 possible functions (0 15) and Y Y Y xor Y or Y = Y nor Y not ( or Y) not Y 1 not nand Y not ( and Y) Winter 2001 SE370 - II - ombinational Logic 1 Winter 2001 SE370 - II - ombinational Logic 2 ost of different logic functions Minimal set of functions ifferent functions are easier or harder to implement each has a cost associated with the number of switches needed 0 (0) and 1 (15): require 0 switches, directly connect output to low/high (3) and Y (5): require 0 switches, output is one of inputs (12) and Y (10): require 2 switches for "inverter" or NOT-gate nor Y (4) and nand Y (14): require 4 switches or Y (7) and and Y (1): require 6 switches = Y (9) and Y (6): require 16 switches thus, because NOT,, and NN are the cheapest they are the functions we implement the most in practice an we implement all logic functions from NOT,, and NN? or example, implementing and Y is the same as implementing not ( nand Y) In fact, we can do it with only or only NN NOT is just a NN or a with both inputs tied together Y nor Y and NN and are "duals", Y nand Y that is, its easy to implement one using the other nand Y not ( (not ) nor (not Y) ) ut lets not move nory too fast... not ((not) nand (not Y) ) lets look at the mathematical foundation of logic Winter 2001 SE370 - II - ombinational Logic 3 Winter 2001 SE370 - II - ombinational Logic 4

2 n algebraic structure oolean algebra n algebraic structure consists of a set of elements binary operations { +, } and a unary operation { } such that the following axioms hold: 1. the set contains at least two elements: a, b 2. closure: a + b is in a b is in 3. commutativity: a + b = b + a a b = b a 4. associativity: a + (b + c) = (a + b) + c a (b c) = (a b) c 5. identity: a + 0 = a a 1 = a 6. distributivity: a + (b c) = (a + b) (a + c) a (b + c) = (a b) + (a c) 7. complementarity: a + a = 1 a a = 0 oolean algebra = {0, 1} variables + is logical OR, is logical N is logical NOT ll algebraic axioms hold Winter 2001 SE370 - II - ombinational Logic 5 Winter 2001 SE370 - II - ombinational Logic 6 Logic functions and oolean algebra xioms and theorems of oolean algebra ny logic function that can be expressed as a truth table can be written as an expression in oolean algebra using the operators:, +, and Y Y Y Y Y Y ( Y ) + ( Y ) ( Y ) + ( Y ) = Y , Y are oolean algebra variables Y Y oolean expression that is true when the variables and Y have the same value and false, otherwise identity = 1. 1 = null = = 0 idempotency: 3. + = 3. = involution: 4. ( ) = complementarity: 5. + = 1 5. = 0 commutativity: 6. + Y = Y + 6. Y = Y associativity: 7. ( + Y) + = + (Y + ) 7. ( Y) = (Y ) Winter 2001 SE370 - II - ombinational Logic 7 Winter 2001 SE370 - II - ombinational Logic 8

3 xioms and theorems of oolean algebra (cont d) xioms and theorems of oolean algebra (cont ) distributivity: 8. (Y + ) = ( Y) + ( ) 8. + (Y ) = ( + Y) ( + ) uniting: 9. Y + Y = 9. ( + Y) ( + Y ) = absorption: Y = 10. ( + Y) = 11. ( + Y ) Y = Y 11. ( Y ) + Y = + Y factoring: 12. ( + Y) ( + ) = 12. Y + = + Y ( + ) ( + Y) concensus: 13. ( Y) + (Y ) + ( ) = 13. ( + Y) (Y + ) ( + ) = Y + ( + Y) ( + ) de Morgan s: 14. ( + Y +...) = Y ( Y...) = + Y +... generalized de Morgan s: 15. f ( 1, 2,..., n,0,1,+, ) = f( 1, 2,..., n,1,0,,+) establishes relationship between and + Winter 2001 SE370 - II - ombinational Logic 9 Winter 2001 SE370 - II - ombinational Logic 10 xioms and theorems of oolean algebra (cont ) Proving theorems (rewriting) uality a dual of a oolean expression is derived by replacing by +, + by, 0 by 1, and 1 by 0, and leaving variables unchanged any theorem that can be proven is thus also proven for its dual! a meta-theorem (a theorem about theorems) duality: Y +... Y... generalized duality: 17. f ( 1, 2,..., n,0,1,+, ) f( 1, 2,..., n,1,0,,+) ifferent than demorgan s Law this is a statement about theorems this is not a way to manipulate (re-write) expressions Using the axioms of oolean algebra: e.g., prove the theorem: Y + Y = distributivity (8) Y + Y = (Y + Y ) complementarity (5) (Y + Y ) = (1) identity (1) (1) = e.g., prove the theorem: + Y = identity (1) + Y = 1 + Y distributivity (8) 1 + Y = (1 + Y) identity (2) (1 + Y) = (1) identity (1) (1) = Winter 2001 SE370 - II - ombinational Logic 11 Winter 2001 SE370 - II - ombinational Logic 12

4 ctivity Proving theorems (perfect induction) Prove the following using the laws of oolean algebra: ( Y) + (Y ) + ( ) = Y + Using perfect induction (complete truth table): e.g., de Morgan s: ( Y) + (Y ) + ( ) identity ( Y) + (1) (Y ) + ( ) complementarity ( Y) + ( + ) (Y ) + ( ) ( + Y) = Y is equivalent to N with inputs complemented Y Y ( + Y) Y distributivity ( Y) + ( Y ) + ( Y ) + ( ) associativity ( Y) + ( Y ) + ( Y ) + ( ) factoring ( Y) (1 + ) + ( ) (1 + Y) ( Y) = + Y NN is equivalent to OR with inputs complemented Y Y ( Y) + Y null ( Y) (1) + ( ) (1) identity ( Y) + ( ) Winter 2001 SE370 - II - ombinational Logic 13 Winter 2001 SE370 - II - ombinational Logic 14 simple example: 1-bit binary adder pply the theorems to simplify expressions Inputs:,, arry-in Outputs: Sum, arry-out in S out S out in S = in + in + in + in out = in + in + in + in The theorems of oolean algebra can simplify oolean expressions e.g., full adder s carry-out function (same rules apply to any function) out = in + in + in + in = in + in + in + in + in = in + in + in + in + in = ( + ) in + in + in + in = (1) in + in + in + in = in + in + in + in + in = in + in + in + in + in = in + ( + ) in + in + in = in + (1) in + in + in = in + in + (in + in) = in + in + (1) = in + in + adding extra terms creates new factoring opportunities Winter 2001 SE370 - II - ombinational Logic 15 Winter 2001 SE370 - II - ombinational Logic 16

5 ctivity ctivity ill in the truth-table for a circuit that checks that a 4-bit number is divisible by 2, 3, or y2 y3 y Write down oolean expressions for y2, y3, and y y2 y3 y y2 = = 1 y3 = y5 = Winter 2001 SE370 - II - ombinational Logic 17 Winter 2001 SE370 - II - ombinational Logic 18 rom oolean expressions to logic gates rom oolean expressions to logic gates (cont d) NOT ~ N Y Y Y OR + Y Y Y Y Y Y Y Y NN OR Y = Y Y Y Y Y Y Y Y Y xory = Y + Y or Y but not both ("inequality", "difference") xnory=y+ Y and Y are the same ("equality", "coincidence") Winter 2001 SE370 - II - ombinational Logic 19 Winter 2001 SE370 - II - ombinational Logic 20

6 rom oolean expressions to logic gates (cont d) Waveform view of logic functions More than one way to map expressions to gates e.g., = ( + ) = ( ( ( + ))) T2 T1 Just a sideways truth table but note how edges don t line up exactly it takes time for a gate to switch its output! time use of 3-input gate T1 T2 change in Y takes time to "propagate" through gates Winter 2001 SE370 - II - ombinational Logic 21 Winter 2001 SE370 - II - ombinational Logic 22 hoosing different realizations of a function Which realization is best? two-level realization (we don t count NOT gates) multi-level realization (gates with fewer inputs) Reduce number of inputs literal: input variable (complemented or not) can approximate cost of logic gate as 2 transitors per literal why not count inverters? fewer literals means less transistors smaller circuits fewer inputs implies faster gates gates are smaller and thus also faster fan-ins (# of gate inputs) are limited in some technologies Reduce number of gates fewer gates (and the packages they come in) means smaller circuits directly influences manufacturing costs OR gate (easier to draw but costlier to build) Winter 2001 SE370 - II - ombinational Logic 23 Winter 2001 SE370 - II - ombinational Logic 24

7 Which is the best realization? (cont d) re all realizations equivalent? Reduce number of levels of gates fewer level of gates implies reduced signal propagation delays minimum delay configuration typically requires more gates wider, less deep circuits How do we explore tradeoffs between increased circuit delay and size? automated tools to generate different solutions logic minimization: reduce number of gates and complexity logic optimization: reduction while trading off against delay Under the same input stimuli, the three alternative implementations have almost the same waveform behavior delays are different glitches (hazards) may arise variations due to differences in number of gate levels and structure The three implementations are functionally equivalent Winter 2001 SE370 - II - ombinational Logic 25 Winter 2001 SE370 - II - ombinational Logic 26 Implementing oolean functions anonical forms Technology independent canonical forms two-level forms multi-level forms Technology choices packages of a few gates regular logic two-level programmable logic multi-level programmable logic Truth table is the unique signature of a oolean function Many alternative gate realizations may have the same truth table anonical forms standard forms for a oolean expression provides a unique algebraic signature Winter 2001 SE370 - II - ombinational Logic 27 Winter 2001 SE370 - II - ombinational Logic 28

8 Sum-of-products canonical forms Sum-of-products canonical form (cont d) lso known as disjunctive normal form lso known as minterm expansion Product term (or minterm) Ned product of literals input combination for which output is true each variable appears exactly once, in true or inverted form (but not both) = = = + + Winter 2001 SE370 - II - ombinational Logic 29 minterms m m m m m m m m7 short-hand notation for minterms of 3 variables in canonical form: (,, ) = Σm(1,3,5,6,7) = m1 + m3 + m5 + m6 + m7 = canonical form minimal form (,, ) = = ( ) + = (( + )( + )) + = + = + = + Winter 2001 SE370 - II - ombinational Logic 30 Product-of-sums canonical form Product-of-sums canonical form (cont d) lso known as conjunctive normal form lso known as maxterm expansion Sum term (or maxterm) ORed sum of literals input combination for which output is false each variable appears exactly once, in true or inverted form (but not both) = = ( + + ) ( + + ) ( + + ) maxterms M M M M M M M M7 in canonical form: (,, ) = ΠM(0,2,4) = M0 M2 M4 = ( + + ) ( + + ) ( + + ) canonical form minimal form (,, ) = ( + + ) ( + + ) ( + + ) = ( + + ) ( + + ) ( + + ) ( + + ) = ( + ) ( + ) = ( + + ) ( + + ) ( + + ) ( + + ) ( + + ) Winter 2001 SE370 - II - ombinational Logic 31 short-hand notation for maxterms of 3 variables Winter 2001 SE370 - II - ombinational Logic 32

9 S-o-P, P-o-S, and de Morgan s theorem our alternative two-level implementations of = + Sum-of-products = + + pply de Morgan s ( ) = ( + + ) = ( + + ) ( + + ) ( + + ) 1 canonical sum-of-products minimized sum-of-products Product-of-sums = ( + + ) ( + + ) ( + + ) ( + + ) ( + + ) pply de Morgan s ( ) = ( ( + + )( + + )( + + )( + + )( + + ) ) = canonical product-of-sums minimized product-of-sums 4 Winter 2001 SE370 - II - ombinational Logic 33 Winter 2001 SE370 - II - ombinational Logic 34 Waveforms for the four alternatives Mapping between canonical forms Waveforms are essentially identical except for timing hazards (glitches) delays almost identical (modeled as a delay per level, not type of gate or number of inputs to gate) Minterm to maxterm conversion use maxterms whose indices do not appear in minterm expansion e.g., (,,) = Σm(1,3,5,6,7) = ΠM(0,2,4) Maxterm to minterm conversion use minterms whose indices do not appear in maxterm expansion e.g., (,,) = ΠM(0,2,4) = Σm(1,3,5,6,7) Minterm expansion of to minterm expansion of use minterms whose indices do not appear e.g., (,,) = Σm(1,3,5,6,7) (,,) = Σm(0,2,4) Maxterm expansion of to maxterm expansion of use maxterms whose indices do not appear e.g., (,,) = ΠM(0,2,4) (,,) = ΠM(1,3,5,6,7) Winter 2001 SE370 - II - ombinational Logic 35 Winter 2001 SE370 - II - ombinational Logic 36

10 Incompleteley specified functions Notation for incompletely specified functions Example: binary coded decimal increment by 1 digits encode the decimal digits 0 9 in the bit patterns W Y off-set of W on-set of W don t care () set of W these inputs patterns should never be encountered in practice "don t care" about associated output values, can be exploited in minimization on t cares and canonical forms so far, only represented on-set also represent don t-care-set need two of the three sets (on-set, off-set, dc-set) anonical representations of the increment by 1 function: = m0 + m2 + m4 + m6 + m8 + d10 + d11 + d12 + d13 + d14 + d15 = Σ [ m(0,2,4,6,8) + d(10,11,12,13,14,15) ] = M1 M3 M5 M7 M = Π [ M(1,3,5,7,9) (10,11,12,13,14,15) ] Winter 2001 SE370 - II - ombinational Logic 37 Winter 2001 SE370 - II - ombinational Logic 38 Simplification of two-level combinational logic The uniting theorem inding a minimal sum of products or product of sums realization exploit don t care information in the process lgebraic simplification not an algorithmic/systematic procedure how do you know when the minimum realization has been found? omputer-aided design tools precise solutions require very long computation times, especially for functions with many inputs (> 10) heuristic methods employed "educated guesses" to reduce amount of computation and yield good if not best solutions Hand methods still relevant to understand automatic tools and their strengths and weaknesses ability to check results (on small examples) Key tool to simplification: ( + ) = Essence of simplification of two-level logic find two element subsets of the ON-set where only one variable changes its value this single varying variable can be eliminated and a single product term used to represent both elements = + = ( +) = has the same value in both on-set rows remains has a different value in the two rows is eliminated Winter 2001 SE370 - II - ombinational Logic 39 Winter 2001 SE370 - II - ombinational Logic 40

11 Implementations of two-level logic Two-level logic using NN gates Sum-of-products N gates to form product terms (minterms) OR gate to form sum Replace minterm N gates with NN gates Place compensating inversion at inputs of OR gate Product-of-sums OR gates to form sum terms (maxterms) N gates to form product Winter 2001 SE370 - II - ombinational Logic 41 Winter 2001 SE370 - II - ombinational Logic 42 Two-level logic using NN gates (cont d) Two-level logic using gates OR gate with inverted inputs is a NN gate de Morgan s: + = ( ) Two-level NN-NN network inverted inputs are not counted in a typical circuit, inversion is done once and signal distributed Replace maxterm OR gates with gates Place compensating inversion at inputs of N gate Winter 2001 SE370 - II - ombinational Logic 43 Winter 2001 SE370 - II - ombinational Logic 44

12 Two-level logic using gates (cont d) Two-level logic using NN and gates N gate with inverted inputs is a gate de Morgan s: = ( + ) Two-level - network inverted inputs are not counted in a typical circuit, inversion is done once and signal distributed NN-NN and - networks de Morgan s law: ( + ) = ( ) = + written differently: + = ( ) ( ) = ( + ) In other words OR is the same as NN with complemented inputs N is the same as with complemented inputs NN is the same as OR with complemented inputs is the same as N with complemented inputs OR OR N N NN NN Winter 2001 SE370 - II - ombinational Logic 45 Winter 2001 SE370 - II - ombinational Logic 46 onversion between forms onversion between forms (cont d) onvert from networks of Ns and ORs to networks of NNs and s introduce appropriate inversions ("bubbles") Each introduced "bubble" must be matched by a corresponding "bubble" conservation of inversions do not alter logic function Example: N/OR to NN/NN Example: verify equivalence of two forms NN NN NN NN NN NN = [ ( ) ( ) ] = [ ( + ) ( + ) ] = [ ( + ) + ( + ) ] = ( ) + ( ) Winter 2001 SE370 - II - ombinational Logic 47 Winter 2001 SE370 - II - ombinational Logic 48

13 onversion between forms (cont d) onversion between forms (cont d) Example: map N/OR network to / network Example: verify equivalence of two forms conserve "bubbles" Step 1 \ \ \ \ Step 2 conserve "bubbles" \ \ \ \ = { [ ( + ) + ( + ) ] } = { ( + ) ( + ) } = ( + ) + ( + ) = ( ) + ( ) Winter 2001 SE370 - II - ombinational Logic 49 Winter 2001 SE370 - II - ombinational Logic 50 Multi-level logic onversion of multi-level logic to NN gates x = + E + + E + + E + G reduced sum-of-products form already simplified 6 x 3-input N gates + 1 x 7-input OR gate (that may not even exist!) 25 wires (19 literals plus 6 internal wires) x = ( + + ) ( + E) + G factored form not written as two-level S-o-P 1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input N gate 10 wires (7 literals plus 3 internal wires) = ( + ) + original N-OR network introduction and conservation of bubbles \ \ Level 1 Level 2 Level 3 Level 4 E G redrawn in terms of conventional NN gates \ \ Winter 2001 SE370 - II - ombinational Logic 51 Winter 2001 SE370 - II - ombinational Logic 52

14 onversion of multi-level logic to s onversion between forms = ( + ) + original N-OR network introduction and conservation of bubbles \ Level 1 Level 2 Level 3 Level 4 Example (a) original circuit add double bubbles at inputs (b) \ redrawn in terms of conventional gates \ \ \ (c) \ \ distribute bubbles some mismatches \ \ insert inverters to fix mismatches (d) \ Winter 2001 SE370 - II - ombinational Logic 53 Winter 2001 SE370 - II - ombinational Logic 54 N-OR-invert gates onversion to OI forms OI function: three stages of logic N, OR, Invert multiple gates "packaged" as a single circuit block logical concept N OR Invert 2x2 OI gate symbol + possible implementation NN NN Invert 3x2 OI gate symbol + General procedure to place in OI form compute the complement of the function in sum-of-products form by grouping the 0s in the Karnaugh map Example: OR implementation xor = + OI form: = ( + ) + Winter 2001 SE370 - II - ombinational Logic 55 Winter 2001 SE370 - II - ombinational Logic 56

15 Examples of using OI gates Examples of using OI gates (cont d) Example: = + + = + + Implemented by 2-input 3-stack OI gate = ( + ) ( + ) ( + ) = ( + ) ( + ) ( + ) Implemented by 2-input 3-stack OI gate Example: 4-bit equality function = ( )( )( )( ) Example: OI implementation of 4-bit equality function high if 0 0 low if 0 = 0 conservation of bubbles if all inputs are low then i = i, i=0,...,3 output is high each implemented in a single 2x2 OI gate Winter 2001 SE370 - II - ombinational Logic 57 Winter 2001 SE370 - II - ombinational Logic 58 Summary for multi-level logic Time behavior of combinational networks dvantages circuits may be smaller gates have smaller fan-in circuits may be faster isadvantages more difficult to design tools for optimization are not as good as for two-level analysis is more complex Waveforms visualization of values carried on signal wires over time useful in explaining sequences of events (changes in value) Simulation tools are used to create these waveforms input to the simulator includes gates and their connections input stimulus, that is, input signal waveforms Some terms gate delay time for change at input to cause change at output min delay typical/nominal delay max delay careful designers design for the worst case rise time time for output to transition from low to high voltage fall time time for output to transition from high to low voltage pulse width time that an output stays high or stays low between changes Winter 2001 SE370 - II - ombinational Logic 59 Winter 2001 SE370 - II - ombinational Logic 60

16 Momentary changes in outputs Oscillatory behavior an be useful pulse shaping circuits an be a problem incorrect circuit operation (glitches/hazards) Example: pulse shaping circuit = 0 delays matter in function nother pulse shaping circuit close switch resistor open switch + initially undefined open switch remains high for three gate delays after changes from low to high is not always 0 pulse 3 gate-delays wide Winter 2001 SE370 - II - ombinational Logic 61 Winter 2001 SE370 - II - ombinational Logic 62 Hardware description languages escribe hardware at varying levels of abstraction Structural description textual replacement for schematic hierarchical composition of modules from primitives ehavioral/functional description describe what module does, not how synthesis generates circuit for module Simulation semantics HLs bel (circa 1983) - developed by ata-i/o targeted to programmable logic devices not good for much more than state machines ISP (circa 1977) - research project at MU simulation, but no synthesis Verilog (circa 1985) - developed by Gateway (absorbed by adence) similar to Pascal and delays is only interaction with simulator fairly efficient and easy to write IEEE standard VHL (circa 1987) - o sponsored standard similar to da (emphasis on re-use and maintainability) simulation semantics visible very general but verbose IEEE standard Winter 2001 SE370 - II - ombinational Logic 63 Winter 2001 SE370 - II - ombinational Logic 64

17 Verilog Structural model Supports structural and behavioral descriptions Structural explicit structure of the circuit e.g., each logic gate instantiated and connected to others ehavioral program describes input/output behavior of circuit many structural implementations could have same behavior e.g., different implementation of one oolean function We ll only be using behavioral Verilog in esignworks rely on schematic when we want structural descriptions module xor_gate (out, a, b); input a, b; output out; wire abar, bbar, t1, t2; inverter inv (abar, a); inverter inv (bbar, b); and_gate and1 (t1, a, bbar); and_gate and2 (t2, b, abar); or_gate or1 (out, t1, t2); endmodule Winter 2001 SE370 - II - ombinational Logic 65 Winter 2001 SE370 - II - ombinational Logic 66 Simple behavioral model Simple behavioral model ontinuous assignment module xor_gate (out, a, b); input a, b; output out; reg out; assign #6 out = a ^ b; endmodule delay from input change to output change simulation register - keeps track of value of signal always block module xor_gate (out, a, b); input a, b; output out; reg out; or b) begin #6 out = a ^ b; end endmodule specifies when block is executed ie. triggered by which signals Winter 2001 SE370 - II - ombinational Logic 67 Winter 2001 SE370 - II - ombinational Logic 68

18 riving a simulation omplete Simulation module stimulus (x, y); output x, y; reg [1:0] cnt; 2-bit vector Instantiate stimulus component and device to test in a schematic initial begin cnt = 0; repeat (4) begin #10 cnt = cnt + 1; initial block executed only once at start of simulation $display ("@ time=%d, x=%b, y=%b, cnt=%b", $time, x, y, cnt); end #10 $finish; print to a console end x y a b z assign x = cnt[1]; assign y = cnt[0]; endmodule directive to stop simulation Winter 2001 SE370 - II - ombinational Logic 69 Winter 2001 SE370 - II - ombinational Logic 70 omparator Example More omplex ehavioral Model module ompare1 (,, Equal, larger, larger); input, ; output Equal, larger, larger; assign #5 Equal = ( ) (~ ~); assign #3 larger = ( ~); assign #3 larger = (~ ); endmodule module life (n0, n1, n2, n3, n4, n5, n6, n7, self, out); input n0, n1, n2, n3, n4, n5, n6, n7, self; output out; reg out; reg [7:0] neighbors; reg [3:0] count; reg [3:0] i; assign neighbors = {n7, n6, n5, n4, n3, n2, n1, n0}; or self) begin count = 0; for (i = 0; i < 8; i = i+1) count = count + neighbors[i]; out = (count == 3); out = out ((self == 1) (count == 2)); end endmodule Winter 2001 SE370 - II - ombinational Logic 71 Winter 2001 SE370 - II - ombinational Logic 72

19 Hardware escription Languages vs. Programming Languages Hardware escription Languages and ombinational Logic Program structure instantiation of multiple components of the same type specify interconnections between modules via schematic hierarchy of modules (only leaves can be HL in esignworks) ssignment continuous assignment (logic always computes) propagation delay (computation takes time) timing of signals is important (when does computation have its effect) ata structures size explicitly spelled out - no dynamic structures no pointers Parallelism hardware is naturally parallel (must support multiple threads) assignments can occur in parallel (not just sequentially) Modules - specification of inputs, outputs, bidirectional, and internal signals ontinuous assignment - a gate s output is a function of its inputs at all times (doesn t need to wait to be "called") Propagation delay- concept of time and delay in input affecting gate output omposition - connecting modules together with wires Hierarchy - modules encapsulate functional blocks Specification of don t care conditions (accomplished by setting output to x ) Winter 2001 SE370 - II - ombinational Logic 73 Winter 2001 SE370 - II - ombinational Logic 74 ombinational logic summary Logic functions, truth tables, and switches NOT, N, OR, NN,, OR,..., minimal set xioms and theorems of oolean algebra proofs by re-writing and perfect induction Gate logic networks of oolean functions and their time behavior anonical forms two-level and incompletely specified functions Simplification two-level simplification Later automation of simplification multi-level logic design case studies time behavior Winter 2001 SE370 - II - ombinational Logic 75