Review. EECS Components and Design Techniques for Digital Systems. Lec 06 Minimizing Boolean Logic 9/ Review: Canonical Forms
|
|
- Josephine Thornton
- 6 years ago
- Views:
Transcription
1 Review EECS Components and Design Techniques for Digital Systems Lec 06 Minimizing Boolean Logic 9/16-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley 9/16/04 UCB EECS150 D. Culler Fa04 1 Combinational logic Truth Tables vs Boolean Expressions vs Gates Minimal Operators And / Or / Not, NAND, NOR New Friends XOR, EQ, Full Adder Boolean Algebra +, *, ~, assoc, comm, distr.,. Manipulating Expressions and Circuits Proofs: Term rewriting & Exhaustive Enumeration Simplifications De Morgan s Law Duality Canonical and minimal forms Sum of products Product of sums 9/16/04 UCB EECS150 D. Culler Fa04 2 Review: Relationship Among Representations * Theorem: Any Boolean function that can be expressed as a truth table can be written as an expression in Boolean Algebra using AND, OR, NOT. unique? Truth Table not unique Boolean Expression [convenient for manipulation] gate representation (schematic) 9/16/04 UCB EECS150 D. Culler Fa04 3? [close to implementaton] How do we convert from one to the other? Optimizations? not unique Review: Canonical Forms Standard form for a Boolean expression - unique algebraic expression directly from a true table (TT) description. Two Types: * Sum of Products (SOP) * Product of Sums (POS) Sum of Products (disjunctive normal form, minterm expansion). Example: minterms a b c f f a b c a b c a bc a bc ab c ab c abc abc One product (and) term for each 1 in f: f = a bc + ab c + ab c +abc +abc f = a b c + a b c + a bc 9/16/04 UCB EECS150 D. Culler Fa04 4 Review: Sum of Products (cont.) Canonical Forms are usually not minimal: Our Example: f = a bc + ab c + ab c + abc +abc (xy + xy = x) = a bc + ab + ab = a bc + a (x y + x = y + x) = a + bc f = a b c + a b c + a bc = a b + a bc = a ( b + bc ) = a ( b + c ) = a b + a c 9/16/04 UCB EECS150 D. Culler Fa04 5 Review: Canonical Forms Product of Sums (conjunctive normal form, maxterm expansion). Example: maxterms a b c f f a+b+c a+b+c a+b +c a+b +c a +b+c a +b+c a +b +c a +b +c One sum (or) term for each 0 in f: f = (a+b+c)(a+b+c )(a+b +c) f = (a+b +c )(a +b+c)(a +b+c ) (a +b +c)(a+b+c ) Mapping from SOP to POS (or POS to SOP): Derive truth table then proceed. 9/16/04 UCB EECS150 D. Culler Fa04 6
2 ncompletely specified functions Example: binary coded decimal increment by 1 BCD digits encode decimal digits 0 9 in bit patterns %&!" # # $ 9/16/04 UCB EECS150 D. Culler Fa04 Outline Review De Morgan s to transform SofP into simple 2-level forms Uniting Law to reduce SofP N-cube perspective Announcements Karnaugh Maps Examples Reduction Algorithm 9/16/04 UCB EECS150 D. Culler Fa04 8 Putting DeMorgan s to work Transformation to Simple Gates DeMorgan s Law: (a + b) = a b (a b) = a + b a + b = (a b ) (a b) = (a + b ) = = = = Sum of Products nvolution: x = (x ) push bubbles or introduce in pairs or remove pairs. = De Morgans 9/16/04 UCB EECS150 D. Culler Fa04 9 9/16/04 UCB EECS150 D. Culler Fa04 10 mplementations of Two-level Logic Sum-of-products AND gates to form product terms (minterms) OR gate to form sum Two-level Logic using NAND Gates Replace minterm AND gates with NAND gates Place compensating inversion at inputs of OR gate Product-of-sums OR gates to form sum terms (maxterms) AND gates to form product 9/16/04 UCB EECS150 D. Culler Fa /16/04 UCB EECS150 D. Culler Fa04 12
3 Two-level Logic using NAND Gates OR gate with inverted inputs is a NAND gate de Morgan's: A'+ B'= (A B)' Two-level NAND-NAND network nverted inputs are not counted n a typical circuit, inversion is done once and signal distributed Two-level Logic using NOR Gates Replace maxterm OR gates with NOR gates Place compensating inversion at inputs of AND gate 9/16/04 UCB EECS150 D. Culler Fa /16/04 UCB EECS150 D. Culler Fa04 14 Two-level Logic using NOR Gates AND gate with inverted inputs is a NOR gate de Morgan's: A' B'= (A + B)' Two-level NOR-NOR network nverted inputs are not counted n a typical circuit, inversion is done once and signal distributed The Uniting Theorem Key tool to simplification: A (B'+ B) = A Essence of simplification of two-level logic Find two element subsets of the ON-set where only one variable changes its value this single varying variable can be eliminated and a single product term used to represent both elements () * )% *& ) # ' # ' ' # 9/16/04 UCB EECS150 D. Culler Fa /16/04 UCB EECS150 D. Culler Fa04 16 Boolean cubes Visual technique for identifying when the uniting theorem can be applied n input variables = n-dimensional "cube Neighbors address differs by one bit flip 9/16/04 UCB EECS150 D. Culler Fa04 1 Mapping truth tables onto Boolean cubes Uniting theorem combines two "faces" of a cube into a larger "face" Example: +, ) + (()# - ) ' $%& # $%& '! 9/16/04 UCB EECS150 D. Culler Fa04 18
4 Three variable example Binary full-adder carry-out logic Higher dimensional cubes Sub-cubes of higher dimension than 2 % *& % *& %* & # -- # %+.& ' # - /0 # (%!!&)Σ# %1!2!3!4& # 5 66!# " 66!8# # %&9 - : )** 9/16/04 UCB EECS150 D. Culler Fa /16/04 UCB EECS150 D. Culler Fa04 20 m-dimensional cubes in a n- dimensional Boolean space n a 3-cube (three variables): 0-cube, i.e., a single node, yields a term in 3 literals 1-cube, i.e., a line of two nodes, yields a term in 2 literals 2-cube, i.e., a plane of four nodes, yields a term in 1 literal 3-cube, i.e., a cube of eight nodes, yields a constant term "1" n general, m-subcube within an n-cube (m < n) yields a term with n m literals Announcements Homework 2 due Friday Reading: (rest of ch 2) Homework 3 posted 9/16/04 UCB EECS150 D. Culler Fa /16/04 UCB EECS150 D. Culler Fa04 22 Karnaugh maps Flat map of Boolean cube Wrap around at edges Hard to draw and visualize for more than 4 dimensions Virtually impossible for more than 6 dimensions Alternative to truth-tables to help visualize adjacencies Guide to applying the uniting theorem On-set elements with only one variable changing value are adjacent unlike the situation in a linear truth-table ( 8 9/16/04 UCB EECS150 D. Culler Fa04 23 Karnaugh maps Numbering scheme based on Gray code e.g., 00, 01, 11, 10 2 n values of n bits where each differs from next by one bit flip» Hamiltonian circuit through n-cube Only a single bit changes in code for adjacent map cells ; 8 < 9/16/04 UCB EECS150 D. Culler Fa ))=
5 Adjacencies in Karnaugh maps Karnaugh map examples Wrap from first to last column Wrap top row to bottom row F = Cout = f(a,b,c) = Σm(0,4,6,) = 9/16/04 UCB EECS150 D. Culler Fa04 25 # # *== *= -9 ' 9/16/04 UCB EECS150 D. Culler Fa04 26 ** More Karnaugh map examples K-map: 4-variable interactive quiz >%!!&) F(A,B,C,D) = Σm(0,2,3,5,6,,8,10,11,14,15) F = (%!!&)Σ# %!1!2!4& )*== ( # - ' ( %!!&)Σ # %!!8!3& )= *= # # 9 +, %' # ' ' # & 9/16/04 UCB EECS150 D. Culler Fa04 2 9/16/04 UCB EECS150 D. Culler Fa04 28 Karnaugh map: 4-variable example F(A,B,C,D) = Σm(0,2,3,5,6,,8,10,11,14,15) F = *= *== # # 9 +, %' # ' ' # & Karnaugh maps: don t cares f(a,b,c,d) = Σ m(1,3,5,,9) + d(6,12,13) without don't cares» f = = *== 9/16/04 UCB EECS150 D. Culler Fa /16/04 UCB EECS150 D. Culler Fa04 30
6 Karnaugh maps: don t cares Design example: two-bit comparator f(a,b,c,d) = Σ m(1,3,5,,9) + d(6,12,13) f = A'D + B'C'D without don't cares f = with don't cares -9 # 9' # 9,, A: BC D ) E A: BC >: ' 1?9 # 8 9/16/04 UCB EECS150 D. Culler Fa /16/04 UCB EECS150 D. Culler Fa04 32 Design example: two-bit comparator?# A:?# BC?# >: Design example: two-bit comparator ' # # BC ' ' +. A: ) * * BC ) * ** = >: ) * * Canonical PofS vs minimal? )%" &F %" &, +.# # ' 8# 9 A: >: # %GG& 9/16/04 UCB EECS150 D. Culler Fa /16/04 UCB EECS150 D. Culler Fa04 34 Design example: 2x2-bit H H H1 H; H; H1 H H 1?# 1 9/16/04 UCB EECS150 D. Culler Fa04 35 Design example: 2x2-bit multiplier?# H; H;)?# H?# H1 H1) * H ) * * * 9/16/04 UCB EECS150 D. Culler Fa04 36?# H H )
7 Design example: BCD increment by 1 Design example: BCD increment by ; + ; ?# 1 + ; ;)* + 1) * *= + )= = * + ) + + 9/16/04 UCB EECS150 D. Culler Fa04 3 9/16/04 UCB EECS150 D. Culler Fa04 38 Definition of terms for two-level simplification Examples to illustrate terms mplicant Single element of ON-set or DC-set or any group of these elements that can be combined to form a subcube Prime implicant mplicant that can't be combined with another to form a larger subcube Essential prime implicant Prime implicant is essential if it alone covers an element of ON-set Will participate in ALL possible covers of the ON-set DC-set used to form prime implicants but not to make implicant essential Objective: Grow implicant into prime implicants (minimize literals per term) Cover the ON-set with as few prime implicants as possible (minimize number of product terms) 9/16/04 UCB EECS150 D. Culler Fa # # J!!!! # # # J1# 3# # J!!!!! # # # J* * 9/16/04 UCB EECS150 D. Culler Fa04 40 Algorithm for two-level simplification Algorithm: minimum sum-of-products expression from a Karnaugh map Step 1: choose an element of the ON-set Step 2: find "maximal" groupings of 1s and Xs adjacent to that element» consider top/bottom row, left/right column, and corner adjacencies» this forms prime implicants (number of elements always a power of 2) Repeat Steps 1 and 2 to find all prime implicants Step 3: revisit the 1s in the K-map» if covered by single prime implicant, it is essential, and participates in final cover» 1s covered by essential prime implicant do not need to be revisited Step 4: if there remain 1s not covered by essential prime implicants» select the smallest number of prime implicants that cover the remaining 1s 9/16/04 UCB EECS150 D. Culler Fa04 41 Algorithm for two-level simplification (example) 9/16/04 UCB EECS150 D. Culler Fa04 42
8 Summary Boolean Algebra provides framework for logic simplification De Morgans transforms between gate types Uniting to reduce minterms Karnaugh maps provide visual notion of simplifications Algorithm for producing reduced form. Question: are there programmable logic families that are simpler than FPGAs for the canonical forms? 9/16/04 UCB EECS150 D. Culler Fa04 43
for Digital Systems Simplification of logic functions Tajana Simunic Rosing Sources: TSR, Katz, Boriello & Vahid
SE140: omponents and Design Techniques for Digital Systems Simplification of logic functions Tajana Simunic Rosing 1 What we covered thus far: Number representations Where we are now inary, Octal, Hex,
More informationEECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive
EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive March 30, 2010 John Wawrzynek Spring 2010 EECS150 - Lec19-cl1 Page 1 Boolean Algebra I (Representations of Combinational
More informationBoolean cubes EECS150. Mapping truth tables onto cubes. Simplification. The Uniting Theorem. Three variable example
EES5 Section 5 Simplification and State Minimization Fall 2 -cube X oolean cubes Visual technique for indentifying when the uniting theorem can be applied n input variables = n-dimensional "cube" Y 2-cube
More informationCombinational Logic (mostly review!)
ombinational Logic (mostly review!)! Logic functions, truth tables, and switches " NOT, N, OR, NN, NOR, OR,... " Minimal set! xioms and theorems of oolean algebra " Proofs by re-writing " Proofs by perfect
More informationWorking with Combinational Logic. Design example: 2x2-bit multiplier
Working with ombinational Logic Simplification two-level simplification exploiting don t cares algorithm for simplification Logic realization two-level logic and canonical forms realized with NNs and NORs
More informationPossible logic functions of two variables
ombinational logic asic logic oolean algebra, proofs by re-writing, proofs by perfect induction logic functions, truth tables, and switches NOT, ND, OR, NND, NOR, OR,..., minimal set Logic realization
More informationCombinational Logic. Review of Combinational Logic 1
Combinational Logic! Switches -> Boolean algebra! Representation of Boolean functions! Logic circuit elements - logic gates! Regular logic structures! Timing behavior of combinational logic! HDLs and combinational
More informationChapter 2 Combinational logic
Chapter 2 Combinational logic Chapter 2 is very easy. I presume you already took discrete mathemtics. The major part of chapter 2 is boolean algebra. II - Combinational Logic Copyright 24, Gaetano Borriello
More informationCh 2. Combinational Logic. II - Combinational Logic Contemporary Logic Design 1
Ch 2. Combinational Logic II - Combinational Logic Contemporary Logic Design 1 Combinational logic Define The kind of digital system whose output behavior depends only on the current inputs memoryless:
More informationL2: Combinational Logic Design (Construction and Boolean Algebra)
L2: Combinational Logic Design (Construction and Boolean Algebra) Acknowledgements: Lecture material adapted from Chapter 2 of R. Katz, G. Borriello, Contemporary Logic Design (second edition), Pearson
More informationUnit 2 Session - 6 Combinational Logic Circuits
Objectives Unit 2 Session - 6 Combinational Logic Circuits Draw 3- variable and 4- variable Karnaugh maps and use them to simplify Boolean expressions Understand don t Care Conditions Use the Product-of-Sums
More informationThis form sometimes used in logic circuit, example:
Objectives: 1. Deriving of logical expression form truth tables. 2. Logical expression simplification methods: a. Algebraic manipulation. b. Karnaugh map (k-map). 1. Deriving of logical expression from
More informationThe Karnaugh Map COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals
The Karnaugh Map COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Boolean Function Minimization The Karnaugh Map (K-Map) Two, Three,
More informationL2: Combinational Logic Design (Construction and Boolean Algebra)
L2: Combinational Logic Design (Construction and oolean lgebra) cknowledgements: Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University of
More informationCHAPTER III BOOLEAN ALGEBRA
CHAPTER III- CHAPTER III CHAPTER III R.M. Dansereau; v.. CHAPTER III-2 BOOLEAN VALUES INTRODUCTION BOOLEAN VALUES Boolean algebra is a form of algebra that deals with single digit binary values and variables.
More informationENG2410 Digital Design Combinational Logic Circuits
ENG240 Digital Design Combinational Logic Circuits Fall 207 S. Areibi School of Engineering University of Guelph Binary variables Binary Logic Can be 0 or (T or F, low or high) Variables named with single
More information211: Computer Architecture Summer 2016
211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Review: cache hit rate - Project3 - Digital Logic: - truth table => SOP - simplification: Boolean
More informationDigital Logic Design. Combinational Logic
Digital Logic Design Combinational Logic Minterms A product term is a term where literals are ANDed. Example: x y, xz, xyz, A minterm is a product term in which all variables appear exactly once, in normal
More informationEECS Variable Logic Functions
EECS150 Section 1 Introduction to Combinational Logic Fall 2001 2-Variable Logic Functions There are 16 possible functions of 2 input variables: in general, there are 2**(2**n) functions of n inputs X
More informationReview for Test 1 : Ch1 5
Review for Test 1 : Ch1 5 October 5, 2006 Typeset by FoilTEX Positional Numbers 527.46 10 = (5 10 2 )+(2 10 1 )+(7 10 0 )+(4 10 1 )+(6 10 2 ) 527.46 8 = (5 8 2 ) + (2 8 1 ) + (7 8 0 ) + (4 8 1 ) + (6 8
More informationEE40 Lec 15. Logic Synthesis and Sequential Logic Circuits
EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.4-7.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html
More informationCHAPTER III BOOLEAN ALGEBRA
CHAPTER III- CHAPTER III CHAPTER III R.M. Dansereau; v.. CHAPTER III-2 BOOLEAN VALUES INTRODUCTION BOOLEAN VALUES Boolean algebra is a form of algebra that deals with single digit binary values and variables.
More informationLecture A: Logic Design and Gates
Lecture A: Logic Design and Gates Syllabus My office hours 9.15-10.35am T,Th or gchoi@ece.tamu.edu 333G WERC Text: Brown and Vranesic Fundamentals of Digital Logic,» Buy it.. Or borrow it» Other book:
More informationEECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits)
EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) September 5, 2002 John Wawrzynek Fall 2002 EECS150 Lec4-bool1 Page 1, 9/5 9am Outline Review of
More informationCombinational logic. Possible logic functions of two variables. Minimal set of functions. Cost of different logic functions.
Combinational logic Possible logic functions of two variables Logic functions, truth tables, and switches NOT, ND, OR, NND, NOR, OR,... Minimal set xioms and theorems of oolean algebra Proofs by re-writing
More informationOutline. EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) Combinational Logic (CL) Defined
EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) January 30, 2003 John Wawrzynek Outline Review of three representations for combinational logic:
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT2: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 2 Following the slides of Dr. Ahmed H. Madian ذو الحجة 438 ه Winter
More informationLecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University
Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University Original Source: Aby K George, ECE Department, Wayne State University Contents The Map method Two variable
More informationKarnaugh Maps Objectives
Karnaugh Maps Objectives For Karnaugh Maps of up to 5 variables Plot a function from algebraic, minterm or maxterm form Obtain minimum Sum of Products and Product of Sums Understand the relationship between
More informationMC9211 Computer Organization
MC92 Computer Organization Unit : Digital Fundamentals Lesson2 : Boolean Algebra and Simplification (KSB) (MCA) (29-2/ODD) (29 - / A&B) Coverage Lesson2 Introduces the basic postulates of Boolean Algebra
More informationUNIT 4 MINTERM AND MAXTERM EXPANSIONS
UNIT 4 MINTERM AND MAXTERM EXPANSIONS Spring 2 Minterm and Maxterm Expansions 2 Contents Conversion of English sentences to Boolean equations Combinational logic design using a truth table Minterm and
More informationL2: Combinational Logic Design (Construction and Boolean Algebra)
L2: Combinational Logic Design (Construction and oolean lgebra) cknowledgements: Lecture material adapted from Chapter 2 of R. Katz, G. orriello, Contemporary Logic Design (second edition), Pearson Education,
More informationLecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps
EE210: Switching Systems Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps Prof. YingLi Tian Feb. 21/26, 2019 Department of Electrical Engineering The City College of New York
More informationLecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions
EE210: Switching Systems Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions Prof. YingLi Tian Feb. 15, 2018 Department of Electrical Engineering The City College of New York The
More informationGate-Level Minimization
Gate-Level Minimization Dr. Bassem A. Abdullah Computer and Systems Department Lectures Prepared by Dr.Mona Safar, Edited and Lectured by Dr.Bassem A. Abdullah Outline 1. The Map Method 2. Four-variable
More informationDIGITAL ELECTRONICS & it0203 Semester 3
DIGITAL ELECTRONICS & it0203 Semester 3 P.Rajasekar & C.M.T.Karthigeyan Asst.Professor SRM University, Kattankulathur School of Computing, Department of IT 8/22/2011 1 Disclaimer The contents of the slides
More informationChapter 7 Logic Circuits
Chapter 7 Logic Circuits Goal. Advantages of digital technology compared to analog technology. 2. Terminology of Digital Circuits. 3. Convert Numbers between Decimal, Binary and Other forms. 5. Binary
More informationMODULAR CIRCUITS CHAPTER 7
CHAPTER 7 MODULAR CIRCUITS A modular circuit is a digital circuit that performs a specific function or has certain usage. The modular circuits to be introduced in this chapter are decoders, encoders, multiplexers,
More informationCPE100: Digital Logic Design I
Chapter 2 Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu http://www.ee.unlv.edu/~b1morris/cpe100/ CPE100: Digital Logic Design I Section 1004: Dr. Morris Combinational Logic Design Chapter
More informationChapter 2: Princess Sumaya Univ. Computer Engineering Dept.
hapter 2: Princess Sumaya Univ. omputer Engineering Dept. Basic Definitions Binary Operators AND z = x y = x y z=1 if x=1 AND y=1 OR z = x + y z=1 if x=1 OR y=1 NOT z = x = x z=1 if x=0 Boolean Algebra
More informationELC224C. Karnaugh Maps
KARNAUGH MAPS Function Simplification Algebraic Simplification Half Adder Introduction to K-maps How to use K-maps Converting to Minterms Form Prime Implicants and Essential Prime Implicants Example on
More information1. Name the person who developed Boolean algebra
MATHEMATIC CENTER D96 MUNIRKA VILLAGE NEW DELHI 67 & VIKAS PURI NEW DELHI CONTACT FOR COACHING MATHEMATICS FOR TH 2TH NDA DIPLOMA SSC CAT SAT CPT CONTACT FOR ADMISSION GUIDANCE B.TECH BBA BCA, MCA MBA
More informationMidterm1 Review. Jan 24 Armita
Midterm1 Review Jan 24 Armita Outline Boolean Algebra Axioms closure, Identity elements, complements, commutativity, distributivity theorems Associativity, Duality, De Morgan, Consensus theorem Shannon
More informationMinimization techniques
Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NSIK - 4 Minimization techniques By Prof. nand N. Gharu ssistant Professor Computer Department Combinational Logic Circuits Introduction Standard representation
More informationCombinatorial Logic Design Principles
Combinatorial Logic Design Principles ECGR2181 Chapter 4 Notes Logic System Design I 4-1 Boolean algebra a.k.a. switching algebra deals with boolean values -- 0, 1 Positive-logic convention analog voltages
More informationOptimizations and Tradeoffs. Combinational Logic Optimization
Optimizations and Tradeoffs Combinational Logic Optimization Optimization & Tradeoffs Up to this point, we haven t really considered how to optimize our designs. Optimization is the process of transforming
More informationPrinciples of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents
B-1 Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix B: Reduction of Digital Logic B-2 Chapter Contents B.1 Reduction of Combinational Logic and Sequential Logic B.2 Reduction
More informationWeek-I. Combinational Logic & Circuits
Week-I Combinational Logic & Circuits Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other logic operators IC families and
More informationL4: Karnaugh diagrams, two-, and multi-level minimization. Elena Dubrova KTH / ICT / ES
L4: Karnaugh diagrams, two-, and multi-level minimization Elena Dubrova KTH / ICT / ES dubrova@kth.se Combinatorial system a(t) not(a(t)) A combinatorial system has no memory - its output depends therefore
More informationAdvanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011
Problem 2-1 Recall that a minterm is a cube in which every variable appears. A Boolean expression in SOP form is canonical if every cube in the expression has a unique representation in which all of the
More informationEx: Boolean expression for majority function F = A'BC + AB'C + ABC ' + ABC.
Boolean Expression Forms: Sum-of-products (SOP) Write an AND term for each input combination that produces a 1 output. Write the input variable if its value is 1; write its complement otherwise. OR the
More informationSimplifying Logic Circuits with Karnaugh Maps
Simplifying Logic Circuits with Karnaugh Maps The circuit at the top right is the logic equivalent of the Boolean expression: f = abc + abc + abc Now, as we have seen, this expression can be simplified
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal
More informationChap 2. Combinational Logic Circuits
Overview 2 Chap 2. Combinational Logic Circuits Spring 24 Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard Forms Part 2 Circuit Optimization Two-Level Optimization
More informationBoolean Algebra and Logic Simplification
S302 Digital Logic Design Boolean Algebra and Logic Simplification Boolean Analysis of Logic ircuits, evaluating of Boolean expressions, representing the operation of Logic circuits and Boolean expressions
More informationSimplification of Boolean Functions. Dept. of CSE, IEM, Kolkata
Simplification of Boolean Functions Dept. of CSE, IEM, Kolkata 1 Simplification of Boolean Functions: An implementation of a Boolean Function requires the use of logic gates. A smaller number of gates,
More informationCHAPTER1: Digital Logic Circuits Combination Circuits
CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits Combination Circuits 1 PRIMITIVE LOGIC GATES Each of our basic operations can be implemented in hardware using a primitive logic gate.
More informationCS 121 Digital Logic Design. Chapter 2. Teacher Assistant. Hanin Abdulrahman
CS 121 Digital Logic Design Chapter 2 Teacher Assistant Hanin Abdulrahman 1 2 Outline 2.2 Basic Definitions 2.3 Axiomatic Definition of Boolean Algebra. 2.4 Basic Theorems and Properties 2.5 Boolean Functions
More informationUNIT 5 KARNAUGH MAPS Spring 2011
UNIT 5 KRNUGH MPS Spring 2 Karnaugh Maps 2 Contents Minimum forms of switching functions Two- and three-variable Four-variable Determination of minimum expressions using essential prime implicants Five-variable
More informationCDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012
CDA 3200 Digital Systems Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 Outline Combinational Logic Design Using a Truth Table Minterm and Maxterm Expansions General Minterm and
More informationECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 2 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 2 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering Boolean Algebra Boolean Algebra A Boolean algebra is defined with: A set of
More informationII. COMBINATIONAL LOGIC DESIGN. - algebra defined on a set of 2 elements, {0, 1}, with binary operators multiply (AND), add (OR), and invert (NOT):
ENGI 386 Digital Logic II. COMBINATIONAL LOGIC DESIGN Combinational Logic output of digital system is only dependent on current inputs (i.e., no memory) (a) Boolean Algebra - developed by George Boole
More informationCSE 140 Midterm I - Solution
CSE 140 Midterm I - Solution 1. Answer the following questions given the logic circuit below. (15 points) a. (5 points) How many CMOS transistors does the given (unsimplified) circuit have. b. (6 points)
More informationKarnaugh Maps ف ر آ ا د : ا ا ب ا م آ ه ا ن ر ا
Karnaugh Maps مخطط آارنوف اعداد:محمد اسماعيل آلية علوم الحاسوب جامعة امدرمان الاهلية الاهداء الي آل من يسلك طريق العلم والمعرفة في هذا المجال Venn Diagrams Venn diagram to represent the space of minterms.
More informationDigital Circuit And Logic Design I. Lecture 4
Digital Circuit And Logic Design I Lecture 4 Outline Combinational Logic Design Principles (2) 1. Combinational-circuit minimization 2. Karnaugh maps 3. Quine-McCluskey procedure Panupong Sornkhom, 2005/2
More informationLOGIC GATES. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Eperiment and Design of Electronics LOGIC GATES Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Boolean algebra Logic gates Karnaugh maps
More informationLogic Design. Chapter 2: Introduction to Logic Circuits
Logic Design Chapter 2: Introduction to Logic Circuits Introduction Logic circuits perform operation on digital signal Digital signal: signal values are restricted to a few discrete values Binary logic
More informationWorking with combinational logic
Working with combinational logic Simplification two-level simplification exploiting don t cares algorithm for simplification Logic realization two-level logic and canonical forms realized with NNs and
More informationDigital Logic (2) Boolean Algebra
Digital Logic (2) Boolean Algebra Boolean algebra is the mathematics of digital systems. It was developed in 1850 s by George Boole. We will use Boolean algebra to minimize logic expressions. Karnaugh
More informationCs302 Quiz for MID TERM Exam Solved
Question # 1 of 10 ( Start time: 01:30:33 PM ) Total Marks: 1 Caveman used a number system that has distinct shapes: 4 5 6 7 Question # 2 of 10 ( Start time: 01:31:25 PM ) Total Marks: 1 TTL based devices
More informationBoolean Algebra, Gates and Circuits
Boolean Algebra, Gates and Circuits Kasper Brink November 21, 2017 (Images taken from Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc.) Outline Last week: Von
More informationCPE100: Digital Logic Design I
Chapter 2 Professor Brendan Morris, SEB 326, brendan.morris@unlv.edu http://www.ee.unlv.edu/~bmorris/cpe/ CPE: Digital Logic Design I Section 4: Dr. Morris Combinational Logic Design Chapter 2 Chapter
More informationSystems I: Computer Organization and Architecture
Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept
More informationNumber System conversions
Number System conversions Number Systems The system used to count discrete units is called number system. There are four systems of arithmetic which are often used in digital electronics. Decimal Number
More informationLecture 2 Review on Digital Logic (Part 1)
Lecture 2 Review on Digital Logic (Part 1) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ Grading Engagement 5% Review Quiz 10% Homework 10% Labs 40%
More informationCHAPTER 12 Boolean Algebra
318 Chapter 12 Boolean Algebra CHAPTER 12 Boolean Algebra SECTION 12.1 Boolean Functions 2. a) Since x 1 = x, the only solution is x = 0. b) Since 0 + 0 = 0 and 1 + 1 = 1, the only solution is x = 0. c)
More informationPart 1: Digital Logic and Gates. Analog vs. Digital waveforms. The digital advantage. In real life...
Part 1: Digital Logic and Gates Analog vs Digital waveforms An analog signal assumes a continuous range of values: v(t) ANALOG A digital signal assumes discrete (isolated, separate) values Usually there
More information9.1. Unit 9. Implementing Combinational Functions with Karnaugh Maps or Memories
. Unit Implementing Combinational Functions with Karnaugh Maps or Memories . Outcomes I can use Karnaugh maps to synthesize combinational functions with several outputs I can determine the appropriate
More informationKarnaugh Map & Boolean Expression Simplification
Karnaugh Map & Boolean Expression Simplification Mapping a Standard POS Expression For a Standard POS expression, a 0 is placed in the cell corresponding to the product term (maxterm) present in the expression.
More informationCHAPTER 7. Exercises 17/ / /2 2 0
CHAPTER 7 Exercises E7. (a) For the whole part, we have: Quotient Remainders 23/2 /2 5 5/2 2 2/2 0 /2 0 Reading the remainders in reverse order, we obtain: 23 0 = 0 2 For the fractional part we have 2
More informationTotal Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18
University of Waterloo Department of Electrical & Computer Engineering E&CE 223 Digital Circuits and Systems Midterm Examination Instructor: M. Sachdev October 23rd, 2007 Total Time = 90 Minutes, Total
More informationLogic Design I (17.341) Fall Lecture Outline
Logic Design I (17.341) Fall 2011 Lecture Outline Class # 06 October 24, 2011 Dohn Bowden 1 Today s Lecture Administrative Main Logic Topic Homework 2 Course Admin 3 Administrative Admin for tonight Syllabus
More informationKarnaugh Maps (K-Maps)
Karnaugh Maps (K-Maps) Boolean expressions can be minimized by combining terms P + P = P K-maps minimize equations graphically Put terms to combine close to one another B C C B B C BC BC BC BC BC BC BC
More informationCombinational Logic Design Combinational Functions and Circuits
Combinational Logic Design Combinational Functions and Circuits Overview Combinational Circuits Design Procedure Generic Example Example with don t cares: BCD-to-SevenSegment converter Binary Decoders
More informationENGG 1203 Tutorial - 2 Recall Lab 2 - e.g. 4 input XOR. Parity checking (for interest) Recall : Simplification methods. Recall : Time Delay
ENGG 23 Tutorial - 2 Recall Lab 2 - e.g. 4 input XOR Parity checking (for interest) Parity bit Parity checking Error detection, eg. Data can be Corrupted Even parity total number of s is even Odd parity
More informationCombinational Logic Fundamentals
Topic 3: Combinational Logic Fundamentals In this note we will study combinational logic, which is the part of digital logic that uses Boolean algebra. All the concepts presented in combinational logic
More informationE&CE 223 Digital Circuits & Systems. Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev
E&CE 223 Digital Circuits & Systems Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev 4 of 92 Section 2: Boolean Algebra & Logic Gates Major topics Boolean algebra NAND & NOR gates Boolean
More informationCombinational Logic. By : Ali Mustafa
Combinational Logic By : Ali Mustafa Contents Adder Subtractor Multiplier Comparator Decoder Encoder Multiplexer How to Analyze any combinational circuit like this? Analysis Procedure To obtain the output
More informationLecture 2. Notes. Notes. Notes. Boolean algebra and optimizing logic functions. BTF Electronics Fundamentals August 2014
Lecture 2 Electronics ndreas Electronics oolean algebra and optimizing logic functions TF322 - Electronics Fundamentals ugust 24 Exercise ndreas ern University of pplied Sciences Rev. 946f32 2. of oolean
More informationChapter 2. Boolean Algebra and Logic Gates
Chapter 2 Boolean Algebra and Logic Gates Basic Definitions A binary operator defined on a set S of elements is a rule that assigns, to each pair of elements from S, a unique element from S. The most common
More informationDigital Logic Circuits - Switching Algebra - Combinational Circuits -
Digital Logic Circuits - Switching Algebra - Combinational Circuits - Dr. Voicu Groza SITE Hall, Room 57 562 58 ext. 259 Groza@EECS.uOttawa.ca Outline Logic Functions Boolean Algebra Logic Functions Minimization
More informationUnit 6. Quine-McClusky Method. Unit 6 1
Unit 6 Quine-McClusky Method Unit 6 1 Outline Determination of prime implicants The prime implicant chart Petrick s method Simplification of incompletely specified functions Unit 6 2 Overview (1/2) A systematic
More informationAdministrative Notes. Chapter 2 <9>
Administrative Notes Note: New homework instructions starting with HW03 Homework is due at the beginning of class Homework must be organized, legible (messy is not), and stapled to be graded Chapter 2
More informationCHAPTER 5 KARNAUGH MAPS
CHAPTER 5 1/36 KARNAUGH MAPS This chapter in the book includes: Objectives Study Guide 5.1 Minimum Forms of Switching Functions 5.2 Two- and Three-Variable Karnaugh Maps 5.3 Four-Variable Karnaugh Maps
More informationEEE130 Digital Electronics I Lecture #4
EEE130 Digital Electronics I Lecture #4 - Boolean Algebra and Logic Simplification - By Dr. Shahrel A. Suandi Topics to be discussed 4-1 Boolean Operations and Expressions 4-2 Laws and Rules of Boolean
More informationCombinational Logic Circuits Part II -Theoretical Foundations
Combinational Logic Circuits Part II -Theoretical Foundations Overview Boolean Algebra Basic Logic Operations Basic Identities Basic Principles, Properties, and Theorems Boolean Function and Representations
More informationPropositional Logic. Logical Expressions. Logic Minimization. CNF and DNF. Algebraic Laws for Logical Expressions CSC 173
Propositional Logic CSC 17 Propositional logic mathematical model (or algebra) for reasoning about the truth of logical expressions (propositions) Logical expressions propositional variables or logical
More informationWEEK 2.1 BOOLEAN ALGEBRA
WEEK 2.1 BOOLEAN ALGEBRA 1 Boolean Algebra Boolean algebra was introduced in 1854 by George Boole and in 1938 was shown by C. E. Shannon to be useful for manipulating Boolean logic functions. The postulates
More informationStandard Expression Forms
ThisLecture will cover the following points: Canonical and Standard Forms MinTerms and MaxTerms Digital Logic Families 24 March 2010 Standard Expression Forms Two standard (canonical) expression forms
More informationCSE 140: Components and Design Techniques for Digital Systems
Lecture 4: Four Input K-Maps CSE 4: Components and Design Techniques for Digital Systems CK Cheng Dept. of Computer Science and Engineering University of California, San Diego Outlines Boolean Algebra
More information