DHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN

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1 DHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I : BOOLEAN ALGEBRA AND LOGIC GATES PART - A (2 MARKS) Number System 1. Find the decimal equivalent of (346)7. (May 2004) (346)7 = (3x7 2 ) + (4x7 1 ) + (6x7 0 ) = (181)10. The Decimal equivalent of (346)7 = (181)10 2. Convert the following number from one base to another (65.342)8 = ( ) 7. (May 2008) Convert the given number to decimal (65.342)8 = (6x8 1 ) + (5x8 0 ) + (3x8-1 ) + (4x8-2 ) + (2x8-3 ) = ( )10 Now, convert this number to base 7. Integer part: = (104)7 Fractional part x 7 = x 7 = x 7 = x 7 = = (0.3042)7 The Base 7 value of (65.342)8 = ( ) 7

2 3. Convert (231.3)4 to base 7. (May 2005) Convert the given number to decimal, (231.3)4 = (2x4 2 ) + (3x4 1 ) + (1x4 0 ) + (3x4-1 ) = = (45.75)10 Now, convert this number to base 7. Integer part: = (63)7 Fractional part: 0.75 x 7 = x 7 = x 7 = x 7 = = (0.5151)7 The base 7 value of (231.3)4 = ( )7 4. Convert the following numbers from one base to another (Nov 2006) a) (354.52) 6 = ( ) 10 b) (100)10 = ( ) 16. (a) (354.52) 6 = (3x6 2 ) + (5x6 1 ) + (4x6 0 ) + (5x6-1 ) + (2x6-2 ) = = ( ) 10 (354.52) 6 = ( ) 10 (b) (100)10 = (64)16 (100)10 = (64)16.

3 5. A hexadecimal counter capable of counting up to (10,000)10 is to be constructed. What is the minimum number of hexadecimal digits that the counter must have? (May 2004) Decimal value to be counted by the hexadecimal counter = (10,000)10 Hexadecimal value = (2710)16 So the minimum number of hexadecimal digits = 4 6. Convert the ( )10 to Octal. (Apr 2010) Integer part: Remainder = = = 0 2 = (231)8 Fractional part: Integer = = = = = (0.4065)8 The Octal value of ( )10 = ( )8 7. Perform the following code conversions ( )16 (?) 2 (?) 8 (?) 10. (Nov 2011) 1. Hexadecimal to binary: (each Digit represent by 4 bits) ( )16 = ( )2 2. Hexadecimal to octal: Step 1: Convert Hexadecimal to binary: ( )16 = ( )2

4 Step 2: Convert Binary to Octal ( )2 (Grouping into 3 bits) (Leave the left and right most Zeros) = ( )8 ( )16 = ( )8 3. Hexadecimal to decimal: ( )16 = ( ) = = ( )10 8. List the different number systems. The different number systems are i) Binary Number system ii) Octal Number system iii) Decimal Number system iv) Hexadecimal Number system 9. Express the following in decimal: a.) ( )2, b.) (16.5)16, c.) (26.24)8, d.) (FAFA.B) 16, e.) ( )2. (a) ( )2 = (1x2 4 ) + (0x2 3 ) + (1x2 2 ) + (1x2 1 ) + (0x2 0 ) + (0x2-1 ) + (1x2-2 ) + (0x2-3 ) + (1x2-4 ) = = ( )10 The decimal value of ( )2 = ( )10 (b) (16.5)16 = (1x16 1 ) + (6x16 0 ) + (5x16-1 ) = (5 (0.0615)) = ( )10 The hexadecimal value of (16.5)16 = ( )10

5 (c) (26.24)8 = (2x8 1 ) + (6x8 0 ) + (2x8-1 ) + (4x8-2 ) = /8 + 4/64 = ( )10 The octal value of (26.24)8 = ( )10 (d) (FAFA.B) 16 = (Fx16 3 ) + (Ax16 2 ) + (Fx16 1 ) + (Ax16 0 ) + (Bx16-1 ) = (15x16 3 ) + (10x16 2 ) + (15x16 1 ) + (10x16 0 ) + (11x16-1 ) = (64, )10 The decimal value of (FAFA.B) 16 = (64, )10 (e) ( )2 = (1x2 3 ) + (0x2 2 ) + (1x2 1 ) + (0x2 0 ) + (1x2-1 ) + (0x2-2 ) + (1x2-3 ) + (0x2-4 ) = = (10.625)10 The decimal value of ( )2 = (10.625) Convert the following binary numbers to its decimal and hexadecimal equivalent: a) b) Explain why the decimal answer in (b) is 8 times that of (a). To convert from binary to hexadecimal: Each 4 binary digits are equal to 1 hexadecimal digit: a) ( )2 = (1.D0)16 b) ( )2 = (E.8) 16 To convert from binary to decimal: a) ( )2 = (1x2 0 ) + (1x2-1 ) + (1x2-2 ) + (0x2-3 ) + (1x2-4 ) + (0x2-5 ) = (1) + ( ) = (1.8125)10 b) ( ) 2 = (1x2 3 ) + (1x2 2 ) + (1x2 1 ) + (0x2 0 ) + (1x2-1 ) + (0x2-2 ) = (8+4+2) + (0.5) = (14.5) 10 The decimal answer in (b) is 8 times that of (a) because the binary number in (b) is the same as that in (a) except that the point is shifted to the right 3 digits and this means that it is multiplied by 2 3.

6 11. Convert (9B2.1A) H to its decimal equivalent. (9B2.1A) H = (9 x 16 2 ) + (B x 16 1 ) + (2 x 16 0 ) + (1 x 16-1 ) + (A (10) x 16-2 ) = = (2482.1)10 The decimal Equivalent of (9B2.1A) H = (2482.1) Convert decimal numbers to its octal equivalent. Integer x 8 = x 8 = = (0.51) 8 The octal equivalent of ( )10 = (0.51) 8 Binary Codes 13. Write the applications of gray code. (Apr 2011) The applications of gray code are i. Position encoders ii. Towers of Hanoi iii. Genetic algorithms iv. Karnaugh maps v. Error correction vi. Communication between clock domains 14. What are the different ways to represent a negative numbers? (Nov 2006) The different ways of representing the negative numbers are i) In ordinary arithmetic, the negative sign is indicated by a minus sign. ii) In signed magnitude representation, in which MSB is indicated as 0 to represent negative number. iii) In signed s 1 complement representation, in which the negative number is indicated by its s 1 complement. iv) In signed s 2 complement representation, in which the negative number is indicated by its s 2 complement. 15. What are error detecting codes? (Nov 2007) When the digital information in the binary form is transmitted from one circuit or system to another circuit or system an error may occur. To maintain the data integrity between transmitter and receiver, extra bit or more than one bit is added in the data. The data along with the extra bit/bits forms the code. Codes which allow only error detection are called error detecting codes.

7 16. What are the advantages of gray codes over binary number sequence? (May 2007) The advantage of gray codes over the binary number is that only one bit in the code group changes when going from one number to the next. The gray code is used in applications where the normal sequence of binary number may produce an error or ambiguity during the transition from one number to next. 17. State the different type of binary codes. The various types of binary codes are, a) BCD code (Binary Coded decimal). b) Self-complementing code. c) The excess-3 (X s-3) code. d) Gray code. e) Binary weighted code. f) Alphanumeric code. g) The ASCII code. h) Extended binary-coded decimal interchange code (EBCDIC). i) Error-detecting and error-correcting code. j) Hamming code. 18. Write the steps involved in Gray to binary conversion. The steps involved in Gray to binary conversion are 1. The MSB of the binary number is the same as the MSB of the gray code number. So write it down. 2. To obtain the next binary digit, perform an exclusive OR operation between the bit just written down and the next gray code bit. Write down the result. Example: The gray code is Complements

8 19. What is the range of values that can be represented using n-bit s 2 complement form of representation? What is the corresponding range with n-bit s 1 complement form? (May 2006) i) The given number N in the base 2 having n digits. The s 2 complement of N is defined as follows. digits. s 2 complement of N= + (2 n-1-1) to (2 n-1 ), Where, n is number of ii) The given number N in the base 2 having n digits. The s 1 complement of N is defined as follows. s 1 complement of N= + (2 n-1-1) to (2 n-1-1), Where n= given number or digit 20. Represent the decimal numbers (-200) and (+200) using s 2 compliment binary form. The Binary value of (+200) = ( )2 Add sign bit +200 = (-200) = (+200) of complement of s 1 complement = add complement Perform subtraction using s 1 complement (11010)2 (10000)2. (Nov 2009) (01111)2 = (10000)2 of s 1 complement (10000)2) of s 1 ) complement (add carry bit to result) The s 1 complement subtraction of (11010)2 (10000)2 = (01010)2

9 22. Perform s 9 and s 10 compliment subtraction between 18 and 24. (Nov 2009) Using s 9 complement representation Step 1: Find s 9 complement of 24 =99 24 = 75 Step 2: Add 18 and s 9 complement of No carry, so result is negative and it is in s 9 complement form Step 3: Find s 9 complement of result 99-93= 6 Ans: = -6 Using s 10 complement representation Step 1: Find s 10 complement of 24 = s 9 ) complement of ) = = 76 Step 2: Add 18 and s 10 complement of No carry, so result is negative and it is in s 9 complement form Step 3: Find s 10 complement of result ((99-94) + 1) = 6 Ans: = Find the complements for the following functions (NOV 2007) a) F1= xy + x y, b) F2= (xy + y z + xz) x. (a) F1= + xy x y x y) + xy ) = F1

10 ( y x ). ( xy ) = ( x+y ) (x +y) = yy yx+ + y x x x+ = F1 = + y x xy. (b) F2= (xy + y z + xz) x. x) z + x z) y ((x y + = F2 x + z) z + x y (x y + = x + [ z) (x. ( z y ). y) [(x = = x )] + ( y (y + ( z x ) + [( z + x [y.y=0] x + [( z + x ( ( z y z x +y x )] = x + z z y + z z x + z y x + z y x + z x x + y x = x = x +y x + z x y + z x y + z x + z y + z x +x] x =,[x.x] x = [x [1 = x +x] x + z y (y + + y ) z x + z x +y x = x + z y + (1) z x + z x +y x = x + z y + z x +y x = z y + z x + x +y x = = x (y + 1) + x z+ y z [y+1= 1] = x (1 + z) + y z [y+1= 1] z y + x = F2 24. Obtain the complement of f = wx y + + xy wxz using De Morgan s theorem. (May 2006) f = wx y + + xy wxz ( wxz + xy (wx y + = f ( wxz ) ( xy ) ( y wx ) = ( z + x + w ) (y + x ) ( y (w +x+ = ( z + x + w ) ( yy + y x xy+ + xx w y+ + x w ) = ( z + x + w ) ( y x w y+ xy+ + x w ) = + z. x w + x. y x + x xy. + x x +w y.. x w + w. y x + w xy. + w w y. + w. x w = z. y x + z xy. + z w y. z y x + xyz + yz w + z x w + y x w x y x w + y x w w xy+ w y+ + x w = z y x + xyz + yz w + z x w + y x w x y+ + y x w w xy+ w y+ + x w = xyz +( z + 1 ) y x +( z w y( +1 +x +( z +y + y +1 ) x w =

11 xyz +( 1 ) y x w y(1)+ +( 1 ) x w = xyz + y x w y+ + x w = f 25. State the different types of number complements. The different types of number complements are i) r s Complement (or) Radix complement ii) (r-1) s Complement(or) Diminished Radix complement 26. Obtain the s 1 and s 2 complement of the following binary numbers: a) b) c) d) e) versa. s 1 complement: Change every 1 to 0 and vice LSB. s 2 complement: Change every 1 to 0 and vice versa, then add (1) to the a) ( )2 complement: s 1 complement: s 2 (+) ( ) b) ( )2 complement: s 1 complement: s 2 (+) ( ) c) ( )2 complement: s 1

12 complement: s 2 (+) ( ) d) ( )2 complement: s 1 complement: s 2 (+) ( ) e) ( )2 complement: s 1 complement: s 2 (+) ( ) Find the s 2 complement of ( ) 2. s 1 Complement (+) complement. s 2 0)2 - (

13 28. Given two binary numbers X = and Y = , perform subtraction X -Y and Y - X using s 1 complements. a) X - Y = X = Y) s 1 ) complement of Discard end carry = + 1 Answer: X - Y = ( )2 b) Y - X = Y = X) s 1 ) complement of There is no end carry. Answer is Y - X = - s 1 ) complement of ) = - ( )2 Boolean Theorems 29. Simplify the following Boolean functions to a minimum number of literals: (May 2010),( y a) (x + y) (x + b) x y + x z + y z. ( y a) (x+ y) (x+ y y x+ y + y = x.x+ x 0] = y x y+ 0 [x. x= x]; [ y. + y = x+ x = x (1+ + y y) = x (1) = x [1+y= 1]. b) x y + x z + y z. = x y + x z + y z (1) 1] = x [x+ ( x z + y z (x+ x = x y + = x y + x z + xyz + x y z Re-arranging,

14 = x y + xyz + x z x + y z = x y (1+ z) + x z (1+y) = x y (1) + x z (1) [1+y= 1]; [1+z= 1] = x y+ x z. 30. Show that A +. A B = A + B using the theorems of Boolean algebra. (Nov 2005) A+A.B = A+ AB + A B [A+AB = A] ( A = A+ B (A+ 1] = A = A+ B (1) [A+ = A+ B 31. Find the complement of the functions F1 = yz x + x y z and F2 = x z y ) + yz) by applying De- Morgan s theorem. (Nov 2012) F1 = yz x + x y z ( z y x + yz x ) = F1 ( z y x ) ( yz x ) = ( z + + z) (x + y y (x + = F2 = x z y ) + yz) [( yz + z y ) x] = F2 ( yz + z y ) + x = ( yz ) ( z y ) + x = ( z + y ) (y + z) + x = 32. Simplify the following Boolean functions (May 2007) a) x x ) + y), b) xy + x z + yz. (a) x (x +y) = + xx xy 0] = x = xy. [x. (b) xy + x z + yz ( x x z + yz( x+ = xy + = xy + x z + xyz + x yz = xy + xyz + x z +x yz = xy (1+ z) + x z (1+y) [1+y= 1]

15 = xy+ x z. 33. State and prove the consensus theorem. (Nov 2010) Consensus theorem states: XY + X Z + YZ = XY + X Z The YZ term is called the consensus term and is redundant. The consensus term is formed from a PAIR OF TERMS in which a variable (X) and its complement ( X ) are present; the consensus term is formed by multiplying the two terms and leaving out the selected variable and its complement. The consensus of XY, X Z is YZ. Consensus Theorem Proof: XY + X Z + YZ = XY + X Z + (X + ( X YZ = XY + X Z + XYZ + X YZ = (XY + XYZ) + (X Z + X YZ) = XY (1 + Z) + X Z (1 + Y) = XY + X Z 34. Simplify the following Boolean expression to a minimum number of literals: (May 2009) CD B A A B D+ + D C A + B A F = F CD B A A B D+ + D C A + B A = CD B A + D C A (D+1) + B A = = B A (1) + + D C A CD B A [1+ x = 1] CD B A + D C A + B A = D C A + CD B A + B A = D C A + ( 1+CD ) B A = = B A (1) + D C A [1+ x = 1] D C A + B A = ( D C + B ) A = 35. What are the basic properties of Boolean algebra? The basic properties of Boolean algebra are i. Commutative property ii. iii. Associative property Distributive property

16 36. State the associative property of Boolean algebra. The associative property of Boolean algebra states that the OR ing of several Variables results in the same regardless of the grouping of the variables. The associative property is stated as follows: A+ (B+C) = (A+B) +C 37. State the commutative property of Boolean algebra. The commutative property states that the order in which the variables are ORed makes no difference. The commutative property is: (A+B) = (B+A) 38. State the distributive property of Boolean algebra. The distributive property states that ANDing several variables and ORing the result with a single variable is equivalent to ORing the single variable with each of the several variables and then ANDing the sums. The distributive property is: A+BC= (A+B) (A+C) 39. State the De- Morgan s theorem. De - Morgan suggested two theorems that form important part of Boolean algebra. They are, 1) The complement of a product is equal to the sum of the complements. B + A = ( A.B ) 2) The complement of a sum term is equal to the product of the complements. B. A = ( A+B ) 40. State the absorption law of Boolean algebra. The absorption law of Boolean algebra is 1) A+AB=A, 2) A (A+B) =A. 41. Define Duality property Duality property states that, starting with a Boolean relation, you can derive another Boolean relation by 1) Changing each OR sign to an AND sign 2) Changing each AND sign to an OR sign 3) Complementing any 0 or 1 appearing in the expression 0 = A 1 is A. = A Example: A+

17 . [ D ( C ( AB ))] 42. Simplify the following using De - Morgan s theorem D] ( C [((AB) L. H. S. = [ B + A = [(AB) D + ( C ((AB) = D C + (AB) = D C + ( B + A ) = 43. What are the methods adopted to reduce Boolean function? The methods are i) Karnaugh map ii) Tabular method or Quine Mc-Cluskey method iii) Variable entered map technique. Karnaugh Map 44. Find the minterms of the function xy+yz+xy z. (Nov 2008) xy+ yz+ xy z = xy(z + ( z + yz(x ( x + + xy z = xyz + xyz + xyz + x yz + xy z = xyz + + xyz x yz + xy z =m7+ m6+m4+m2 = Σm (2, 4, 6, 7) 45. Simplify the following Boolean function using Karnaugh map method (May 2009) F (A, B, C, D) = Σm (1, 5, 9, 12, 13, 15) ABC C D+ Therefore, F= ABD+

18 46. What are the drawbacks of Karnaugh map? (Nov 2007) The drawbacks of the K-map method are i) Generally it is limited to six variable maps (i.e.) more than six variable involving expressions are not reduced. ii) The map method is restricted in its capability since they are useful for simplifying only Boolean expression represented in standard form. iii) It is not suitable for computer reduction. iv) Care must be taken to fill in every cell with the relevant entry, such as a 0, 1 (or) don t care terms. 47. What is a minterm? (May 2008) Each individual term in standard SOP form is called minterm. 48. Convert the following function into sum of product form (AB + C) (B + C D). (May 2008) (AB+C)(B+C D) = (AB.B+ B.C+ AB.C D+ C.C D) 0] = C.C ] ABC D [B. B= 1] = AB+ BC+ AND each product term having missing literals, by ORing the literals and its complement = AB (C+ ( C (D+ ( D + BC (A+ ( A (D+ ( D + ABC D = (ABC+ ( ABC (D+ ( D + (ABC+ A BC) (D+ ( D + ABC D = ABCD+ + ABCD ABC D+ + D ABC ABCD+ + ABCD A BCD+ + BCD A ABC D. BCD A A BCD+ + D ABC ABC D+ + ABCD = ABCD+ = m15+ m14+ m13+ m12+ m7+ m6 F(A,B,C,D) = Σm( 6,7, 12,13,14,15) 49. Define Maxterm Each individual term in standard POS form is called maxterms.. ABC + +A BC +A B C C B A 50. Find the minterms of the logical expression Y= ABC A BC + A B C + + C B A Y = = m0 + m1 +m3 +m6 = Σm (0, 1, 3, 6)

19 51. Convert the given expression in canonical SOP form Y = AC + AB + BC. Y = AC + AB + BC = AC (B + ( B + AB (C + ( C + (A + ( A BC = ABC + ABC + AB C + C AB + ABC + ABC + ABC = ABC + ABC +AB C + C AB [A + A =1] = m7 + m6 +m5 +m4 = Σm (4, 5, 6, 7) 52. What is a Karnaugh map? A Karnaugh map or k map is a pictorial form of truth table, in which the map diagram is made up of squares, with each squares representing one minterm of the function. Logic gates 53. Distinguish between positive logic and negative logic. ` (Nov 2003) In binary logic, two voltage levels represent the two binary digits, 1 and 0. If the higher of the two voltages represents a 1 and the lower voltage represents a 0, the system is called positive logic system. On the other hand, if the lower voltage represents a 1 and the higher voltage represents a 0, then it is a negative logic system. 54. How will you use a 4 input NOR gate as a 2 input NOR gate? (May 2003) By connecting unused inputs to logic 0, we can use 4-input NOR gate as a 2 input NOR gate. 55. How will you use a 4 input NAND gate as a 2 input NAND gate? (Nov 2002) By connecting unused inputs to logic 1, we can use 4-input NAND gate as a 2 input NAND gate. 56. What is meant by a functionally complete set of logic gates? (May 2005) A set of logic gates by which we can implement any logic function is called functionally complete set of logic gates. 57. Show that a positive logic NAND gate is the same as a negative logic NOR gate. (May 2003, Nov 2004).B) Logic expression for NAND gate is, Y= (A Y.B) (A = B + A = Y= A + B is the logic expression for negative logic NOR gate.

20 58. What happens when all the gates in a two level AND-OR gate networks are replaced by NOR gate? (May 2004, Nov 2004) The output will change. We will get complemented output when all applied inputs are complemented. 59. Realize OR gate using NAND gate. (Nov 2005, 2012) OR gate using AND gate 60. Write the truth tables of logical AND and XOR gates. (Apr 2011) XOR TRUTH TABLE AND TRUTH TABLE A B A B A.B What is a Logic gate? Logic gates are the basic elements that make up a digital system. The electronic gate is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical function.

21 PART B (16 MARKS) 1. Simplify the following Boolean expressions to a minimum number of literals: (Nov/Dec 2011) a. b. c. XY + YZ + X Z d. A + ABD + AB + + B e. BD + BC + A 2. Simplify the following using K-map to obtain a minimum POS expression: F= (A + B +C+D) (A+B +C+D) (A+B+C+D ) (A+B+C +D ) (A +B+C +D ) (A+B+C +D) 3. a) Simplify F (A, B, C, D) = m (0, 1, 2, 5, 8, 9, 10) in sum of products and product of sums using K-map. b) Write notes on negative and positive logic. (Nov/Dec 2012) 4. a) Minimize the following expression using K-Map : (Apr/May 2011) Y= A'BC'D' + A'BC'D + ABC'D' + AB'C'D +A'B'CD' b) State and prove De Morgan s theorems 5. Minimize the following expression using Quine McCluskey Tabulation method : (Apr/May 2012) Y= A'BC'D' + A'BC'D + ABC'D' + AB'C'D +A'B'CD' 6. Simplify the following expression F (A, B, C, D)= m (1, 4, 6, 7, 8, 9, 10, 11, 15) using Quine-McClusky method. (Nov/Dec 2012)

22 UNIT II : COMBINATIONAL LOGIC PART A (2 MARKS) Design of combinational logic 1. Define Combinational circuit. (May 2009) A combinational circuit consists of logic gates whose outputs at anytime are determined directly from the present combination of inputs, without regard to previous inputs. 2. What are the differences between sequential and combinational logic circuits? (Nov 2004, Nov 2007, May 2010) Adder 3. What is a half-adder? (Nov 2009) A half-adder is a combinational circuit that can be used to add two bits. It has two inputs that represent the two bits to be added and two outputs, with one producing the SUM output and the other producing the CARRY. 4. Draw the logic diagram of a half-adder. (Nov 2005, 2009)

23 5. What is a full adder? (May 2007) A full adder is a combinational circuit that forms the arithmetic sum of three input bits. It consists of 3 inputs and 2 outputs. Two of the input variables, represent the significant bits to be added. The third input represents the carry from previous lower significant position. The block diagram of full adder is given by, 6. Write the truth table for a half adder. Inputs Outputs A B Sum (S) Carry (C) From the truth table of a half adder derive the logic equation. Inputs Outputs A B Sum (S) Carry (C)

24 8. Draw the circuit of a full-adder. Subtractor 9. Write the truth table for a full-subtractor. (Nov 2004) Inputs Outputs A B Bin D Bo What is a half-subtractor?

25 11. Derive the logic equation of a half-subtractor. 12. Draw the circuit of a half-subtractor. Code convertors 13. What is the need for code conversion? (May 2009) The two systems working with different binary codes are to be synchronized in operation, and then we need digital circuit which converts one system of codes to the other. The process of conversion is referred to as code conversion. 14. Draw a 4-bit binary to gray code converter circuit and discuss its operation. (May 2006) The gray code is often used in digital systems because it has the advantage that only bit in the numerical representation changes between successive.

26 15. What is a code converter? Code Converter is a circuit that makes the two systems compatible even though each uses a different binary code. It is a device that converts binary signals from a source code to its output code. One example is a BCD to Xs3 converter. Basic of HDL 16. What is logic synthesis in HDL? (Nov 2006, Apr 2012, Nov 2007) Logic Synthesis is the automatic process of transforming a high level language description such as HDL into an optimized net list of gates that perform the operations specified by the source code. It is the process of deriving a list of components and their interconnections from the model of a digital system described in HDL. 17. List the important features of HDL. (Nov 2006, May 2010) The important features of HDL are 1). It is specifically oriented to describe hardware structures and behaviors. 2). It can be used to represent logic diagrams, Boolean expressions and other complex digital circuits. 3). It is used to represent and document digital systems in a form that can be read by both humans and computers. 18. Mention any two uses of HDL. (May 2006) 1). HDL is a language that describes the hardware of digital systems in textural form. 2). It can be used to represent logic diagrams, Boolean expressions and other more complex digital circuits. 3). It is used to represent and document digital systems in a form that can be read by both humans and computers. 4). The language content can be stored and retrieved easily and processed by computer software in an efficient manner. 19. List the modeling techniques in HDL. (Nov 2011) The modeling techniques in HDL are 1) Data Flow Modeling. 2) Behavioral Modeling 3) Gate level Modeling.

27 PART B (2 MARKS) 1. a) Design a half subtractor circuit. b) Design a full Adder circuit with necessary diagram. (Apr/May 2010) 2. Explain BCD subtractor using 9 s and 10 s complement method, with a neat diagram. (Nov/Dec 2009) 3. a) Explain Binary multiplier with a suitable block diagram. b) Write a detailed note on carry propagation. (Nov/Dec 2011) 4. Design a logic circuit that accepts a 4-bit Gray code and convert it into 4-bit binary code. 5. Construct a combinational circuit to convert given binary coded decimal number into an excess- 3 code. For example, when the input to the gate is 0110 then the circuit should generate output as a) Implement the following Boolean function with 16:1 multiplexer F (A, B, C, D) = m (0, 1, 3, 4, 8, 9, 15) using block diagram. b) Implement full adder with two 4:1 multiplexers. (Apr/May 2012)

28 UNIT III : SYNCHRONOUS SEQUENTIAL LOGIC PART A (2 MARKS) Design of sequential circuit 1. What is sequential circuit? (Nov, Dec 2011) Sequential circuit is a broad category of digital circuit whose logic states depend on a specified time sequence. A sequential circuit consists of a combinational circuit to which memory elements are connected to form a feedback path. 2. What are the differences between sequential and combinational logic circuits? (Nov 2004, Nov 2007, May 2010) The differences between sequential and combinational logic circuits 3. State one advantage and disadvantage of Asynchronous sequential circuit. (Nov 2005) The advantage and disadvantage of asynchronous sequential circuit are Advantage: Because of the absence of clock it can operate faster than synchronous sequential circuits. Disadvantage: The charge in input signal can affect memory elements at any instant of time and it is more difficult to design. 4. State the classifications of sequential circuit. The classifications of sequential circuit are i) Synchronous sequential circuit. ii) Asynchronous sequential circuit. 5. What is a Synchronous sequential circuit? A Synchronous sequential circuit is a system whose behavior can be defined from the knowledge of its signal at discrete instants of time.

29 6. What are clocked sequential circuits? Synchronous sequential circuit that use clock pulses in the inputs of memory elements are called clocked sequential circuit. One advantage as that they don t cause instability problems. Flip flop 7. Draw the logic diagram of D-type latch. (Nov 2007) The logic diagram of D-type latch is given as 8. Differentiate Flip-flops from Latches. (May 2010) Latch is a sequential device that checks all of its inputs continuously and changes its outputs according to any time, independent of a clocking signal. Flip-flop is a sequential device that samples its inputs and changes its outputs only at times determined by clocking signal. 9. What is race around condition? How can it be avoided? (May 2009, Nov 2009) Race around condition is defined as in a JK latch, when J and k are both high, then the output toggles continuously. This condition is called a race around condition.

30 10. Derive the characteristic equation of a D flip-flop. (Nov 2002) The characteristic equation of a D flip-flop is given as Characteristic equation: Qn+1= TQn + T Qn 11. A reduced state table has 14 rows. What is the minimum number of flip-flops needed to build the sequential circuit? (Nov 2004) The minimum number of flip-flops needed to build the sequential circuit is four, therefore 24> Define Latch Latch is a simple memory element, which consists of a pair of logic gates with their inputs and outputs inter connected in a feedback arrangement, which permits a single bit to be stored. 13. List the different types of flip-flops. The different types of flip-flops are i) SR flip-flop ii) Clocked RS flip-flop iii) D flip-flop iv) T flip-flop v) JK flip-flop vi) JK master slave flip-flop 14. What is the meaning for triggering of flip-flop? The meaning for triggering of flip-flop is the state of a flip-flop is switched by a momentary change in the input signal. This momentary change is called a trigger and the transition it causes is said to trigger the flip-flop. Counters and shift registers 15. What is a binary counter? (Nov 2006) Binary counter is a counter that follows the binary sequence is called binary counter. An n-bit binary counter consists of n flip-flops and can count in binary from 0 to 2n-1.

31 16. State the relative merits of series and parallel counters. (May 2003) The relative merits of series and parallel counters are in comparison with parallel counters the serial counters have simple logic circuits, however, serial counters are low speed counters as the clock is propagated through number is flip-flops before it reaches the last flip-flop. 17. What is a shift register? (Nov 2003) Shift register is a register capable of shifting its binary information in one or both directions is called shift register. The logical configuration of a shift register consists of a chain of flip-flops in cascade, with the output of one flip-flop connected to the input of the next flip-flop. All flip-flops receive common clock pulses, which activate the shift from one stage to the next. 18. How many flip-flops are needed to build an 8-bit register? (Nov 2002) Flip-flops are needed to build an 8-bit register are 8 -flops are needed to build an 8-bit register. 19. What are the applications of shift registers? (May 2005) The applications of shift registers are i) A serial-in-serial-out shift register can be used to introduce time delay in digital signals. ii) A serial-in-parallel-out shift register can be used to convert data in the serial form to the parallel form. iii) A parallel-in-serial-out shift register can be used to convert data in the parallel form to the serial form. iv) A shift register can also be used as a counter. 20. A shift register comprises of JK flip-flops. How will you complement the contents of the register? (May 2003) Shift register outputs J and K of previous flip-flop are connected to the inputs of the next flip-flop. If these lines are connected through OR gate, we can complement the contents of flip-flop. When complement line is high all J and K inputs will be high and flip-flops will complement the output. 21. What is an excitation table? Excitation table is the design process we usually know the transition from present state to next state and wish to find the flip-flop input conditions that will cause the require transition. A table which lists the required inputs for a given chance of state is called an excitation table.

32 22. What is a characteristic table? A characteristic table defines the logical property of the flip-flop and completely characteristic its operation. 23. Define Counter Counter is used to count pulse and give the output in binary form. 24. Define Synchronous counter In a synchronous counter, the clock pulse is applied simultaneously to all flip-flops. The output of the flip-flops change states at the same instant. The speed of operation is high compared to an asynchronous counter. 25. Define Asynchronous counter In an Asynchronous counter, the clock pulse is applied to the first flip-flops. The change of state in the output of this flip-flop serves as a clock pulse to the next flip-flop and so on. Here all the flip-flops do not change state at the same instant and hence speed is less. 26. Name the different types of counter. The different types of counter are a) Synchronous counter b) Asynchronous counter i) Up counter ii) Down counter iii) Modulo N counter iv) Up/Down counter. 27. What is an up counter? Up counter is a counter that increments the output by one binary number each time a clock pulse are applied. 28. What is a down counter? Down counter is a counter that decrements the output by one binary number each time a clock pulse are applied. 29. What is an up/down counter? A mode control input (M) is provided to select either up or down mode. When M=0, the counter acting as up counter and When M=1, the counter acting as down counter. 30. What is a ripple counter? A ripple counter is nothing but an asynchronous counter, in which the output of the flip-flop changes state like a ripple in water.

33 31. State the uses of a counter? The uses of a counter are i) The digital clock ii) Auto parking control iii) Parallel to serial data conversion. 32. What is meant by modulus of a counter? The term modulus of a counter we say it is the number of states through which a counter can progress. 33. What is meant by natural count of a counter? The term natural count of a counter we say that the maximum number of states through which a counter can progress. 34. What is a ring counter? Ring counter is a counter formed by circulating a bit in a shift register whose serial output has been connected to its serial input. 35. What is a BCD counter? A BCD counter counts in binary coded decimal from 0000 to 1001 and back to Because of the return to 0000 after a count of 1001, a BCD counter does not have a regular pattern as in a straight binary counter. 36. State the uses of a ring counter? The uses of a ring counter are i) Control section of a digital system. ii) Controlling events, which occur in strict time sequence. 37. What is a register? Register is defined as memory elements capable of storing one binary word. It consists of a group of flip-flops, which store the binary information. 38. What is Johnson counter? Johnson counter is a ring counter in which the inverted output is fed into the input. It is also know as a twisted ring counter. 39. What is a shift register? Shift register is defined in digital circuits datas are needed to be moved into a register (shift in) or moved out of a register (shift out). A group of flip-flops having either or both of these facilities is called a shift register. 40. What is serial shifting? Serial shifting is defined in a shift register, if the data is moved 1 bit at a time in a serial fashion, then the technique is called serial shifting.

34 41. What is parallel shifting? Parallel shifting is defined in a shift register all the data are moved simultaneously and then the technique is called parallel shifting. 42. Write the uses of a shift register. The uses of a shift register i) Temporary data storage ii) Bit manipulations.

35 PART B (16 MARKS) 1. Design the sequential circuit specified by the following state diagram using JK flip flop. (16) (Apr/May 2012) 2. Design a sequential circuit using RS flip flop for the state table given below using minimum number of flip flops. (16) (Nov/Dec 2012) 3. What is the aim of state reduction? Reduce the given state diagram and prove that both the state diagrams are equal. (16) (Apr/May 2010) 4. Explain state reduction and state assignment with suitable examples. (16) (Nov/Dec 2011)

36 5. Design and explain the working of a synchronous mod 7 counter. (16) 6. Design a synchronous counter with states 0, 1, 2, 3, 0, 1 using JK flip-flop (16) 7. Design a parallel counter using SR flip flops which counts in the sequence 000,111,101,110,001,010,000.. (16) 8. a) Design a 3-bit binary counter. (10) b) Write the HDL description of T flip flop and JK flip flop from D flip Flop and gates. (6) (Nov/Dec 2012)

37 UNIT IV : ASYNCHRONOUS SEQUENTIAL LOGIC PART A (2 MARKS) 1. What are the steps to be followed in the design of asynchronous sequential circuit? (Nov, Dec 2009) The steps to be followed in the design of asynchronous sequential circuit are i) Construction of a primitive flow table from the problem statement. ii) Primitive flow table is reduced by eliminating redundant states using the state reduction. iii) State assignment is made. iv) The primitive flow table is realized using appropriate logic elements. 2. What is meant by flow table? During the design of asynchronous sequential circuits, it is more convenient to name the states by letter symbols without making specific reference to their binary values. Such a table is called a flow table. 3. Define Primitive flow table A primitive flow table is a special case of flow table with only one stable state in each row. 4. Define Merging The primitive flow table has only one stable state in each row. The table can be reduced to a smaller numbers of rows if two or more stable states are placed in the same row of the flow table. The grouping of stable states from separate rows into one common row is called merging. 5. Write the procedural steps for determining the compatibles used for the purpose of merging a flow table. The purpose that must be applied in order to find a suitable group of compatibles for the purpose of merging a flow table can be divided into 3 procedural steps i) Determine all compatible pairs by using the implication table. ii) Find the maximal compatibles using a Merger diagram iii) Find a minimal collection of compatibles Races 6. What is meant by race conditions? (Apr, May 2010) When two or more binary state variables change their value in response to a change in an input variable, race condition occurs in asynchronous sequential circuits. In case of unequal delays, a race condition may cause the state variables to change in an unpredictable manner. 7. What is critical race? Why should it be avoided? (Nov, Dec 2010) Race exists in synchronous sequential circuits when two or more binary state variables charge during a state transition. A race becomes critical if the correct next value in not reached during a state transition. For the proper operation of the circuits, the critical races must be avoided.

38 8. What is meant by a race condition in asynchronous sequential circuit? (Nov, Dec 2011) A race condition is said to exist in an asynchronous sequential circuit when two or more binary state variables changes value in response to a change in an input variable. The order by which the state variables change may not be known in advance if the final stable state that the circuit reaches does not depend on the order in which the state variable change, the race is called a non-critical race. 9. What are the assumptions to be made in the pulse mode circuit? (Nov, Dec 2010) The assumptions to be made in the pulse mode circuit are i) The input variables are pulses instead of levels. ii) The width of the pulses is long enough for the circuit to respond to the input. iii) The pulse width must not be so long that it is still present after the new state is reached. 10. What are the two types of asynchronous circuits? (Apr, May 2010) Two types of asynchronous circuits are i) Fundamental mode circuit. ii) Pulse mode circuit. 11. What is the advantage of debounce circuit? (Nov, Dec 2010) The advantage of a debounce circuit is a circuit which removes the series of pulses that result from a contact bounce and produces a single smooth transition of the binary signal from 0 to 1or from 1 to What are the assumptions made for fundamental mode circuit? (Apr, May 2010) The assumptions made for fundamental mode circuit are i) The input variables change only when the circuit is stable. ii) Only one input variable can change at a given time. iii) Inputs are levels and not pulses. Hazards 13. What are hazards? (Nov, Dec 2011) Hazards are unwanted switching transients that may appear at the output of a circuit because different paths exhibit different propagation delays.

39 14. What are the types of hazards? (Nov, Dec 2010) The 3 types of hazards are 1. Static hazards Static 0 hazards Static 1 hazard 2. Dynamic hazards. 15. How does an essential hazard occur? (Apr, May 2012) An essential hazard occurs due to unequal delays along two or more paths that originate from the same input. An excessive delay through an inverter circuit in comparison to the delay associated with the feedback path causes essential hazard. 16. Define Static 0-Hazard, Static 1-Hazard and Dynamic Hazard (Apr, May 2009) i) Static-1 hazard: In a combinational circuit, if output goes momentarily 0 when it should remain a1, the hazard is known as static-1 hazard. ii) Static-0 hazard: In a combinational circuit, If the output goes momentarily 1 when it should remain a 0, the hazard is known as static-0 hazard. iii) Dynamic hazard: When the output changes three or more times when it should change from 1 to 0 or from 0 to 1 is known as dynamic hazard. 17. What are the hazards in combinational circuits? (Nov, Dec 2011) The unwanted switching transients that may appear at the output of a circuit are called hazards. The hazards cause the circuit to malfunction. The main cause of hazards is the different propagation delays at different paths. Hazards occur in the combinational circuits, where they may cause a temporary false output value. When such combinational circuits are used in the asynchronous sequential circuits, they may result in a transition to a wrong stable state. 18. How can the hazards in combinational circuit be removed? Hazards in the combinational circuits can be removed by covering any two min terms that may produce a hazard with a product term common to both. The removal of hazards requires the addition of redundant gates to the circuit. 19. Does Hazard occur in sequential circuit? If so what is the problem caused? Yes, Hazards occur in sequential circuit that is Asynchronous sequential circuit. It may result in a transition to a wrong state.

40 PART B (16 MARKS) 1. Design an asynchronous sequential circuit that has 2 inputs X2 and X1 and one output Z. When X1=0, the output Z is 0. The first change in X2 that occurs while X1 is 1 will cause output Z to be 1. The output Z will remain 1 until X1 returns to 0. (16) (Apr/May 2012) 2. Construct the state diagram and primitive flow table for an asynchronous network that has two inputs and one output. The input sequence X1X2 = 00, 01, and 11 causes the output to become 1.The next input change then causes the output to return to 0. No other inputs will produce a 1 output. (16) 3. Write a detailed note on race free state assignment. (16) (Nov/Dec 2011) 4. What is the objective of state assignment in an asynchronous circuit? Give hazard free realization for the following Boolean function f (A, B, C, D) = Σm(0, 2, 6, 7, 8, 10, 12). (16) 5. a) Explain the hazards in combinational and sequential logic circuit with suitable examples. (8) b) Explain the concept of reduction of state and flow tables with necessary examples. (8) (Apr/May 2010)

41 UNIT V : MEMORY AND PROGRAMMABLE LOGIC PART A (2 MARKS) 1. What is a multiplexer? (Nov 2006, May 2010, Apr/May 2010) A multiplexer is a digital switch which allows digital information from several sources to be routed into a single output line. The basic multiplexer has several data-input lines and a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally there are 2n input lines and n selection lines. 2. Write a dataflow description of a 2-1 line MUX using a conditional operator. (Nov, Dec 2010) Module mux (A, B, select, out); input A, B, select; output out; assign out = select? A: B endmodule 3. Implement the logic function f= Σm (0, 2, 3, 6) using a decoder. (May 2006)

42 4. Construct a 16 1 multiplexer with two 8 1 multiplexer and 2 1 Multiplexer. (Nov 2008) 5. What is a demultiplexer? (May 2008) A demultiplexer is a combinational logic circuit with an input line, 2n output lines and n select lines. It routes the information present on the input line to any of the output lines. The output line that gets the information present on the input line is decided by the bit status of the selection lines. 6. How can a decoder be converted into a demultiplexer? (Nov 2005) Decoder is a circuit which converts one form of code into another. Demultiplexer is a circuit which converts one input to many outputs. If the enable line E is taken as a data input line A and B are taken as selection lines, then it is a demultiplexer. 7. Distinguish between decoder and demultiplexer. (May 2004, Nov 2009)

43 8. Implement the logic function f= AB + A.B using a suitable multiplexer: F = AB + A B = Σm (3, 0) 9. Design 8: 1 multiplexer using two 4:1 multiplexers. 10. Design 1: 8 demultiplexer using two 1: 4 demultiplexers.

44 11. Write any two applications of multiplexers. (May 2007, May 2009) The applications of demultiplexer are i) Data routing ii) Logic function generator iii) Control sequencer iv) Parallel-to-serial converter. 12. Define Priority encoder (May 2008, May 2007, Nov/Dec 2010) A priority encoder is an encoder circuit that includes the priority function. The operation of priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. 13. What is a decoder? (May 2009) A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2 n unique output lines. If the n bit coded information has unused combinations, the decoder may have fewer than 2n outputs. 14. What is an encoder? (May 2010) An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2 n and n output lines. The output lines generate the binary code corresponding to the input value. 15. What are the functions of encoders and decoders? (Nov 2006) An encoder is a combinational circuit that converts binary information from 2 n input lines to a maximum of n unique output lines. A decoder is a combinational circuit that decodes the binary information on n input lines to a maximum of 2 n unique output lines. 16. Draw the circuit diagram for 3-bit parity generator. (Nov 2007)

45 17. Draw the logic diagram of 4 bit even parity checker. (Nov 2008) 18. What is a Binary parallel adder? A binary parallel adder is a digital function that produces the arithmetic sum of two binary numbers in parallel. 19. What is a BCD adder? A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit also in BCD. 20. What are a Parity Generator/ Checker? A parity bit is used for the purpose of detecting errors during transmission of binary information. A parity bit is an extra bit included in a binary message to make the number of 1 s either odd or even. The message, including the parity bit is transmitted and then checked at the receiving end for errors. An error is detected if the checked parity does not correspond with the one transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker. 21. What is Programmable Logic Array (PLA)? How does it differ from ROM? (Nov/Dec2009) PLA is a programmable logic device which consists of programmable AND and OR array. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM. 22. What is a combinational PLD? (Apr, May 2012) It is an integrated circuit with programmable gates divided into an AND array and OR array to provide an AND- OR sum of product implementation. There are three types of combinational PLD s i) PROM-fixed AND array, programmable OR array. ii) PAL- Programmable AND array, fixed OR array iii) PLA- Programmable AND array and Programmable OR array.

46 23. How can a multiplexer be used to convert 8-bit parallel data into serial form? Draw the circuit and briefly explain. (May 2006) Here, binary counter is used to derive the select inputs of the multiplexer so that as the binary counter increments its count, the next bit is available at the output of the multiplexer. The binary counter counts from 000 to 111, therefore D0 through D7 bits are available at the output of the multiplexer as serial output. 24. List the basic types of programmable logic devices. The basic types of programmable logic devices are 25. Define ROM 1. Read only memory 2. Programmable logic Array 3. Programmable Array Logic A read only memory is a device that includes both the decoder and the OR gates within a single IC package. 26. Define PAL PAL programmable logic device with fixed OR array and a programmable AND array. Because only AND gates are programmable, PAL is easier to program, but it is not as flexible as PLA. 27. Define Address and word In a ROM, each bit combination of the input variable is called on address. Each bit combination that comes out of the output lines is called a word. 28. State the types of ROM? The types of ROM are 1. Masked ROM. 2. Programmable Read only Memory 3. Erasable Programmable Read only memory. 4. Electrically Erasable Programmable Read only Memory.