Figure 1-1 Basic Gates

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Abraham Jacobs
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1 Figure - Basic Gates B ND: = B B OR: = + B NOT: = ' B ELUSIVE OR: = + B

2 Figure -2 Full dder Y in FULL DDER (a) Full adder module out Sum Y in outsum (b) Truth Table Sum = 'Y'in + 'Yin' + Y'in' + Yin = + Y + in out = 'Yin + Y'in + Yin' + Yin = Y + in + Yin

3 Figure -3 Four-Variable Karnaugh Maps B D B D four corner terms combine to give B' D' 'BD F = m(,2,3,5,6,7,8,,) + d(4,5) = + B' D' + ' BD = (B' + + D) (B + + D') ('+B')

4 Figure -4 Selection of Prime Implicants B D '' D 'B'D' F = '' + 'B'D' + D + 'BD or F = '' + 'B'D' + D + BD

5 Figure -5 Simplification Using Map-Entered Variables B D D B B D D B E F E G E = F = MS = 'B' + D E =, F = MS = 'D E =, F = MS 2 = D G = MS + EMS + FMS 2 = 'B' + D + E'D + FD

6 Figure -6 NND and NOR Gates NND: B B = (B)' = ' + B' B NOR: B = (+B)' = 'B'

7 Figure -7 onversion to NOR Gates B' D E F G (a) ND-OR network Z B' ' omplemented input cancels inversion Double inversion cancels D E F G' (b) Equivalent NOR-gate network Z

8 Figure -8 onversion of ND-OR Network to NND Gates B D (a) ND_OR network E F B Bubbles cancel D (b) First step in NND conversion E F B' dded inverter D' (c) ompleted conversion dded inverter E' F

9 Figure -9 Elimination of -Hazard B D F E F = B' + B (a) Network with -hazard B - Hazard B B' D E F ns ns 2 ns 3 ns 4 ns 5 ns 6 ns (b) Timing hart B F B F = B' + B + (c) Network with hazard removed

10 Figure - locked D Flip-flop with Rising-edge Trigger Q' LK DFF Q D Q + = D D Q Q +

11 Figure - locked J-K Flip-flop Q' K FF K Q J J K Q Q + Q + = JQ' + K'Q

12 Figure -2 locked T Flip-flop Q' Q T Q Q + LK FF T + Q = QT' + Q'T = Q + T

13 Figure -3 S-R Latch S R P Q S R Q Q+ Q + = S + R'Q

14 Figure -4 Transparent D Latch G Q Latch D G D Q Q +

15 Figure -5 Implementation of D Latch D G Q Q + = DG + G'Q + (DQ) D

16 Figure -6 General Model of Mealy Sequential Machine Inputs () Outputs (Z) ombinational Network Next state clock State Reg State

17 Figure -7 State Graph and Table for ode onverter t t t 2 t 3 /,/ S / / N S S2 / / /,/ N S3 S4 /,/ / / S5 S6 N (a) Mealy state graph / NS PS = = S S S2 S3 S4 S5 S6 S S3 S4 S5 S5 S S S2 S4 S4 S5 S6 S Z = = (b) State Table

18 From Page 2 I. States which have the same next state (NS) for a given input should be given adjacent assignments (look at the columns of the state table). II. States which are the next states of the same state should be given adjacent assignments (look at the rows). III. States which have the same output for a given input should be given adjacent assignments. I. (,2) (3,4) (5,6) (in the = column, S and S2 both have NS S4; in the = column, S3 & S4 have NS S5, and S5 & S6 have NS S) II. (,2) (3,4) (5,6) (S & S2 are NS of S; S3 & S4 are NS of S; and S5 & S6 are NS of S4) III. (,,4,6) (2,3,5) Q2 Q3 Q S S Figure -8(a) State ssignment Map S5 S2 S3 S6 S4

19 Figure -7(b) State Table Figure -8(b) Transition Table NS Z Q Q2 Q3 Z PS = = = = QQ2Q3 = = = = S S S2 S S3 S4 S2 S4 S4 S3 S5 S5 S4 S5 S6 S5 S S S6 S xxx x xxx xxx x x S =, S =, S2 =, S3 =, S4 =, S5 =, S6 =

20 Figure -9 Karnaugh Maps for Figure -7 Q Q 2 Q 3 Q Q 2 Q 3 D = Q + = Q 2 ' Q Q 2 Q 3 D 2 = Q + 2 = Q Q Q 2 Q 3 D 3 = Q 3 + = Q Q 2 Q 3 + 'Q Q 3 ' + Q 'Q 2 ' Z = 'Q 3 ' + Q 3

21 Figure -2 Realization of ode onverter Q Q2 Q3 G Q2' D Q FF Q' Q Q' I Q Q3' ' G2 2 Q D Q FF2 Q' Q2 Q2' G5 5 Q' Q2' G3 3 D3 G4 LK D Q FF3 Q' Q3 Q3' ' G6 6 G7 Z

22 Figure -2 Derivation of J-K Input Equations Q Q + Q J = Q 2 ' Q K = Q 2 Q 2 Q 3 Q 2 Q 3 Q 2 Q 3 (a) Derivation using separate J-K map Q + Q Q + Q 2 Q Q + 3 Q 2 Q 3 Q 2 Q 3 J 2 Q 2 Q 3 K 2 ' J 3 J3 K 3 ' J K ' J J 2 = Q J = Q 2 ' K = Q K 2 2 = Q ' (b) Derivation using the shortcut method J 3 = 'Q + Q ' K 3 = Q ' + Q 2 '

23 Figure -22 oding Schemes for Serial Data Transmission bit sequence NRZ NRZI RZ Manchester bit time

24 Figure -23 Moore network for NRZ-to-Manchester onversion NRZ data LK2 onversion Network Z Manchester data (a) onversion network S S3 S S2 (b) State Graph Present State S S S 2 S 3 Next State = = S S 2 S S 3 S 3 S (c) State table Present Output (Z)

25 Figure -24 Timing for Moore Network bit time (NRZ) LOK2 State Z (Manchester) S S S 2 S 3 S S 3 S S 3 S S S 2 S S 2 S 3 S S bit time

26 Figure -25 Determination of Equivalent States s i N Z = ( s i, ) s j N 2 Z 2 = 2 ( s j, ) s i s j iff Z = Z 2 for every input sequence

27 Figure -26(i) State Table Reduction Present State Next State = Present Output = a c f b d e c h/ a g d b g e e b f f a g c g h c f b c d e c - d e - f f - g b - c f - g a- d e- g a b iff c d and e f e- g a- b f a- b g c - e b-g e - f a- g a b c d e f

28 Figure -26(ii) State Table Reduction b c - d e - f a b iff c d and e f b c - d e - f c f - g a- d e- g c f - g a- d e- g d b- c f - g e- g a- b d b - c f - g e- g a- b e e f a- b f a- b g c - e b-g e - f a- g g c - e b-g e - f a-g a b c d e f a b c d e f a b, c d, e f

29 Figure -26(iii) State Table Reduction Present State Next State = Present Output = a c f b d e c h/ a g d b g e e b f f a g c g h c f a b, c d, e f Present State = = a c e c a g e e a g c g Final Reduced Table

30 Figure -27 Timing Diagram for ode onverter lock State S S S 3 S 5 S S 2 S 4 S 5 S Next State S S 3 S 5 S * S 2 S 4 S 5 S S 2 Z t a t b t c * = S

31 Figure -28 Timing Diagram for Figure -2 lock Q3 Q2 Q Z

32 Figure -29 Setup and Hold Times for D Flip-flop t su t h D lock Q t plh t phl

33 Figure -3 Setup and Hold Timing for hanges in LK t x t y t cxmin D t cxmax t su t h

34 Figure -3 Synchronous Digital System lock Data In ontrol Inputs ONTROL SETION ontrol Signals ondition Signals DT SETION Data Out

35 Figure -32 Timing hart for System with Falling-Edge Devicves State hange Initiated Here lock Switching Transients Uncertain ontrol Signal lock S Figure -33 Gated ontrol Signal lock S LK K lock S K (a) Faling-edge device (b) Rising-edge device

36 Figure -34 Timing hart with Rising-Edge Devices State hange Initiated Here lock Switching Transients ontrol Signal (S) LK = lock S (a) (b) S LK2 = lock + S Figure -35 Incorrect Design Figure -36 orrect Design (a) with gated clock (b) With enble lock S LK K lock S LK2 K S lock Enable K "Rising Edge" Device

37 Synchronous Design Principals (from page 34) Method: Result: ll clock inputs to flip-flops, registers, counters, etc. are driven directly from the system clock or from the clock NDed with a control signal. ll state changes occur immediately following the active edge of the clock signal. dvantage: ll switching transients, switching noise, etc. occur between clock pulses and have no effect on system performance.

38 Figure -37 Four Kinds of Tristate Buffers B B B B B Hi-Z Hi-Z B Hi-Z Hi-Z B Hi-Z Hi-Z B Hi-Z Hi-Z (a) (b) (c) (d)

39 Figure -38 Data Transfer Using Tristate Bus Input Data Eni 8 Ena 8 TRI-STTE BUS Enb Enc Lda Reg. Ldb Reg. B Ldc Reg. lock

CPE/EE 422/522. Chapter 1 - Review of Logic Design Fundamentals. Dr. Rhonda Kay Gaede UAH. 1.1 Combinational Logic

CPE/EE 422/522. Chapter 1 - Review of Logic Design Fundamentals. Dr. Rhonda Kay Gaede UAH. 1.1 Combinational Logic CPE/EE 422/522 Chapter - Review of Logic Design Fundamentals Dr. Rhonda Kay Gaede UAH UAH Chapter CPE/EE 422/522. Combinational Logic Combinational Logic has no control inputs. When the inputs to a combinational