Written reexam with solutions for IE1204/5 Digital Design Monday 14/
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1 Written reexam with solutions for IE204/5 Digital Design Monday 4/ General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone Exam text does not have to be returned when you hand in your writing. Aids: No aids are allowed! The exam consists of three parts with a total of 4 tasks, and a total of 30 points: Part A (Analysis containes ten short questions. Right answer will give you one point. Incorrect answer will give you zero points. The total number of points in Part A is 0 points. To pass the Part A requires at least 6p, if fewer points we will not look at the rest of your exam. Part A2 (Methods contains two method problems on a total of 0 points. To pass the exam requires at least points from A A2, if fewer points we will not look at the rest of your exam. Part B (Design problems contains two design problems of a total of 0 points. Part B is corrected only if there are at least p from the exam A- Part. NOTE! At the end of the exam text there is a submission sheet for Part A, which shall be separated and be submitted together with the solutions for A2 and B. For a passing grade (E requires at least points on the exam. If exactly 0p A(6pA2(4p, (FX, completion to (E will be offered. Grades are given as follows: F E D C B A The result is expected to be announced before Monday 4/4 206.
2 Part A: Analysis Only answers are needed in Part A. Write the answers on the submission sheet for Part A, which can be found at the end of the exam text.. p/0p A function f(x, y, z is described by the expression: f ( x, y, z = ( z x( x z( xyz Write down the function as a minimized product of sums, PoS. f ( x, y, z = { PoS } = min?. Proposed solution. f ( x, y, z = ( z x( x z( xyz ( z x = zx z x = { dm} = ( z x( z x ( xyz = { dm} = ( x y z f ( x, y, z = ( z x( z x( x y z = = ( z x( z x 2. p/0p A special case of addition is when a binary number x (x N x x 0 is incremented with, S = x. One can then build a simplified adder as in the figure. Since there is one number and not two numbers being added it is enough to use half adders (HA instead of full adders (FA. The first stage can be further simplified. Derive the functions S 0 and C out0 for this first stage. S =?? 0 C = out0 2. Propsed solution. It is enough that the blocks are half adders instead of full adders. The first stage just need an inverter. 3. p/0p Two two-complement 4 bit binary numbers are x = and y =. Give the result of the multiplication x y as a two-complement 8-bit binary number (sign extended to 8 bit. 3. Proposed solution. x = = - ( = - 2 = -6 0 y = 2 = = (8-bit = - 2 = ( 2 = 2 (238 2
3 4. p/0p Given is a Karnaugh map for a function of four variables Y = f(x 3, x 2, x, x 0. Write the function as a minimized Y min sum of products, on SoP form. - in the map means don t care. 4. Proposed solution. Y = x x x x x x x min x 5. p/0p Draw a circuit with NOR-gates that corresponds to the Venn-diagram in the figure. ( white area = 0, dark area =. The complement of the variables are not available. Z = f( xy, 5. Proposed solution. Z = x y = x y = { dm} = x y 6. p/0p The figure below shows a circuit with two NOR gates and one NAND-gate. Simplify the function Y = f( a, b, c as much as possible. 6. Proposed solution. Y = ( a c b c = { dm} = a c b c = = { dm} = a c b c = a b c 3
4 7. p/0p Give an expression for the logical function realized by the CMOS circuit in the figure? Give the function on the SoP form. Y = f(a, B, C =? 7. Proposed solution. The circuit has three inverters that first inverts the signals A B and C to A B C before they proceed. The lower part of the circuit, Pull Down Network, gives us the condition of 0, for Y. Finally Y is obtained with de Morgan Law. 8. p/0p A synchronous counter as shown above starts with the state q q 0 =. Specify the count sequence for the next four clock pulses. 8. Proposed solution. 4
5 9. p/0p For a JK-flip flop, as you probably remember, the following rules apply: JK: Q remains the same JK: 0 Q is reset to 0 JK: Q toggles value JK: 0 Q is set to Show (draw how to make a JK flip-flop of the D flip-flop and a 4: multiplexer. In addition to Q and its inverse, there are constants and 0 available. A copy of the figure is also on the submission sheet. 9. Proposed solution. 0. p/0p The following is the VHDL code for a logic function. What is the function? library ieee; use ieee.std_logic_64.all; entity GATE_ent is port( x: in std_logic; y: in std_logic; F: out std_logic ; end GATE_ent; architecture behv of GATE_ent is begin process(x, y begin if (x='0' and y='0' then F <= ''; else F <= '0'; end if; end process; end behv; 0. Proposed solution. F = x y = x y = { dm} = x y NOR ( or bubble AND 5
6 Part A2: Methods Note! Part A2 will only be corrected if you have passed part A ( 6p. 4p Light Gun - emergency equipment for traffic control tower. You shall construct a combinatorial circuit for a signal lamp for traffic control tower (emergency. With an 8-position binary coded switch one selects Mode M: m 2 m m 0. Turned off, steady green (G light, flashing green light, steady red (R light, flashing red light, flashing white light alternately green and red light, and steady white (W light. Flashing lights are controlled by x pulses from a pulse generator. See the figures. A trigger circuit with three AND gates are also in the figure (for eg. Morse signaling, but this part of the equipment is given, and is not included in the task. a (p Set up the truth table for the relationship between GRW and xm 2 m m 0. b (2p Draw the Karnaugh maps for the three output signals G R W and derive the minimized expressions for G = f(x,m 2,m,m 0, R = f(x,m 2,m,m 0 and W = f(x,m 2,m,m 0 on SoP-form. c (p Draw the combinatorial circuit using optional gates. (No inverted variables are available.. Proposed solution. For mode 6, when G and R are alternating, it is important that the G and R have opposite values in the truth table rows 6 and 4! 6
7 2. 6p A synchronous sequential circuit, a Moore machine, have one input signal x and one output signal out. The circuit state diagram is shown in the figure below right. In the figure is shown where x q q 0 and out is placed in the state symbol. If the circuit would "end up" in a state outside of the sequence described by the state diagram, the circuit should remain in the state but with out = 0 and an additional output error =. The additional output error should always be 0 otherwise. The Moore machine uses D-flip-flops. a (p Derive the encoded state table. q q0 = f ( x, qq0 b (2p Derive minimized expressions for next state. q = f x, q q = f x, q ( q0 0 ( q0 c (p Derive minimized expressions for the output functions. out = f ( q q q 0 error = f q also draw wiring diagram for these with optional gates. ( 0 d (2p Construct the circuit, use two 4: multiplexers and not more than one inverter to the next state functions q = f x, q q q = f ( x, q ( 0 0 q0 You should indicate what is to be connected to multiplexers data inputs. See the figure to the right. q : mux q 0 : mux =? =? 7
8 2. Proposed solution. 8
9 Part B. Design Problems Note! Part B will only be corrected if you have passed part AA2 ( p. 3. 5p Synchronous sequential circuit. Detector for specific event. For a Moore machine applies to the output signal z = if and only if the input signal is w = at the clock pulse, and if of the previous clock pulses at exactly one time the input signal was, and at least one time the input signal was 0. Otherwise, the output is 0. (After a short reset pulse of clr =, the machine is ready to detect the "event" again. a (3p Derive the state table and state diagram based on the description in the text. A completely different Moore machine has two input signals and one output signal. The machine has six states according to the state diagram in the right figure. Output value is written in square brackets inside the states []. b (2p State minimize the machine, and derive the state table and state diagram of the minimized circuit. 3. Proposed solution. a b ( ace ( bdf a ( ace a c e ( ace ( ae ( c( bdf b ( ae d f c e b d f 0 0 ( ae ( ae a c e d f b ( ace ( ae a c e b d f 0 0 ( ace ( ace ( ace ( ae ( ae 9
10 ( ae ( b( c( df now minimized. ( ae = A ( b = B ( c = C ( df = D 4. 5p Frequency divider with ratio :.5. A computer system have a 90 MHz clock. We want to divide the frequency by a factor of.5 down to a frequency of 60 MHz. For this you need an asynchronous sequential circuit. See the figure. a Set up a proper flow table for the sequence circuit. Draw the state diagram. b Do a suitable state assignement with an exitation table which gives a circuit that is free of critical race. (Comment on how this has been achieved. You should also derive hazard free expressions (comment on how this has been achieved for the next state and an expression for output. You do not need draw any schematic. 4. Proposed solution. Code has Hamming distance. Hazard cover included. Good Luck! 0
11 Submission sheet for Part A Sheet (remove and hand in together as sheet no with your answers for part A2 and part B Last name: Given name: Personal code: Sheet: Write down your answers for the questions from Part A ( to 0 Question Answer f ( x, y, z = { PoS } = min? S =?? 0 C = out0 x y (8 bit 2-complement =? Y = {SoP} min 5 Z = f( xy, Y = f( a, b, c Y = f(a, B, C =? q q 0 =???????? 9 0 (VHDL program What is the function? This table is completed by the examiner!! Part A (0 Part A2 (0 Part B (0 Total (30 Poäng Sum Grade
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