# ELCT201: DIGITAL LOGIC DESIGN

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1 ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, Dr. Eng. Wassim Alexan, Lecture 6 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter 2018

2 COURSE OUTLINE 1. Introduction 2. Gate-Level Minimization 3. Combinational Logic 4. Synchronous Sequential Logic 5. Registers and Counters 6. Memories and Programmable Logic 2

3 LECTURE OUTLINE Sequential Circuits Introduction Memory Types Latches SR Latch D Latch 3

4 COMBINATIONAL LOGIC CIRCUITS These are circuits that use logic gates, where the output depends only on the current inputs w x y F z 4

5 SEQUENTIAL LOGIC CIRCUITS These are circuits where the outputs depend on the sequence of past outputs As a result, such a circuit must remember something about the past Example: In a football game The current score = the previous goals (state) + new goal (input) For example, if you have a previous goal score of 5 and there is a new goal, then the final score will be 6 5

6 SEQUENTIAL LOGIC CIRCUITS A circuit with memory, whose outputs depend on the current input and the sequence of past outputs, is called a sequential circuit The behavior of such a circuit may be described by a state table that specifies its output and next state as functions of its current state and input 6

7 TYPES OF SEQUENTIAL LOGIC CIRCUITS 1. Synchronous, where the behavior of the circuit depends on the input signal at discrete instances of time (also called clocked) 2. Asynchronous, where the behavior of the circuit depends on the input signals at any instance of time and the order of the inputs change A combinational logic circuit with feedback 7

8 STORAGE ELEMENTS What is required from a storage element? Store data (hold) Accept writing new data (write) Read the stored data 8

9 TYPES OF STORAGE ELEMENTS Latches SR D Flip-flops Master-slave Edge-triggered D JK T Before going in detail regarding storage elements, we must understand what a clock signal is 9

10 DEFINING THE CLOCK A clock signal is a particular type of signal that oscillates between a high and a low state and is utilized to coordinate actions of circuits A clock signal is produced by a clock generator While other more complex arrangements are also in use, the most common clock signal takes the form of a square wave, with 50% duty cycle, usually with a fixed, constant frequency Circuits using a clock signal for synchronization may become active at either the rising or the falling edge of a clock cycle Clk 10

11 CLOCK PULSES A clock pulse can be positive or negative Positive pulse Negative pulse Positive edge Negative edge Negative edge Positive edge 11

12 BASIC MEMORY ELEMENTS A basic memory element consists of two cascaded inverters and the output of the last inverter is fed back into the input of the first inverter Q and Q are the outputs of the memory element Such a memory element will always store a single bit Such a memory element is called a Latch 1 Q = 0 Q = 1 12

13 STORAGE ELEMENTS But how to write a new value in this latch? We need a special technique that enables us to do this writing action 1 Q = 0 Q = 1 13

14 SR LATCH USING NOR GATES R S Q Q S R Q Q Circuit Graphic symbol Characteristic table 14

15 SR LATCH USING NOR GATES The SR latch is constructed with two cross-coupled NOR gates and two inputs labelled S for set and R for reset The SR latch has two useful states When the output Q = 1 and Q = 0, the latch is said to be in the set state When Q = 0 and Q = 1, it is in the reset state Outputs Q and Q are normally the complement of each other 15

16 SR LATCH USING NOR GATES The SR latch can store only 1 bit If both inputs are equal to 1 at the same time, a condition in which both new outputs are equal to 0 occurs (irrespective of the old output values) If both inputs are then switched to 0 simultaneously, the device will enter an undefined state In practice, setting both inputs to 1 is forbidden! 16

17 SR LATCH USING NOR GATES Writing a 1 into the memory cell set state R Q S Q 17

18 SR LATCH USING NOR GATES Hold the written data in the memory cell hold state R Q S Q 18

19 SR LATCH USING NOR GATES Writing a 0 into the memory cell reset state R Q S Q 19

20 SR LATCH USING NOR GATES Hold the written date in the memory cell hold state R Q S Q 20

21 SR LATCH USING NOR GATES Having both inputs equal to 1 in the memory cell forbidden state Because if S and R go to the hold state after being both equal to 1, the memory cell will go into an undefined state R Q S 1 10 Q 21

22 SR LATCH USING NOR GATES R S Q Q Timing diagram 22

23 SR LATCH USING NAND GATES Also known as the S R latch S Q R Q S R Q Q Circuit Graphic symbol Characteristic table 23

24 SR LATCH USING NAND GATES The outputs of the latch are Q and Q After each write operation there must be a hold operation to store the data Writing a 1 into the cell means set (S = 0 & R = 1) The hold state means store the data (S = R = 1) Writing a 0 into the cell means reset (R = 0 & S = 1) For S = R = 0, this is an unstable condition The S R latch (SR latch using NAND gates) can store only one bit 24

25 SR LATCH: IMPLEMENTATION COMPARISON R Q S Q S Q R Q S R Q Q S R Q Q set hold reset hold reset hold set hold Forbidden case

26 GATED SR LATCH USING NAND GATES S Can we hold (store) the value at the outputs unchanged, even if the inputs keep changing? Q En S R Next state of Q 0 X X No change No change En R Q Q = Q = Undefined Circuit Characteristic table 26

27 GATED SR LATCH USING NAND GATES The control input En acts as an enable signal for the other two inputs The outputs of the first two NAND gates stay at the logic-1 level as long as the enable signal remains at 0 When the enable input goes to 1, information from S or R input is allowed to affect the latch The set state is reached with S = 1, R = 0 and En = 1 The reset state is reached with S = 0, R = 1 and En = 1 In either case, when En returns to 0, the circuit remains in its current state, irrespective of any later changes to S or R An undefined condition occurs when S = R = En = 1. As this places 0s on both inputs of the basic SR latch, which puts in in the undefined state 27

28 D LATCH (TRANSPARENT LATCH) Forces S and R to be complements of each other (so that they are never equal to 1 at the same time) D Q En Q 28

29 D LATCH (TRANSPARENT LATCH) Forces S and R to be complements of each other (so that they are never equal to 1 at the same time) En D Next state of Q 0 X No change 1 0 Q = Q = 1 Graphic symbol Characteristic table 29

30 D LATCH (TRANSPARENT LATCH) The D latch receives that designation from its ability to hold data in its internal storage It is suited for use as a temporary storage for binary info between a unit and its environment The binary information present at the data input of the D latch is transferred to the Q output when the enable input is asserted (En = 1) The output follows changes in the data input as long as the enable input is asserted (En = 1) This situation provides a path from input D to the output (thus the naming transparent latch) When the enable input is de-asserted (En = 0), the binary info that was present at the data input at the time the transition occurred is stored 30

31 THE LATCH TIMING PROBLEM What happens if Clk = 1? What will be the value of Q when the Clk goes to 0? Problem: A latch is transparent, its state keeps changing as long as the clock remains active Due to this uncertainty, latches cannot be reliably used as storage elements 31

32 THE LATCH TIMING PROBLEM When latches are used as storage elements, a problem arises The state transitions of the latches start as soon as the clock pulse changes to the logic-1 level The new state of a latch appears at the output while the pulse is still active This output is connected to the inputs of the latches through the combinational circuit If the inputs applied to the latches change while the clock pulse is still at the logic-1 level, the latches will respond to new values and a new output state may occur 32

33 THE LATCH TIMING PROBLEM This is an unpredictable situation, since the state of the latches may keep changing as long as Clk = 1 Because of this unreliable operation, the output of a latch cannot be applied directly or through combinational logic to the input of the same or another latch when all the latches are triggered by a common clock source 33

34 FLIP-FLOPS A flip-flop is a one-bit memory cell, similar to latches A flip-flop solves the issue of latch transparency Latches are level sensitive memory elements (active as long as Clk = 1) Flip-flops are edge-triggered or edge-sensitive memory elements (active only at transitions; i.e. either 0 1 or 1 0) 34

35 RESPONSE OF LATCHES VS. FLIP-FLOPS Latch Flip-flop Flip-flop 35

36 LEVEL-SENSITIVE VS. EDGE-TRIGGERED STORAGE ELEMENTS D Clk Q a Q a Clk D Q b Q b Q a Q b Q c Q c Q c Timing diagram Circuit 36

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