ELCT201: DIGITAL LOGIC DESIGN

Size: px
Start display at page:

Download "ELCT201: DIGITAL LOGIC DESIGN"

Transcription

1 ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, Dr. Eng. Wassim Alexan, Lecture 6 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter 2018

2 COURSE OUTLINE 1. Introduction 2. Gate-Level Minimization 3. Combinational Logic 4. Synchronous Sequential Logic 5. Registers and Counters 6. Memories and Programmable Logic 2

3 LECTURE OUTLINE Sequential Circuits Introduction Memory Types Latches SR Latch D Latch 3

4 COMBINATIONAL LOGIC CIRCUITS These are circuits that use logic gates, where the output depends only on the current inputs w x y F z 4

5 SEQUENTIAL LOGIC CIRCUITS These are circuits where the outputs depend on the sequence of past outputs As a result, such a circuit must remember something about the past Example: In a football game The current score = the previous goals (state) + new goal (input) For example, if you have a previous goal score of 5 and there is a new goal, then the final score will be 6 5

6 SEQUENTIAL LOGIC CIRCUITS A circuit with memory, whose outputs depend on the current input and the sequence of past outputs, is called a sequential circuit The behavior of such a circuit may be described by a state table that specifies its output and next state as functions of its current state and input 6

7 TYPES OF SEQUENTIAL LOGIC CIRCUITS 1. Synchronous, where the behavior of the circuit depends on the input signal at discrete instances of time (also called clocked) 2. Asynchronous, where the behavior of the circuit depends on the input signals at any instance of time and the order of the inputs change A combinational logic circuit with feedback 7

8 STORAGE ELEMENTS What is required from a storage element? Store data (hold) Accept writing new data (write) Read the stored data 8

9 TYPES OF STORAGE ELEMENTS Latches SR D Flip-flops Master-slave Edge-triggered D JK T Before going in detail regarding storage elements, we must understand what a clock signal is 9

10 DEFINING THE CLOCK A clock signal is a particular type of signal that oscillates between a high and a low state and is utilized to coordinate actions of circuits A clock signal is produced by a clock generator While other more complex arrangements are also in use, the most common clock signal takes the form of a square wave, with 50% duty cycle, usually with a fixed, constant frequency Circuits using a clock signal for synchronization may become active at either the rising or the falling edge of a clock cycle Clk 10

11 CLOCK PULSES A clock pulse can be positive or negative Positive pulse Negative pulse Positive edge Negative edge Negative edge Positive edge 11

12 BASIC MEMORY ELEMENTS A basic memory element consists of two cascaded inverters and the output of the last inverter is fed back into the input of the first inverter Q and Q are the outputs of the memory element Such a memory element will always store a single bit Such a memory element is called a Latch 1 Q = 0 Q = 1 12

13 STORAGE ELEMENTS But how to write a new value in this latch? We need a special technique that enables us to do this writing action 1 Q = 0 Q = 1 13

14 SR LATCH USING NOR GATES R S Q Q S R Q Q Circuit Graphic symbol Characteristic table 14

15 SR LATCH USING NOR GATES The SR latch is constructed with two cross-coupled NOR gates and two inputs labelled S for set and R for reset The SR latch has two useful states When the output Q = 1 and Q = 0, the latch is said to be in the set state When Q = 0 and Q = 1, it is in the reset state Outputs Q and Q are normally the complement of each other 15

16 SR LATCH USING NOR GATES The SR latch can store only 1 bit If both inputs are equal to 1 at the same time, a condition in which both new outputs are equal to 0 occurs (irrespective of the old output values) If both inputs are then switched to 0 simultaneously, the device will enter an undefined state In practice, setting both inputs to 1 is forbidden! 16

17 SR LATCH USING NOR GATES Writing a 1 into the memory cell set state R Q S Q 17

18 SR LATCH USING NOR GATES Hold the written data in the memory cell hold state R Q S Q 18

19 SR LATCH USING NOR GATES Writing a 0 into the memory cell reset state R Q S Q 19

20 SR LATCH USING NOR GATES Hold the written date in the memory cell hold state R Q S Q 20

21 SR LATCH USING NOR GATES Having both inputs equal to 1 in the memory cell forbidden state Because if S and R go to the hold state after being both equal to 1, the memory cell will go into an undefined state R Q S 1 10 Q 21

22 SR LATCH USING NOR GATES R S Q Q Timing diagram 22

23 SR LATCH USING NAND GATES Also known as the S R latch S Q R Q S R Q Q Circuit Graphic symbol Characteristic table 23

24 SR LATCH USING NAND GATES The outputs of the latch are Q and Q After each write operation there must be a hold operation to store the data Writing a 1 into the cell means set (S = 0 & R = 1) The hold state means store the data (S = R = 1) Writing a 0 into the cell means reset (R = 0 & S = 1) For S = R = 0, this is an unstable condition The S R latch (SR latch using NAND gates) can store only one bit 24

25 SR LATCH: IMPLEMENTATION COMPARISON R Q S Q S Q R Q S R Q Q S R Q Q set hold reset hold reset hold set hold Forbidden case

26 GATED SR LATCH USING NAND GATES S Can we hold (store) the value at the outputs unchanged, even if the inputs keep changing? Q En S R Next state of Q 0 X X No change No change En R Q Q = Q = Undefined Circuit Characteristic table 26

27 GATED SR LATCH USING NAND GATES The control input En acts as an enable signal for the other two inputs The outputs of the first two NAND gates stay at the logic-1 level as long as the enable signal remains at 0 When the enable input goes to 1, information from S or R input is allowed to affect the latch The set state is reached with S = 1, R = 0 and En = 1 The reset state is reached with S = 0, R = 1 and En = 1 In either case, when En returns to 0, the circuit remains in its current state, irrespective of any later changes to S or R An undefined condition occurs when S = R = En = 1. As this places 0s on both inputs of the basic SR latch, which puts in in the undefined state 27

28 D LATCH (TRANSPARENT LATCH) Forces S and R to be complements of each other (so that they are never equal to 1 at the same time) D Q En Q 28

29 D LATCH (TRANSPARENT LATCH) Forces S and R to be complements of each other (so that they are never equal to 1 at the same time) En D Next state of Q 0 X No change 1 0 Q = Q = 1 Graphic symbol Characteristic table 29

30 D LATCH (TRANSPARENT LATCH) The D latch receives that designation from its ability to hold data in its internal storage It is suited for use as a temporary storage for binary info between a unit and its environment The binary information present at the data input of the D latch is transferred to the Q output when the enable input is asserted (En = 1) The output follows changes in the data input as long as the enable input is asserted (En = 1) This situation provides a path from input D to the output (thus the naming transparent latch) When the enable input is de-asserted (En = 0), the binary info that was present at the data input at the time the transition occurred is stored 30

31 THE LATCH TIMING PROBLEM What happens if Clk = 1? What will be the value of Q when the Clk goes to 0? Problem: A latch is transparent, its state keeps changing as long as the clock remains active Due to this uncertainty, latches cannot be reliably used as storage elements 31

32 THE LATCH TIMING PROBLEM When latches are used as storage elements, a problem arises The state transitions of the latches start as soon as the clock pulse changes to the logic-1 level The new state of a latch appears at the output while the pulse is still active This output is connected to the inputs of the latches through the combinational circuit If the inputs applied to the latches change while the clock pulse is still at the logic-1 level, the latches will respond to new values and a new output state may occur 32

33 THE LATCH TIMING PROBLEM This is an unpredictable situation, since the state of the latches may keep changing as long as Clk = 1 Because of this unreliable operation, the output of a latch cannot be applied directly or through combinational logic to the input of the same or another latch when all the latches are triggered by a common clock source 33

34 FLIP-FLOPS A flip-flop is a one-bit memory cell, similar to latches A flip-flop solves the issue of latch transparency Latches are level sensitive memory elements (active as long as Clk = 1) Flip-flops are edge-triggered or edge-sensitive memory elements (active only at transitions; i.e. either 0 1 or 1 0) 34

35 RESPONSE OF LATCHES VS. FLIP-FLOPS Latch Flip-flop Flip-flop 35

36 LEVEL-SENSITIVE VS. EDGE-TRIGGERED STORAGE ELEMENTS D Clk Q a Q a Clk D Q b Q b Q a Q b Q c Q c Q c Timing diagram Circuit 36

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Following the slides of Dr. Ahmed H. Madian Lecture 10 محرم 1439 ه Winter

More information

Sequential vs. Combinational

Sequential vs. Combinational Sequential Circuits Sequential vs. Combinational Combinational Logic: Output depends only on current input TV channel selector (-9) inputs system outputs Sequential Logic: Output depends not only on current

More information

Sequential Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science

Sequential Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science Sequential Logic Rab Nawaz Khan Jadoon DCS COMSATS Institute of Information Technology Lecturer COMSATS Lahore Pakistan Digital Logic and Computer Design Sequential Logic Combinational circuits with memory

More information

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering SEQUENTIAL CIRCUITS: LATCHES Overview Circuits require memory to store intermediate

More information

Synchronous Sequential Logic

Synchronous Sequential Logic 1 IT 201 DIGITAL SYSTEMS DESIGN MODULE4 NOTES Synchronous Sequential Logic Sequential Circuits - A sequential circuit consists of a combinational circuit and a feedback through the storage elements in

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT2: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 4 Following the slides of Dr. Ahmed H. Madian محرم 439 ه Winter 28

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 5 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter

More information

Chapter 7 Sequential Logic

Chapter 7 Sequential Logic Chapter 7 Sequential Logic SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} March 28, 2016 Table of Contents 1 Intro 2 Bistable Circuits 3 FF Characteristics

More information

Lecture 14: State Tables, Diagrams, Latches, and Flip Flop

Lecture 14: State Tables, Diagrams, Latches, and Flip Flop EE210: Switching Systems Lecture 14: State Tables, Diagrams, Latches, and Flip Flop Prof. YingLi Tian Nov. 6, 2017 Department of Electrical Engineering The City College of New York The City University

More information

Introduction EE 224: INTRODUCTION TO DIGITAL CIRCUITS & COMPUTER DESIGN. Lecture 6: Sequential Logic 3 Registers & Counters 5/9/2010

Introduction EE 224: INTRODUCTION TO DIGITAL CIRCUITS & COMPUTER DESIGN. Lecture 6: Sequential Logic 3 Registers & Counters 5/9/2010 EE 224: INTROUCTION TO IGITAL CIRCUITS & COMPUTER ESIGN Lecture 6: Sequential Logic 3 Registers & Counters 05/10/2010 Avinash Kodi, kodi@ohio.edu Introduction 2 A Flip-Flop stores one bit of information

More information

Topic 8: Sequential Circuits

Topic 8: Sequential Circuits Topic 8: Sequential Circuits Readings : Patterson & Hennesy, Appendix B.4 - B.6 Goals Basic Principles behind Memory Elements Clocks Applications of sequential circuits Introduction to the concept of the

More information

Computers also need devices capable of Storing data and information Performing mathematical operations on such data

Computers also need devices capable of Storing data and information Performing mathematical operations on such data Sequential Machines Introduction Logic devices examined so far Combinational Output function of input only Output valid as long as input true Change input change output Computers also need devices capable

More information

Sequential Circuits Sequential circuits combinational circuits state gate delay

Sequential Circuits Sequential circuits combinational circuits state gate delay Sequential Circuits Sequential circuits are those with memory, also called feedback. In this, they differ from combinational circuits, which have no memory. The stable output of a combinational circuit

More information

LOGIC CIRCUITS. Basic Experiment and Design of Electronics

LOGIC CIRCUITS. Basic Experiment and Design of Electronics Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output

More information

Synchronous Sequential Circuit

Synchronous Sequential Circuit Synchronous Sequential Circuit The change of internal state occurs in response to the synchronized clock pulses. Data are read during the clock pulse (e.g. rising-edge triggered) It is supposed to wait

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT2: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 2 Following the slides of Dr. Ahmed H. Madian ذو الحجة 438 ه Winter

More information

Sequential Logic Circuits

Sequential Logic Circuits Chapter 4 Sequential Logic Circuits 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of a sequential circuit,

More information

LOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.

LOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D. Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor

More information

Chapter 14 Sequential logic, Latches and Flip-Flops

Chapter 14 Sequential logic, Latches and Flip-Flops Chapter 14 Sequential logic, Latches and Flip-Flops Flops Lesson 4 JK Flip Flop Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 JK Flip-Flop ve edge triggered Output Q and

More information

L4: Sequential Building Blocks (Flip-flops, Latches and Registers)

L4: Sequential Building Blocks (Flip-flops, Latches and Registers) L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements:., Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University

More information

L4: Sequential Building Blocks (Flip-flops, Latches and Registers)

L4: Sequential Building Blocks (Flip-flops, Latches and Registers) L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements: Lecture material adapted from R. Katz, G. Borriello, Contemporary Logic esign (second edition), Prentice-Hall/Pearson

More information

Latches. October 13, 2003 Latches 1

Latches. October 13, 2003 Latches 1 Latches The second part of CS231 focuses on sequential circuits, where we add memory to the hardware that we ve already seen. Our schedule will be very similar to before: We first show how primitive memory

More information

Chapter 4. Sequential Logic Circuits

Chapter 4. Sequential Logic Circuits Chapter 4 Sequential Logic Circuits 1 2 Chapter 4 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of

More information

Module - 19 Gated Latches

Module - 19 Gated Latches Digital Circuits and Systems Prof. Shankar Balachandran Department of Electrical Engineering Indian Institute of Technology, Bombay And Department of Computer Science and Engineering Indian Institute of

More information

ELEN Electronique numérique

ELEN Electronique numérique ELEN0040 - Electronique numérique Patricia ROUSSEAUX Année académique 2014-2015 CHAPITRE 3 Combinational Logic Circuits ELEN0040 3-4 1 Combinational Functional Blocks 1.1 Rudimentary Functions 1.2 Functions

More information

Introduction to Digital Logic

Introduction to Digital Logic Introduction to Digital Logic Lecture 17: Latches Flip-Flops Problem w/ Bistables Output should have been at end of sequence Problem: Glitch was remembered Need some way to ignore inputs until they are

More information

Memory Elements I. CS31 Pascal Van Hentenryck. CS031 Lecture 6 Page 1

Memory Elements I. CS31 Pascal Van Hentenryck. CS031 Lecture 6 Page 1 Memory Elements I CS31 Pascal Van Hentenryck CS031 Lecture 6 Page 1 Memory Elements (I) Combinational devices are good for computing Boolean functions pocket calculator Computers also need to remember

More information

Unit II Chapter 4:- Digital Logic Contents 4.1 Introduction... 4

Unit II Chapter 4:- Digital Logic Contents 4.1 Introduction... 4 Unit II Chapter 4:- Digital Logic Contents 4.1 Introduction... 4 4.1.1 Signal... 4 4.1.2 Comparison of Analog and Digital Signal... 7 4.2 Number Systems... 7 4.2.1 Decimal Number System... 7 4.2.2 Binary

More information

Gates and Flip-Flops

Gates and Flip-Flops Gates and Flip-Flops Chris Kervick (11355511) With Evan Sheridan and Tom Power December 2012 On a scale of 1 to 10, how likely is it that this question is using binary?...4? What s a 4? Abstract The operation

More information

Topic 8: Sequential Circuits. Bistable Devices. S-R Latches. Consider the following element. Readings : Patterson & Hennesy, Appendix B.4 - B.

Topic 8: Sequential Circuits. Bistable Devices. S-R Latches. Consider the following element. Readings : Patterson & Hennesy, Appendix B.4 - B. Topic 8: Sequential Circuits Bistable Devices Readings : Consider the following element Patterson & Hennesy, Appendix B.4 - B.6 Goals Basic Principles behind Memory Elements Clocks Applications of sequential

More information

Lecture 17: Designing Sequential Systems Using Flip Flops

Lecture 17: Designing Sequential Systems Using Flip Flops EE210: Switching Systems Lecture 17: Designing Sequential Systems Using Flip Flops Prof. YingLi Tian April 11, 2019 Department of Electrical Engineering The City College of New York The City University

More information

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017 UNIVERSITY OF BOLTON TW35 SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER 2-2016/2017 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002

More information

S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques

S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12]

More information

Laboratory Exercise #8 Introduction to Sequential Logic

Laboratory Exercise #8 Introduction to Sequential Logic Laboratory Exercise #8 Introduction to Sequential Logic ECEN 248: Introduction to Digital Design Department of Electrical and Computer Engineering Texas A&M University 2 Laboratory Exercise #8 1 Introduction

More information

I. Motivation & Examples

I. Motivation & Examples I. Motivation & Examples Output depends on current input and past history of inputs. State embodies all the information about the past needed to predict current output based on current input. State variables,

More information

Chapter 5 Synchronous Sequential Logic

Chapter 5 Synchronous Sequential Logic Chapter 5 Synchronous Sequential Logic Sequential circuit: A circuit that includes memory elements. In this case the output depends not only on the current input but also on the past inputs. Memory A synchronous

More information

COE 202: Digital Logic Design Sequential Circuits Part 4. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:

COE 202: Digital Logic Design Sequential Circuits Part 4. Dr. Ahmad Almulhem   ahmadsm AT kfupm Phone: Office: COE 202: Digital Logic Design Sequential Circuits Part 4 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives Registers Counters Registers 0 1 n-1 A register is a group

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 23, 2017 Energy and Power Optimization, Design Space Exploration, Synchronous MOS Logic Lecture Outline! Energy and Power Optimization

More information

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI DEPARTMENT: ECE MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 QUESTION BANK SUBJECT NAME: DIGITAL ELECTRONICS UNIT : Design of Sequential Circuits PART A ( Marks). Draw the logic diagram 4: Multiplexer.(AUC

More information

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.4-7.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html

More information

Lecture 7: Logic design. Combinational logic circuits

Lecture 7: Logic design. Combinational logic circuits /24/28 Lecture 7: Logic design Binary digital circuits: Two voltage levels: and (ground and supply voltage) Built from transistors used as on/off switches Analog circuits not very suitable for generic

More information

EE 209 Logic Cumulative Exam Name:

EE 209 Logic Cumulative Exam Name: EE 209 Logic Cumulative Exam Name: 1.) Answer the following questions as True or False a.) A 4-to-1 multiplexer requires at least 4 select lines: true / false b.) An 8-to-1 mux and no other logi can be

More information

S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques

S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12] Q.1(a) (i) Derive AND gate and OR gate

More information

Problem Set 9 Solutions

Problem Set 9 Solutions CSE 26 Digital Computers: Organization and Logical Design - 27 Jon Turner Problem Set 9 Solutions. For each of the sequential circuits shown below, draw in the missing parts of the timing diagrams. You

More information

Different encodings generate different circuits

Different encodings generate different circuits FSM State Encoding Different encodings generate different circuits no easy way to find best encoding with fewest logic gates or shortest propagation delay. Binary encoding: K states need log 2 K bits i.e.,

More information

Chapter 9 Asynchronous Sequential Logic

Chapter 9 Asynchronous Sequential Logic 9.1 Introduction EEA051 - Digital Logic 數位邏輯 Chapter 9 Asynchronous Sequential Logic 吳俊興高雄大學資訊工程學系 December 2004 Two major types of sequential circuits: depending on timing of their signals Asynchronous

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) State any two Boolean laws. (Any 2 laws 1 mark each)

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) State any two Boolean laws. (Any 2 laws 1 mark each) Subject Code: 17333 Model Answer Page 1/ 27 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model

More information

EET 310 Flip-Flops 11/17/2011 1

EET 310 Flip-Flops 11/17/2011 1 EET 310 Flip-Flops 11/17/2011 1 FF s and some Definitions Clock Input: FF s are controlled by a trigger or Clock signal. All FF s have a clock input. If a device which attempts to do a FF s task does not

More information

Konstruktion av Vippor och Latchar

Konstruktion av Vippor och Latchar Konstruktion av Vippor och Latchar Datorarkitektur 1 (1DT038) Fördjupning November 2009 karl.marklund@it.uu.se Om du läser IT (1DT038) är detta material överkurs du bör dock redan vara bekant med hur det

More information

Appendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs

Appendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs Appendix B Review of Digital Logic Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Elect. & Comp. Eng. 2 DeMorgan Symbols NAND (A.B) = A +B NOR (A+B) = A.B AND A.B = A.B = (A +B ) OR

More information

Digital Design. Sequential Logic

Digital Design. Sequential Logic Principles Of igital esign Chapter 6 Sequential Logic Chapter preview Boolean algebra 3 Logic gates and flip-flops 3 Finite-state machine 6 Logic design techniques 4 Sequential design techniques 6 Binary

More information

Chapter 3 Digital Logic Structures

Chapter 3 Digital Logic Structures Chapter 3 Digital Logic Structures Original slides from Gregory Byrd, North Carolina State University Modified by C. Wilcox, M. Strout, Y. Malaiya Colorado State University Computing Layers Problems Algorithms

More information

Vidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution

Vidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution S.E. Sem. III [ETRX] Digital Circuits and Design Prelim uestion Paper Solution. (a) Static Hazard Static hazards have two cases: static and static. static- hazard exists when the output variable should

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 18 CMOS Sequential Circuits - 1 guntzel@inf.ufsc.br

More information

Lecture 7: Sequential Networks

Lecture 7: Sequential Networks CSE 140: Components and Design Techniques for Digital Systems Lecture 7: Sequential Networks CK Cheng Dept. of Computer Science and Engineering University of California, San Diego 1 Part II: Sequential

More information

Adders, subtractors comparators, multipliers and other ALU elements

Adders, subtractors comparators, multipliers and other ALU elements CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Adders 2 Circuit Delay Transistors have instrinsic resistance and capacitance

More information

ELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)

ELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) ELEC 2200-002 Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

More information

CSE140: Components and Design Techniques for Digital Systems. Midterm Information. Instructor: Mohsen Imani. Sources: TSR, Katz, Boriello & Vahid

CSE140: Components and Design Techniques for Digital Systems. Midterm Information. Instructor: Mohsen Imani. Sources: TSR, Katz, Boriello & Vahid CSE140: Components and Design Techniques for Digital Systems Midterm Information Instructor: Mohsen Imani Midterm Topics In general: everything that was covered in homework 1 and 2 and related lectures,

More information

Roger L. Tokheim. Chapter 8 Counters Glencoe/McGraw-Hill

Roger L. Tokheim. Chapter 8 Counters Glencoe/McGraw-Hill Digital Electronics Principles & Applications Sixth Edition Roger L. Tokheim Chapter 8 Counters 2003 Glencoe/McGraw-Hill INTRODUCTION Overview of Counters Characteristics of Counters Ripple Up Counter

More information

Overview of Chapter 4

Overview of Chapter 4 Overview of hapter 4 Types of Sequential ircuits Storage Elements Latches Flip-Flops Sequential ircuit Analysis State Tables State Diagrams Sequential ircuit Design Specification Assignment of State odes

More information

Hold Time Illustrations

Hold Time Illustrations Hold Time Illustrations EE213-L09-Sequential Logic.1 Pingqiang, ShanghaiTech, 2018 Hold Time Illustrations EE213-L09-Sequential Logic.2 Pingqiang, ShanghaiTech, 2018 Hold Time Illustrations EE213-L09-Sequential

More information

Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3

Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3 Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 Basic Logic Gates XOR CMPE12 Summer 2009 02-2 Truth Table The most basic representation of a logic function Lists the output for all possible

More information

Digital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd..

Digital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd.. Indian Institute of Technology Jodhpur, Year 2017-2018 Digital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd.. Course Instructor: Shree Prakash Tiwari Email: sptiwari@iitj.ac.in

More information

Chapter 7. Sequential Circuits Registers, Counters, RAM

Chapter 7. Sequential Circuits Registers, Counters, RAM Chapter 7. Sequential Circuits Registers, Counters, RAM Register - a group of binary storage elements suitable for holding binary info A group of FFs constitutes a register Commonly used as temporary storage

More information

EECS150 - Digital Design Lecture 23 - FFs revisited, FIFOs, ECCs, LSFRs. Cross-coupled NOR gates

EECS150 - Digital Design Lecture 23 - FFs revisited, FIFOs, ECCs, LSFRs. Cross-coupled NOR gates EECS150 - Digital Design Lecture 23 - FFs revisited, FIFOs, ECCs, LSFRs April 16, 2009 John Wawrzynek Spring 2009 EECS150 - Lec24-blocks Page 1 Cross-coupled NOR gates remember, If both R=0 & S=0, then

More information

5. Sequential Logic x Computation Structures Part 1 Digital Circuits. Copyright 2015 MIT EECS

5. Sequential Logic x Computation Structures Part 1 Digital Circuits. Copyright 2015 MIT EECS 5. Sequential Logic 6.004x Computation Structures Part 1 igital Circuits Copyright 2015 MIT EECS 6.004 Computation Structures L5: Sequential Logic, Slide #1 Something We Can t Build (Yet) What if you were

More information

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Total Power. Energy and Power Optimization. Worksheet Problem 1

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Total Power. Energy and Power Optimization. Worksheet Problem 1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 20, 2018 Energy and Power Optimization, Design Space Exploration Lecture Outline! Energy and Power Optimization " Tradeoffs! Design

More information

Sequential Circuit Analysis

Sequential Circuit Analysis Sequential Circuit Analysis Last time we started talking about latches and flip-flops, which are basic one-bit memory units. Today we ll talk about sequential circuit analysis and design. First, we ll

More information

State and Finite State Machines

State and Finite State Machines State and Finite State Machines See P&H Appendix C.7. C.8, C.10, C.11 Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University Big Picture: Building a Processor memory inst register

More information

Synchronous Sequential Circuit Design. Digital Computer Design

Synchronous Sequential Circuit Design. Digital Computer Design Synchronous Sequential Circuit Design Digital Computer Design Races and Instability Combinational logic has no cyclic paths and no races If inputs are applied to combinational logic, the outputs will always

More information

Lecture 3 Review on Digital Logic (Part 2)

Lecture 3 Review on Digital Logic (Part 2) Lecture 3 Review on Digital Logic (Part 2) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ ircuit Optimization Simplest implementation ost criterion literal

More information

ALU A functional unit

ALU A functional unit ALU A functional unit that performs arithmetic operations such as ADD, SUB, MPY logical operations such as AND, OR, XOR, NOT on given data types: 8-,16-,32-, or 64-bit values A n-1 A n-2... A 1 A 0 B n-1

More information

ALU, Latches and Flip-Flops

ALU, Latches and Flip-Flops CSE14: Components and Design Techniques for Digital Systems ALU, Latches and Flip-Flops Tajana Simunic Rosing Where we are. Last time: ALUs Plan for today: ALU example, latches and flip flops Exam #1 grades

More information

University of Minnesota Department of Electrical and Computer Engineering

University of Minnesota Department of Electrical and Computer Engineering University of Minnesota Department of Electrical and Computer Engineering EE2301 Fall 2008 Introduction to Digital System Design L. L. Kinney Final Eam (Closed Book) Solutions Please enter your name, ID

More information

EE141Microelettronica. CMOS Logic

EE141Microelettronica. CMOS Logic Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit

More information

Unit 7 Sequential Circuits (Flip Flop, Registers)

Unit 7 Sequential Circuits (Flip Flop, Registers) College of Computer and Information Sciences Department of Computer Science CSC 220: Computer Organization Unit 7 Sequential Circuits (Flip Flop, Registers) 2 SR Flip-Flop The SR flip-flop, also known

More information

Chapter 13. Clocked Circuits SEQUENTIAL VS. COMBINATIONAL CMOS TG LATCHES, FLIP FLOPS. Baker Ch. 13 Clocked Circuits. Introduction to VLSI

Chapter 13. Clocked Circuits SEQUENTIAL VS. COMBINATIONAL CMOS TG LATCHES, FLIP FLOPS. Baker Ch. 13 Clocked Circuits. Introduction to VLSI Chapter 13 Clocked Circuits SEQUENTIAL VS. COMBINATIONAL CMOS TG LATCHES, FLIP FLOPS SET-RESET (SR) ARBITER LATCHES FLIP FLOPS EDGE TRIGGERED DFF FF TIMING Joseph A. Elias, Ph.D. Adjunct Professor, University

More information

Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS

Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS 1) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction (a) X -Y and (b) Y - X using 2's complements. a) X = 1010100

More information

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page 1 of 13 COE 202: Digital Logic Design (3-0-3) Term 112 (Spring 2012) Final

More information

11.1 As mentioned in Experiment 10, sequential logic circuits are a type of logic circuit where the output of

11.1 As mentioned in Experiment 10, sequential logic circuits are a type of logic circuit where the output of EE 2449 Experiment 11 Jack Levine and Nancy Warter-Perez CALIFORNIA STATE UNIVERSITY LOS ANGELES Department of Electrical and Computer Engineering EE-2449 Digital Logic Lab EXPERIMENT 11 SEQUENTIAL CIRCUITS

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Synchronous Sequential Circuits Basic Design Steps CprE 281: Digital Logic Iowa State University, Ames,

More information

Counters. We ll look at different kinds of counters and discuss how to build them

Counters. We ll look at different kinds of counters and discuss how to build them Counters We ll look at different kinds of counters and discuss how to build them These are not only examples of sequential analysis and design, but also real devices used in larger circuits 1 Introducing

More information

Week-5. Sequential Circuit Design. Acknowledgement: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA.

Week-5. Sequential Circuit Design. Acknowledgement: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA. Week-5 Sequential Circuit Design Acknowledgement: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA. Storing a value: SR = 00 What if S = 0 and R = 0? The equations on the

More information

WORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of

WORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of 27 WORKBOOK Detailed Eplanations of Try Yourself Questions Electrical Engineering Digital Electronics Number Systems and Codes T : Solution Converting into decimal number system 2 + 3 + 5 + 8 2 + 4 8 +

More information

Digital Circuits ECS 371

Digital Circuits ECS 371 Digital Circuits ECS 371 Dr. Prapun Suksompong prapun@siit.tu.ac.th Lecture 18 Office Hours: BKD 3601-7 Monday 9:00-10:30, 1:30-3:30 Tuesday 10:30-11:30 1 Announcement Reading Assignment: Chapter 7: 7-1,

More information

Fundamentals of Boolean Algebra

Fundamentals of Boolean Algebra UNIT-II 1 Fundamentals of Boolean Algebra Basic Postulates Postulate 1 (Definition): A Boolean algebra is a closed algebraic system containing a set K of two or more elements and the two operators and

More information

CS/COE1541: Introduction to Computer Architecture. Logic Design Review. Sangyeun Cho. Computer Science Department University of Pittsburgh

CS/COE1541: Introduction to Computer Architecture. Logic Design Review. Sangyeun Cho. Computer Science Department University of Pittsburgh CS/COE54: Introduction to Computer Architecture Logic Design Review Sangyeun Cho Computer Science Department Logic design? Digital hardware is implemented by way of logic design Digital circuits process

More information

CMPEN 411. Spring Lecture 18: Static Sequential Circuits

CMPEN 411. Spring Lecture 18: Static Sequential Circuits CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 18: Static Sequential Circuits [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11

More information

Philadelphia University Student Name: Student Number:

Philadelphia University Student Name: Student Number: Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2017/2018 Dept. of Computer Engineering Course Title: Logic Circuits Date: 29/01/2018

More information

CMPE12 - Notes chapter 1. Digital Logic. (Textbook Chapter 3)

CMPE12 - Notes chapter 1. Digital Logic. (Textbook Chapter 3) CMPE12 - Notes chapter 1 Digital Logic (Textbook Chapter 3) Transistor: Building Block of Computers Microprocessors contain TONS of transistors Intel Montecito (2005): 1.72 billion Intel Pentium 4 (2000):

More information

P2 (10 points): Given the circuit below, answer the following questions:

P2 (10 points): Given the circuit below, answer the following questions: P1 (10 points): Given the function f(a, b, c, d) = m(3,4,5,10,14) + D(6,7): A: Fill in the timing diagram for f. B: Implement f using only 2-1 MUXes. Your circuit should not include more than four 2-1

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified)

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) WINTER 17 EXAMINATION Subject Name: Digital Techniques Model Answer Subject Code: 17333 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given

More information

on candidate s understanding. 7) For programming language papers, credit may be given to any other program based on equivalent concept.

on candidate s understanding. 7) For programming language papers, credit may be given to any other program based on equivalent concept. WINTER 17 EXAMINATION Subject Name: Digital Techniques Model Answer Subject Code: 17333 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given

More information

Digital Electronics Sequential Logic

Digital Electronics Sequential Logic /5/27 igital Electronics Sequential Logic r. I. J. Wassell Sequential Logic The logic circuits discussed previously are known as combinational, in that the output depends only on the condition of the latest

More information

Using the NOT realization from the NAND, we can NOT the output of the NAND gate making it a NOT NOT AND or simply an AND gate.

Using the NOT realization from the NAND, we can NOT the output of the NAND gate making it a NOT NOT AND or simply an AND gate. CSC 216 NAND/NOR Equivalents and Flip/Flops Dr. Anthony S. Pyzdrowski 10/28/2016 The NAND gate is a NOT AND gate. It is false when all inputs are true and true otherwise. The NOR gate is a NOT OR gate.

More information

I. Motivation & Examples

I. Motivation & Examples I. Motivation & Examples Output depends on current input and past history of inputs. State embodies all the information about the past needed to predict current output based on current input. State variables,

More information

DIGITAL LOGIC CIRCUITS

DIGITAL LOGIC CIRCUITS DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memory Components Integrated Circuits Digital Computers 2 LOGIC GATES

More information

Reg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering

Reg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering Sp 6 Reg. No. Question Paper Code : 27156 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2015. Second Semester Computer Science and Engineering CS 6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN (Common

More information

Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing

Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing IT 204 Section 3.0 Boolean Algebra and Digital Logic Boolean Algebra 2 Logic Equations to Truth Tables X = A. B + A. B + AB A B X 0 0 0 0 3 Sum of Products The OR operation performed on the products of

More information

CPE100: Digital Logic Design I

CPE100: Digital Logic Design I Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Midterm02 Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Thursday Nov. 16 th In normal lecture (13:00-14:15)

More information