University of Minnesota Department of Electrical and Computer Engineering

Size: px

Start display at page:

Download "University of Minnesota Department of Electrical and Computer Engineering"

Merry Freeman
5 years ago
Views:

1 University of Minnesota Department of Electrical and Computer Engineering EE2301 Fall 2008 Introduction to Digital System Design L. L. Kinney Final Eam (Closed Book) Solutions Please enter your name, ID number. This eam is closed book and closed notes. Please remove all items from your desk other than pencils and eraser; this includes cell phones and calculators--no calculators or other electronic devices may be used during the eam. Show all of your work for a problem in the space provided on the eam sheet. If you need additional space, you must place a note with the problem indicating where the additional work is located. Answers without derivations are worth no credit. Please be sure that all parts of each problem have been completed. Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Problem 7 Problem 8 Total (46 pts) (35 pts) (10 pts) (16 pts) (20 pts) (20 pts) (20 pts) (20 pts) (187 pts)

2 1(46) Circle the most correct answer, T (true) or F (false), to the following statements or do not answer. The scoring is +2 for a correct answer, 0 for no answer, and -2 for an incorrect answer. a) F Clock skew is the deterioration of the rise and fall times of clock signals as they propagate throughout a digital system. b) T A gate having an inertial delay of 10ns can be used to filter out glitches if their duration is less than 10ns. c) T Metastability in the flip-flops of a sequential circuit can occur if changes in the sequential circuit inputs are not synchronized with the clock signal. d) F A multiple level combinational circuit containing only NAND gates cannot contain static-0 hazards. e) T Tri-state buses allow bidirectional communication between devices. f) T Minimal implementations of two-level multiple output circuits may use nonminimal implementations of individual outputs. g) T There are 256 different combinational functions of 3 variables. h) T A sequential circuit always contains feedback. i) F A combinational circuit never contains feedback. j) F Unstable states in an asynchronous sequential circuit almost always cause oscillations in the circuit. k) F Hazards in combinational logic can be eliminated by properly adjusting the delays in the wires and gates of the circuit. l) T Equivalent states in a sequential circuit cannot be distinguished eperimentally by observing the response of the circuit to different input sequences. m) T Eliminating equivalent states in a state table permits its realization with a minimal number of flip-flops. n) T A sequential circuit consisting of a set of interconnected Mealy model circuits may have to operate at a slower clock speed than that of the slowest Mealy model circuit which it contains. o) F Hazards must be eliminated from the combinational logic in synchronous sequential circuits in order to obtain reliable operation. p) F The major disadvantage of one s complement representation of negative numbers over two s complement is the eistence of two zeros in one s complement. q) F If m i and M j are a minterm and a materm of n-variables, where i does not equal j, then m i + M j = m i. r) T If p i and p j are distinct prime implicants of a function f of n-variables, then p i + p j cannot be a prime implicant of f. s) F Two distinct essential prime implicants of a function f cannot cover (include) the same minterm. t) T The Boolean algebra identity w+(y+z)( +z) = (w+y+z)(w+ +z) illustrates the distributive property of Boolean algebra. u) F The Boolean algebra identity yz+ yz= yz illustrates the involution property of Boolean algebra. v) T The Boolean algebra identity wy+w z+ z+yz= wy+w z+ z can be verified using the distributive, DeMorgan and consensus properties of Boolean algebra. 2

3 2(35) The SM chart below describes a sequential circuit with two inputs, A and B and three outputs, X, Y and Z. (a) The circuit is to be implemented using four D FFs with outputs Q 4, Q 3, Q 2, and Q 1. The state assignment is State Q 4 Q 3 Q 2 Q 1 S S S S S Derive FF ecitation equations and output equations. You need not draw the circuit. (b) Using the guidelines discussed in class and the tet for finding a good state assignment for sequential circuits, find a good minimal state assignment for this circuit. You can ignore the outputs and you need not give the equations, just give the state assignment. Assign all 0 s to S 0. 3

4 (a) D 1 = AQ 4 Q 3 Q 2 Q 1 + Q 4 = AQ 3 Q 2 Q 1 + Q 4 + A B Q 1 D 2 = A BQ 1 D 3 = AQ 1 D 4 = Q 3 X = Q 4 Q 3 Q 2 Q 1 + Q 3 Y = AQ 4 Q 3 Q 2 Q 1 + A BQ 1 Z = AQ 1 + A BQ 1 b. AB S0 S0 S0 S1 S1 S1 S0 S2 S3 S3 S2 S3 S2 S2 S3 S3 S4 S4 S4 S4 S4 S0 S0 S0 S0 H1: (S0,S1), (S0,S4), (S1,S4) (S0,S4), (S1,S2) (S1,S2) =(S0,S1), (S0,S4) 2, (S1,S4), (S1,S2) 2 H2: (S0,S1) 4 (S0,S2), (S0,S3) 2 (S2,S3) 4 Two possible assignments: S0 = 000 S1 = 100 S2 = 110 S3 = 010 S4 = 001 and S0 = 000 S1 = 100 S2 = 101 S3 = 001 S4 = 010 4

5 3(10) Realize an SR latch with just two components: 1) a 3-to-8 decoder with active high outputs, no enable and 2) a NOR gate with up to 8 inputs. The inputs to the NOR are the minterms of Q, S and R for which Q + is a 0. (Thinking of a NOR as an OR followed by an inverter, the output of the OR should be the complement of the function at the output of the NOR; hence, the minterms of the complement function should be ORed.) If Q, S and R are the I 2, I 1, and I 0 inputs to decoder, then Y 0, Y 1, and Y 5 from the decoder are the inputs to the NOR gate. 4(16) A positive edge-triggered, LM flip-flop operates as shown in the transition table below. L M CP Q Q LM flip-flops are to be used to implement the following transition table. Construct the ecitation table for the B FF. (You don t need the ecitation table for the A FF. AB ,-1 0-, ,1- -0,1- LA,MA AB , , , LB,MB AB

6 5(20) Construct a Mealy state diagram, with a minimum number of states, for a sequential circuit with two inputs, and y, and one output, z. At each clock time, the most-recent two inputs on is considered to be a 2-bit unsigned, binary number; similarly, the mostrecent two inputs on y is considered to be a 2-bit unsigned, binary number. (For both and y, the most recent input is the least significant bit of the two-bit number.) z is 1 if the sum of these two 2-bit numbers is divisible by 3; otherwise, z is 0. (Note: 0 is divisible by 3.) For the first and y input combination, the circuit responds as if the previous and y input combination had been 00. An eample input/output sequence is : y: z: Mealy Circuit Past Present y sum State , 1 2, 0 3, 0 2, , 0 2, 1 3, 0 2, , 0 2, 0 3, 1 2, 0 6(20) A certain EE2301 student claims that the two circuits below implement the same combinational logic function. Prove or disprove her claim. Show your derivation. Circuit on left (A + C)(B E + C ) + CDF = A B E + A C + B CE + CDF = A C + B CE + CDF (consensus of A C and B CE) Circuit on right (A + C)(B E + C + D F ) = A B E + A C + A DF + B CE + CDF = A B E + A C + B CE + CDF (consensus of A C and CDF ) = A C + B CE + CDF (consensus of A C and B CE). The two circuits implement the same function. 6

7 7(20) Find the minimal row state table that is equivalent to the one below. Show your derivation. 1 2 S ,0 5,1 4,1 1,0 2 1,1 8,0 3,1 5,1 3 6,0 5,1 4,1 1,0 4 2,0 5,1 3,1 4,0 5 2,1 5,1 3,0 7,0 6 3,1 8,0 1,1 5,1 7 1,1 6,0 4,1 5,1 8 4,1 2,0 1,1 4,1 Equivalent States: 134,26,5,7,8 1 2 S ,0 5,1 1,1 1,0 2 1,1 8,0 1,1 5,1 5 2,1 5,1 1,0 7,0 7 1,1 2,0 1,1 5,1 8 1,1 2,0 1,1 1,1 7

8 8(20) The state table below is to be implemented using a minimum number of JK flip-flops and a minimal number of gates (AND, OR and inverters). State A is the initial state and has a state assignment of all 0 s. Derive the FF ecitation equations and the output equation. 0 1 Z A B A 0 B B C 0 C C C 1 Using the state assignment A = 00, B = 01, and C = 11, the transition and output tables become 0 1 Z For JK flip-flops, the ecitation and output tables are q1q0 0 1 Z , 1-0 -, , , , - 0-0, , , J1 = q0, K1 = 0, J2 =, K2 = 0, Z = q1 Using the state assignment A = 00, B = 01, and C = 10, the transition and output tables become 0 1 Z For JK flip-flops, the ecitation and output tables are q1q0 0 1 Z , 1-0 -, , , , , , , J1 = q0, K1 = 0, J2 = q1, K2 =, Z = q1 8

Synchronous Sequential Circuit

Synchronous Sequential Circuit The change of internal state occurs in response to the synchronized clock pulses. Data are read during the clock pulse (e.g. rising-edge triggered) It is supposed to wait