LOGIC GATES. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
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1 Basic Eperiment and Design of Electronics LOGIC GATES Ho Kyung Kim, Ph.D. School of Mechanical Engineering Pusan National University
2 Outline Boolean algebra Logic gates Karnaugh maps 2
3 Analog and digital signals Analog signal An electric signal whose value varies in analogy with a physical quantity (e.g., temp., force, or acceleration) Sensitive to noise Digital signal Immune to noise 3
4 Binary signal Characterized by transitions between two states (f /f, on/off, 5 V/ V ) Knowledge of the transition between one state to another is equivalent to knowledge of the state Digital logic circuits can operate by detecting transitions (edges) between voltage levels 4
5 Binary number system bits = binary digits LSB (least significant bit), MSB (most significant bit) 8 bits = byte 6 bits = 2 bytes = word 3.25 = = = = =? =? 2 MSB LSB MSB LSB 5
6 Addition Subtraction Multiplication Division 6
7 Negative binary numbers +5, -5 2 n N +(2 n ) for n-bit signed integer words X + Y instead of X Y in digital computers Complements Ones complement a = ones complement of a = 2 4 a = Twos complement (= ones complement + ) a = ones complement of a =2 4 a = (= + ) Headecimal system,, 2,, 9, A (= ), B (= ), C (= 2), D (= 3), E (= 4), (= 5) B5 6 = = 26 7
8 E) Perform the following subtractions using the twos complement arithmetic. X Y = 2. X Y = Sol.). X Y = X + Y = = + = Since X Y <, X Y = 2. X Y = X + Y = = + = Since X Y >, X Y = 8
9 Binary codes BCD (binary-coded decimal) 39 e.g., hand calculator Gray codes Any consecutive numbers differ only by bit Effective in encoding mechanical angular position BCD code Gray code 9
10 Encoders
11 Boolean algebra Mathematics associated with the binary number system (and with the more general field of logic) Logical algebra Positive logic Logic = true, logic = false Negative logic Logic = false, logic = true Analysis of logic functions, that is, functions of logical (Boolean) variables, can be carried out in terms of truth tables Logic gates Physical devices that can be used to implement logic functions
12 Logic gates: OR, AND, NOT Logical addition Logical multiplication Logical complement 2
13 V CC +V CC Input A B Output Input A B Output V BB RB R C V CE 3
14 E) Realize the following statement with the logic gates: The output Z shall be logic only when the condition (X = AND Y = ) OR (W = ) occurs, and shall be logic otherwise 4
15 E) Realize the following statement with the logic gates: The output Z shall be logic only when the condition (X = AND Y = ) OR (W = ) occurs, and shall be logic otherwise The output Z shall be logic only when the condition ( X = AND Y = ) OR (W = ) occurs, and shall be logic otherwise 5
16 Rules of Boolean algebra rom 2: A + B C + = rom 7: A + B A + C D = A + B C D Proof of rule 6 by perfect induction (truth table) = + = (duality) 6
17 De Morgan s theorems (X + Y) = X Y (X Y) = X + Y NOR NAND Any logic gates can be implemented by using only OR and NOT gates, or only AND and NOT gates 7
18 E) Simplify the following functions f A, B, C, D = A B D + A B D + B C D + A C D Sol.) f = A D ( B + B) + B C D + A C D f = A D + B C D + A C D f = ( A + A C) D + B C D f = ( A + C) D + B C D f = A D + C D + B C D f = A D + ( + B) C D f = A D + C D f = ( A + C) D Rule 4 Rule 8 Rule 2 8
19 E) Realize the logic function described by the truth table below Sol.) y = A B C + A B C + A B C + A B C + A B C + A B C y = A C B + B + A B C + C + A B ( C + C) y = A C + A B + A B y = A C + A ( B + B) y = A C + A y = A + C 9
20 Logic gates: NAND, NOR, XOR NAND = NOT AND NOR = NOT OR Just regard this bubble as the NOT gate 2
21 AND function with NAND gates 2
22 Realization of various logic gates with only NAND gates Inverter AND OR NOR 22
23 AND function with NOR gates f = f = A B = A + B 23
24 Realization of various logic gates with only NOR gates Inverter AND OR NOR 24
25 XOR (eclusive OR) gate When its inputs are all logic s, the output is eclusively a logic ; otherwise, identical to the OR gate Z = X Y = (X + Y) (X Y) 25
26 Summary NOT 또는 inverter = ' 입력이반전되어출력 게이트이름회로기호논리식진리표 비고 buffer = 게이트이름회로기호논리식진리표 입력이그대로출력 비고 AND y = y y 입력이모두 일때출력이 NAND y = = (y)' y 입력이모두 일때에만때출력이 OR y = +y y 입력중하나라도 이면출력이 NOR y = = (+y)' y 입력중입력이하나라도모두 일때에만 이면출력이 NOT 또는 inverter = ' 입력이반전되어출력 NOT XOR 또는 (eclusive-or) inverter y = y = ' = 'y + y' y 입력이입력에반전되어 이홀수개일때출력출력이 buffer = 입력이그대로출력 XNOR (eclusive-nor) buffer 또는 equivalence y = ( y)' = = 'y'+y y 입력이입력에그대로 이짝수출개일때력출력이 NAND y = (y)' y 입력이모두 일때에만출력이 NAND y = (y)' y 입력이모두 일때에만출력이 NOR y = (+y)' y 입력이모두 일때에만출력이 NOR y = (+y)' y 입력이 26모두 일때에만출력이
27 Standard forms Sum-of-products epression Product-of-sums epression Any logical epression can be reduced to one of these two forms! 27
28 Sum-of-products OR of minterms = X Y Z + XY Z + X YZ + XY Z Products-of-sums AND of materms = (X + Y + Z)(X + Y + Z)( X + Y + Z)( X + Y + Z) X Y Z Minterm Materm X Y Z XY Z X YZ XY Z X + Y + Z X + Y + Z X + Y + Z X + Y + Z 28
29 Karnaugh maps and logic designs Karnaugh map Describing all possible combinations of the N variables present in the logic function of interest Arranging variables in a -bit change between adjacent terms 2 N cells Minterm in each cell AND-combination of the N variables in either uncomplemented or complemented form Product of the variables appearing at the corresponding vertical and horizontal coordinates Define a subcube with logical value cell 2 cells = pair 4 cells = quad 8 cells = octet 29
30 cell f = W X Y Z + W X Y Z + W X Y Z + W X Y Z + W X Y Z + W X Y Z+W X Y Z 2 cells f = W X Y + W Y Z + X Y Z + W X Y Z + W X Y Z+W X Y Z 3
31 4 cells f = W X + W Z + X Z 8 cells f = Z 3
32 E) Simplify the following logic circuit X Y Z YZ X X Z f = X + Y Z + Y Z = X + Y + Y Z = X+ Z 32
33 Sum-of-products realizations E) Design a logic circuit that implements the following truth table y = A B D + B C + C D + A D 33
34 E) Derive the truth table and minimum sum-of-products epression for the following circuit f = y + y z 34
35 Product-of-sums realization. Solve for the s eactly as for the s in sum-of-products epressions 2. Complement the resulting epression z Product-of-sums f = y z + y = y z y f = ( + y + z) ( + y) Sum-of-products f = y + y z + y 35
36 Don t care conditions Use the don t care entry with whenever it does not matter whether a position in the K- map is filled by a or a Then, can be used as either a or a, depending on which results in a greater simplification (i.e., helps in forming the smallest number of maimal subcubes) If = in the right truth table; f = B D + B C + A C D 36
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