CMSC 313 Lecture 17. Focus Groups. Announcement: in-class lab Thu 10/30 Homework 3 Questions Circuits for Addition Midterm Exam returned

Size: px
Start display at page:

Download "CMSC 313 Lecture 17. Focus Groups. Announcement: in-class lab Thu 10/30 Homework 3 Questions Circuits for Addition Midterm Exam returned"

Transcription

1 Focus Groups CMSC 33 Lecture 7 Need good sample of all types of CS students Mon /7 & Thu /2, 2:3p-2:p & 6:p-7:3p Announcement: in-class lab Thu /3 Homework 3 Questions Circuits for Addition Midterm Exam returned UMBC, CMSC33, Richard Chang <chang@umbc.edu>

2 CMSC 33, Computer Organization & Assembly Language Programming, section Fall 23 Homework 3 Due: October 3, 23. (2 points) Draw schematics for the following functions using AND, OR and NOT gates. (Do not simplify the formulas.) (a) X(Y + Z) (b) X + Y Z (c) X(Y + Z) (d) W(X + Y Z) 2. ( points) Question A.3, page 493, Murdocca & Heuring 3. ( points) Prove the Consensus Theorem AB + AC + BC = AB + AC using the postulates and theorems of Boolean algebra (except the Consensus Theorem itself) in Table A- (p. 45). Hint: use absorption creatively. 4. (4 points) For each CMOS circuit below, (a) Provide a truth table for the circuit s function. (b) For diagram (a), write down the Sum-of-Products (SOP) Boolean formula for the truth table. For diagram (b), wrtie down the Product-of-Sums (POS) Boolean formula. (c) Simplify the SOP or POS formula using the postulates and theorems of Boolean Algebra (p. 45). Show all work. (d) Draw the logic diagram of the simplified formula using AND, OR, NAND, NOR and NOT gates. +5v A +5v A B z B z C D C D GND GND (a) (b)

3 Last Time Postulates & Theorems of Boolean Algebra Periodic Table & Semiconductors P-N junction Field-Effect Transistors CMOS Logic Gates UMBC, CMSC33, Richard Chang

4 Half Adder Inputs: A and B Outputs: S = lower bit of A + B, c out = carry bit A B S c out Using Sum-of-Products: S = AB + AB, c out = AB. Alternatively, we could use XOR: S = A B.

5 Adder Inputs: A, B and c in Outputs: S = lower bit of A + B, c out = carry bit A B c in S c out S = ABC + ABC + AB C + ABC = A B C. c out = MAJ3 = AB + BC + AC. 2

6 3-6 Ripple Carry Adder Two binary numbers A and B are added from right to left, creating a sum and a carry at the outputs of each full for each bit position. b 3 a 3 c 3 b 2 a 2 c 2 b a c b a c c 4 s 3 s 2 s s

7 3-7 Constructing Larger Adders A 6-bit can be made up of a cascade of four 4-bit ripplecarry s. a 5 a 4 a 3 a 2 b 5 b 4 b 3 b 2 b 3 a 3 b 2 a 2 b a b a c 6 4-Bit Adder #3 c 2 c 4 c... 4-Bit Adder # s 5 s 4 s 3 s 2 s 3 s 2 s s

8 3-8 Subtractor Truth table and schematic symbol for a ripple-borrow subtractor: a i b i bor i diff i bor i+ b i a i bor i+ subtractor diff i (a i b i ) bori

9 3-9 Ripple-Borrow Subtractor A ripple-borrow subtractor can be composed of a cascade of full subtractors. Two binary numbers A and B are subtracted from right to left, creating a difference and a borrow at the outputs of each full subtractor for each bit position. b 3 a 3 b 2 a 2 b a b a bor subtractor subtractor subtractor subtractor bor 4 diff 3 diff 2 diff diff

10 3- Combined Adder/Subtractor A single ripple-carry can perform both addition and subtraction, by forming the two s complement negative for B when subtracting. (Note that + is added at c for two s complement.) b 3 b 2 b b ADD / SUBTRACT a 3 a 2 a a c c 4 s 3 s 2 s s

11 3-2 Carry-Lookahead Addition Carries are represented in terms of G i (generate) and P i (propagate) expressions. G i = a i b i and P i = a i + b i c = c = G c 2 = G + P G c 3 = G 2 + P 2 G + P 2 P G c 4 = G 3 + P 3 G 2 + P 3 P 2 G + P 3 P 2 P G

12 3-22 Carry Lookahead Adder b 3 a 3 b 2 a 2 b a b a G 3 P 3 G 2 P 2 G P G Maximum gate delay for the carry generation is only 3. The full s introduce two more gate delays. Worst case path is 5 gate delays. c 4 c 3 c 2 c c s 3 s 2 s s

13 In-class Labs Homework 3 due Homework 4 assigned Next Time UMBC, CMSC33, Richard Chang <chang@umbc.edu>

CMSC 313 Lecture 18 Midterm Exam returned Assign Homework 3 Circuits for Addition Digital Logic Components Programmable Logic Arrays

CMSC 313 Lecture 18 Midterm Exam returned Assign Homework 3 Circuits for Addition Digital Logic Components Programmable Logic Arrays MS 33 Lecture 8 Midterm Exam returned Assign Homework 3 ircuits for Addition Digital Logic omponents Programmable Logic Arrays UMB, MS33, Richard hang MS 33, omputer Organization & Assembly

More information

CMSC 313 Lecture 18 Midterm Exam returned Assign Homework 3 Circuits for Addition Digital Logic Components Programmable Logic Arrays

CMSC 313 Lecture 18 Midterm Exam returned Assign Homework 3 Circuits for Addition Digital Logic Components Programmable Logic Arrays CMSC 33 Lecture 8 Midterm Exam returned ssign Homework 3 Circuits for ddition Digital Logic Components Programmable Logic rrays UMC, CMSC33, Richard Chang Half dder Inputs: and Outputs:

More information

CMSC 313 Lecture 16 Postulates & Theorems of Boolean Algebra Semiconductors CMOS Logic Gates

CMSC 313 Lecture 16 Postulates & Theorems of Boolean Algebra Semiconductors CMOS Logic Gates CMSC 33 Lecture 6 Postulates & Theorems of oolean lgebra Semiconductors CMOS Logic Gates UMC, CMSC33, Richard Chang Last Time Overview of second half of this course Logic gates & symbols

More information

Combinational Logic. By : Ali Mustafa

Combinational Logic. By : Ali Mustafa Combinational Logic By : Ali Mustafa Contents Adder Subtractor Multiplier Comparator Decoder Encoder Multiplexer How to Analyze any combinational circuit like this? Analysis Procedure To obtain the output

More information

Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two.

Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two. Announcements Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two. Chapter 5 1 Chapter 3: Part 3 Arithmetic Functions Iterative combinational circuits

More information

Chapter 5 Arithmetic Circuits

Chapter 5 Arithmetic Circuits Chapter 5 Arithmetic Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 11, 2016 Table of Contents 1 Iterative Designs 2 Adders 3 High-Speed

More information

CMSC 313 Lecture 17 Postulates & Theorems of Boolean Algebra Semiconductors CMOS Logic Gates

CMSC 313 Lecture 17 Postulates & Theorems of Boolean Algebra Semiconductors CMOS Logic Gates CMSC 313 Lecture 17 Postulates & Theorems of Boolean Algebra Semiconductors CMOS Logic Gates UMBC, CMSC313, Richard Chang Last Time Overview of second half of this course Logic gates &

More information

CSE 140L Spring 2010 Lab 1 Assignment Due beginning of the class on 14 th April

CSE 140L Spring 2010 Lab 1 Assignment Due beginning of the class on 14 th April CSE 140L Spring 2010 Lab 1 Assignment Due beginning of the class on 14 th April Objective - Get familiar with the Xilinx ISE webpack tool - Learn how to design basic combinational digital components -

More information

Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.

Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr. Chapter 4 Dr. Panos Nasiopoulos Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Combinational

More information

Floating Point Representation and Digital Logic. Lecture 11 CS301

Floating Point Representation and Digital Logic. Lecture 11 CS301 Floating Point Representation and Digital Logic Lecture 11 CS301 Administrative Daily Review of today s lecture w Due tomorrow (10/4) at 8am Lab #3 due Friday (9/7) 1:29pm HW #5 assigned w Due Monday 10/8

More information

Systems I: Computer Organization and Architecture

Systems I: Computer Organization and Architecture Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept

More information

CMSC 313 Lecture 16 Announcement: no office hours today. Good-bye Assembly Language Programming Overview of second half on Digital Logic DigSim Demo

CMSC 313 Lecture 16 Announcement: no office hours today. Good-bye Assembly Language Programming Overview of second half on Digital Logic DigSim Demo CMSC 33 Lecture 6 nnouncement: no office hours today. Good-bye ssembly Language Programming Overview of second half on Digital Logic DigSim Demo UMC, CMSC33, Richard Chang Good-bye ssembly

More information

Adders - Subtractors

Adders - Subtractors Adders - Subtractors Lesson Objectives: The objectives of this lesson are to learn about: 1. Half adder circuit. 2. Full adder circuit. 3. Binary parallel adder circuit. 4. Half subtractor circuit. 5.

More information

Chapter 03: Computer Arithmetic. Lesson 03: Arithmetic Operations Adder and Subtractor circuits Design

Chapter 03: Computer Arithmetic. Lesson 03: Arithmetic Operations Adder and Subtractor circuits Design Chapter 03: Computer Arithmetic Lesson 03: Arithmetic Operations Adder and Subtractor circuits Design Objective To understand adder circuit Subtractor circuit Fast adder circuit 2 Adder Circuit 3 Full

More information

CMSC 313 Lecture 15 Good-bye Assembly Language Programming Overview of second half on Digital Logic DigSim Demo

CMSC 313 Lecture 15 Good-bye Assembly Language Programming Overview of second half on Digital Logic DigSim Demo CMSC 33 Lecture 5 Good-bye ssembly Language Programming Overview of second half on Digital Logic DigSim Demo UMC, CMSC33, Richard Chang Good-bye ssembly Language What a pain! Understand

More information

CMSC 313 Lecture 19 Combinational Logic Components Programmable Logic Arrays Karnaugh Maps

CMSC 313 Lecture 19 Combinational Logic Components Programmable Logic Arrays Karnaugh Maps CMSC 33 Lecture 9 Combinational Logic Components Programmable Logic rrays Karnaugh Maps UMC, CMSC33, Richard Chang Last Time & efore Returned midterm exam Half adders & full adders Ripple

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT2: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 4 Following the slides of Dr. Ahmed H. Madian محرم 439 ه Winter 28

More information

CMSC 313 Lecture 19 Homework 4 Questions Combinational Logic Components Programmable Logic Arrays Introduction to Circuit Simplification

CMSC 313 Lecture 19 Homework 4 Questions Combinational Logic Components Programmable Logic Arrays Introduction to Circuit Simplification CMSC 33 Lecture 9 Homework 4 Questions Combinational Logic Components Programmable Logic rrays Introduction to Circuit Simplification UMC, CMSC33, Richard Chang CMSC 33, Computer Organization

More information

UNIVERSITI TENAGA NASIONAL. College of Information Technology

UNIVERSITI TENAGA NASIONAL. College of Information Technology UNIVERSITI TENAGA NASIONAL College of Information Technology BACHELOR OF COMPUTER SCIENCE (HONS.) FINAL EXAMINATION SEMESTER 2 2012/2013 DIGITAL SYSTEMS DESIGN (CSNB163) January 2013 Time allowed: 3 hours

More information

Chapter 4: Designing Combinational Systems Uchechukwu Ofoegbu

Chapter 4: Designing Combinational Systems Uchechukwu Ofoegbu Chapter 4: Designing Combinational Systems Uchechukwu Ofoegbu Temple University Gate Delay ((1.1).1) ((1.0).0) ((0.1).1) ((0.1).0) ((1.1) = 1 0 s = sum c out carry-out a, b = added bits C = carry in a

More information

Chapter 2: Princess Sumaya Univ. Computer Engineering Dept.

Chapter 2: Princess Sumaya Univ. Computer Engineering Dept. hapter 2: Princess Sumaya Univ. omputer Engineering Dept. Basic Definitions Binary Operators AND z = x y = x y z=1 if x=1 AND y=1 OR z = x + y z=1 if x=1 OR y=1 NOT z = x = x z=1 if x=0 Boolean Algebra

More information

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18 University of Waterloo Department of Electrical & Computer Engineering E&CE 223 Digital Circuits and Systems Midterm Examination Instructor: M. Sachdev October 23rd, 2007 Total Time = 90 Minutes, Total

More information

Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions

Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions EE210: Switching Systems Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions Prof. YingLi Tian Feb. 15, 2018 Department of Electrical Engineering The City College of New York The

More information

COMBINATIONAL LOGIC FUNCTIONS

COMBINATIONAL LOGIC FUNCTIONS COMBINATIONAL LOGIC FUNCTIONS Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends only on the present

More information

Digital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits.

Digital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits. CS211 Computer Architecture Digital Logic l Topics l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Figures & Tables borrowed from:! http://www.allaboutcircuits.com/vol_4/index.html!

More information

Adders, subtractors comparators, multipliers and other ALU elements

Adders, subtractors comparators, multipliers and other ALU elements CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Adders 2 Circuit Delay Transistors have instrinsic resistance and capacitance

More information

EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits)

EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) September 5, 2002 John Wawrzynek Fall 2002 EECS150 Lec4-bool1 Page 1, 9/5 9am Outline Review of

More information

Carry Look Ahead Adders

Carry Look Ahead Adders Carry Look Ahead Adders Lesson Objectives: The objectives of this lesson are to learn about: 1. Carry Look Ahead Adder circuit. 2. Binary Parallel Adder/Subtractor circuit. 3. BCD adder circuit. 4. Binary

More information

ECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks

ECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks ECE 545 Digital System Design with VHDL Lecture Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Law Combinational

More information

Outline. EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) Combinational Logic (CL) Defined

Outline. EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) Combinational Logic (CL) Defined EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) January 30, 2003 John Wawrzynek Outline Review of three representations for combinational logic:

More information

Intro To Digital Logic

Intro To Digital Logic Intro To Digital Logic 1 Announcements... Project 2.2 out But delayed till after the midterm Midterm in a week Covers up to last lecture + next week's homework & lab Nick goes "H-Bomb of Justice" About

More information

Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary

Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary Number System Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary BOOLEAN ALGEBRA BOOLEAN LOGIC OPERATIONS Logical AND Logical OR Logical COMPLEMENTATION

More information

Total Time = 90 Minutes, Total Marks = 100. Total /10 /25 /20 /10 /15 /20

Total Time = 90 Minutes, Total Marks = 100. Total /10 /25 /20 /10 /15 /20 University of Waterloo Department of Electrical & Computer Engineering E&CE 223 Digital Circuits and Systems Midterm Examination Instructor: M. Sachdev October 30th, 2006 Total Time = 90 Minutes, Total

More information

Experiment 7: Magnitude comparators

Experiment 7: Magnitude comparators Module: Logic Design Lab Name:... University no:.. Group no: Lab Partner Name: Experiment 7: Magnitude comparators Mr. Mohamed El-Saied Objective: Realization of -bit comparator using logic gates. Realization

More information

CS 226: Digital Logic Design

CS 226: Digital Logic Design CS 226: Digital Logic Design 0 1 1 I S 0 1 0 S Department of Computer Science and Engineering, Indian Institute of Technology Bombay. 1 of 29 Objectives In this lecture we will introduce: 1. Logic functions

More information

Chapter 2: Boolean Algebra and Logic Gates

Chapter 2: Boolean Algebra and Logic Gates Chapter 2: Boolean Algebra and Logic Gates Mathematical methods that simplify binary logics or circuits rely primarily on Boolean algebra. Boolean algebra: a set of elements, a set of operators, and a

More information

Midterm Examination # 1 Wednesday, February 25, Duration of examination: 75 minutes

Midterm Examination # 1 Wednesday, February 25, Duration of examination: 75 minutes Page 1 of 10 School of Computer Science 60-265-01 Computer Architecture and Digital Design Winter 2009 Semester Midterm Examination # 1 Wednesday, February 25, 2009 Student Name: First Name Family Name

More information

KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE

KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE Estd-1984 KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE 641 006 QUESTION BANK UNIT I PART A ISO 9001:2000 Certified 1. Convert (100001110.010) 2 to a decimal number. 2. Find the canonical SOP for the function

More information

Combina-onal Logic Chapter 4. Topics. Combina-on Circuit 10/13/10. EECE 256 Dr. Sidney Fels Steven Oldridge

Combina-onal Logic Chapter 4. Topics. Combina-on Circuit 10/13/10. EECE 256 Dr. Sidney Fels Steven Oldridge Combina-onal Logic Chapter 4 EECE 256 Dr. Sidney Fels Steven Oldridge Topics Combina-onal circuits Combina-onal analysis Design procedure simple combined to make complex adders, subtractors, converters

More information

Lecture 22 Chapters 3 Logic Circuits Part 1

Lecture 22 Chapters 3 Logic Circuits Part 1 Lecture 22 Chapters 3 Logic Circuits Part 1 LC-3 Data Path Revisited How are the components Seen here implemented? 5-2 Computing Layers Problems Algorithms Language Instruction Set Architecture Microarchitecture

More information

SAMPLE ANSWERS MARKER COPY

SAMPLE ANSWERS MARKER COPY Page 1 of 12 School of Computer Science 60-265-01 Computer Architecture and Digital Design Fall 2012 Midterm Examination # 1 Tuesday, October 23, 2012 SAMPLE ANSWERS MARKER COPY Duration of examination:

More information

Overview. Arithmetic circuits. Binary half adder. Binary full adder. Last lecture PLDs ROMs Tristates Design examples

Overview. Arithmetic circuits. Binary half adder. Binary full adder. Last lecture PLDs ROMs Tristates Design examples Overview rithmetic circuits Last lecture PLDs ROMs Tristates Design examples Today dders Ripple-carry Carry-lookahead Carry-select The conclusion of combinational logic!!! General-purpose building blocks

More information

Combinational Logic Design Arithmetic Functions and Circuits

Combinational Logic Design Arithmetic Functions and Circuits Combinational Logic Design Arithmetic Functions and Circuits Overview Binary Addition Half Adder Full Adder Ripple Carry Adder Carry Look-ahead Adder Binary Subtraction Binary Subtractor Binary Adder-Subtractor

More information

Sample Test Paper - I

Sample Test Paper - I Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:

More information

Logic. Combinational. inputs. outputs. the result. system can

Logic. Combinational. inputs. outputs. the result. system can Digital Electronics Combinational Logic Functions Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Examples of Solved Problems CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander

More information

14:332:231 DIGITAL LOGIC DESIGN

14:332:231 DIGITAL LOGIC DESIGN 4:332:23 DIGITAL LOGIC DEIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 23 Lecture #4: Adders, ubtracters, and ALUs Vector Binary Adder [Wakerly 4 th Ed., ec. 6., p. 474] ingle

More information

Section 3: Combinational Logic Design. Department of Electrical Engineering, University of Waterloo. Combinational Logic

Section 3: Combinational Logic Design. Department of Electrical Engineering, University of Waterloo. Combinational Logic Section 3: Combinational Logic Design Major Topics Design Procedure Multilevel circuits Design with XOR gates Adders and Subtractors Binary parallel adder Decoders Encoders Multiplexers Programmed Logic

More information

EEE130 Digital Electronics I Lecture #4

EEE130 Digital Electronics I Lecture #4 EEE130 Digital Electronics I Lecture #4 - Boolean Algebra and Logic Simplification - By Dr. Shahrel A. Suandi Topics to be discussed 4-1 Boolean Operations and Expressions 4-2 Laws and Rules of Boolean

More information

CSE 140 Spring 2017: Final Solutions (Total 50 Points)

CSE 140 Spring 2017: Final Solutions (Total 50 Points) CSE 140 Spring 2017: Final Solutions (Total 50 Points) 1. (Boolean Algebra) Prove the following Boolean theorem using Boolean laws only, i.e. no theorem is allowed for the proof. State the name of the

More information

Digital Logic Design ENEE x. Lecture 14

Digital Logic Design ENEE x. Lecture 14 Digital Logic Design ENEE 244-010x Lecture 14 Announcements Homework 6 due today Agenda Last time: Binary Adders and Subtracters (5.1, 5.1.1) Carry Lookahead Adders (5.1.2, 5.1.3) This time: Decimal Adders

More information

Computer organization

Computer organization Computer organization Levels of abstraction Assembler Simulator Applications C C++ Java High-level language SOFTWARE add lw ori Assembly language Goal 0000 0001 0000 1001 0101 Machine instructions/data

More information

ECE 545 Digital System Design with VHDL Lecture 1A. Digital Logic Refresher Part A Combinational Logic Building Blocks

ECE 545 Digital System Design with VHDL Lecture 1A. Digital Logic Refresher Part A Combinational Logic Building Blocks ECE 545 Digital System Design with VHDL Lecture A Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Laws

More information

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.4-7.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html

More information

Combinational Logic. Course Instructor Mohammed Abdul kader

Combinational Logic. Course Instructor Mohammed Abdul kader Combinational Logic Contents: Combinational and Sequential digital circuits. Design Procedure of combinational circuit. Adders: Half adder and Full adder. Subtractors: Half Subtractor and Full Subtractor.

More information

EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive

EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive March 30, 2010 John Wawrzynek Spring 2010 EECS150 - Lec19-cl1 Page 1 Boolean Algebra I (Representations of Combinational

More information

Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 1 Gate Circuits and Boolean Equations Chapter 2 - Part 1 2 Chapter 2 - Part 1 3 Chapter 2 - Part 1 4 Chapter 2 - Part

More information

COE 202: Digital Logic Design Combinational Circuits Part 2. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:

COE 202: Digital Logic Design Combinational Circuits Part 2. Dr. Ahmad Almulhem   ahmadsm AT kfupm Phone: Office: COE 202: Digital Logic Design Combinational Circuits Part 2 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives Arithmetic Circuits Adder Subtractor Carry Look Ahead Adder

More information

Learning Objectives 10/7/2010. CE 411 Digital System Design. Fundamental of Logic Design. Review the basic concepts of logic circuits. Dr.

Learning Objectives 10/7/2010. CE 411 Digital System Design. Fundamental of Logic Design. Review the basic concepts of logic circuits. Dr. /7/ CE 4 Digital ystem Design Dr. Arshad Aziz Fundamental of ogic Design earning Objectives Review the basic concepts of logic circuits Variables and functions Boolean algebra Minterms and materms ogic

More information

Binary addition by hand. Adding two bits

Binary addition by hand. Adding two bits Chapter 3 Arithmetic is the most basic thing you can do with a computer We focus on addition, subtraction, multiplication and arithmetic-logic units, or ALUs, which are the heart of CPUs. ALU design Bit

More information

Combinational Logic. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C.

Combinational Logic. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Combinational Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2010 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Combinational Circuits

More information

Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps

Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps EE210: Switching Systems Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps Prof. YingLi Tian Feb. 21/26, 2019 Department of Electrical Engineering The City College of New York

More information

Circuits & Boolean algebra.

Circuits & Boolean algebra. Circuits & Boolean algebra http://xkcd.com/730/ CSCI 255: Introduction to Embedded Systems Keith Vertanen Copyright 2011 Digital circuits Overview How a switch works Building basic gates from switches

More information

Menu. Binary Adder EEL3701 EEL3701. Add, Subtract, Compare, ALU

Menu. Binary Adder EEL3701 EEL3701. Add, Subtract, Compare, ALU Other MSI Circuit: Adders >Binar, Half & Full Canonical forms Binar Subtraction Full-Subtractor Magnitude Comparators >See Lam: Fig 4.8 ALU Menu Look into m... 1 Binar Adder Suppose we want to add two

More information

Review for Test 1 : Ch1 5

Review for Test 1 : Ch1 5 Review for Test 1 : Ch1 5 October 5, 2006 Typeset by FoilTEX Positional Numbers 527.46 10 = (5 10 2 )+(2 10 1 )+(7 10 0 )+(4 10 1 )+(6 10 2 ) 527.46 8 = (5 8 2 ) + (2 8 1 ) + (7 8 0 ) + (4 8 1 ) + (6 8

More information

Lecture 2 Review on Digital Logic (Part 1)

Lecture 2 Review on Digital Logic (Part 1) Lecture 2 Review on Digital Logic (Part 1) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ Grading Engagement 5% Review Quiz 10% Homework 10% Labs 40%

More information

Fundamentals of Digital Design

Fundamentals of Digital Design Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric

More information

Combinational Logic. Mantıksal Tasarım BBM231. section instructor: Ufuk Çelikcan

Combinational Logic. Mantıksal Tasarım BBM231. section instructor: Ufuk Çelikcan Combinational Logic Mantıksal Tasarım BBM23 section instructor: Ufuk Çelikcan Classification. Combinational no memory outputs depends on only the present inputs expressed by Boolean functions 2. Sequential

More information

CPE100: Digital Logic Design I

CPE100: Digital Logic Design I Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Midterm01 Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Thursday Oct. 5 th In normal lecture (13:00-14:15)

More information

Switches: basic element of physical implementations

Switches: basic element of physical implementations Combinational logic Switches Basic logic and truth tables Logic functions Boolean algebra Proofs by re-writing and by perfect induction Winter 200 CSE370 - II - Boolean Algebra Switches: basic element

More information

Cs302 Quiz for MID TERM Exam Solved

Cs302 Quiz for MID TERM Exam Solved Question # 1 of 10 ( Start time: 01:30:33 PM ) Total Marks: 1 Caveman used a number system that has distinct shapes: 4 5 6 7 Question # 2 of 10 ( Start time: 01:31:25 PM ) Total Marks: 1 TTL based devices

More information

CSE140: Components and Design Techniques for Digital Systems. Logic minimization algorithm summary. Instructor: Mohsen Imani UC San Diego

CSE140: Components and Design Techniques for Digital Systems. Logic minimization algorithm summary. Instructor: Mohsen Imani UC San Diego CSE4: Components and Design Techniques for Digital Systems Logic minimization algorithm summary Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing & Dr.Pietro Mercati Definition

More information

CSE 140 Midterm I - Solution

CSE 140 Midterm I - Solution CSE 140 Midterm I - Solution 1. Answer the following questions given the logic circuit below. (15 points) a. (5 points) How many CMOS transistors does the given (unsimplified) circuit have. b. (6 points)

More information

Chapter 4: Combinational Logic Solutions to Problems: [1, 5, 9, 12, 19, 23, 30, 33]

Chapter 4: Combinational Logic Solutions to Problems: [1, 5, 9, 12, 19, 23, 30, 33] Chapter 4: Combinational Logic Solutions to Problems: [, 5, 9, 2, 9, 23, 3, 33] Problem: 4- Consider the combinational circuit shown in Fig. P4-. (a) Derive the Boolean expressions for T through T 4. Evaluate

More information

Combinational Logic. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C.

Combinational Logic. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Combinational Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Combinational Circuits

More information

ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN VALUES

ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN VALUES EC 216(R-15) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, DECEMBER- 2016 First Semester ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN

More information

Additional Gates COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals

Additional Gates COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Additional Gates COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Additional Gates and Symbols Universality of NAND and NOR gates NAND-NAND

More information

211: Computer Architecture Summer 2016

211: Computer Architecture Summer 2016 211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Review: cache hit rate - Project3 - Digital Logic: - truth table => SOP - simplification: Boolean

More information

Digital Logic. Lecture 5 - Chapter 2. Outline. Other Logic Gates and their uses. Other Logic Operations. CS 2420 Husain Gholoom - lecturer Page 1

Digital Logic. Lecture 5 - Chapter 2. Outline. Other Logic Gates and their uses. Other Logic Operations. CS 2420 Husain Gholoom - lecturer Page 1 Lecture 5 - Chapter 2 Outline Other Logic Gates and their uses Other Logic Operations CS 2420 Husain Gholoom - lecturer Page 1 Digital logic gates CS 2420 Husain Gholoom - lecturer Page 2 Buffer A buffer

More information

Module 2. Basic Digital Building Blocks. Binary Arithmetic & Arithmetic Circuits Comparators, Decoders, Encoders, Multiplexors Flip-Flops

Module 2. Basic Digital Building Blocks. Binary Arithmetic & Arithmetic Circuits Comparators, Decoders, Encoders, Multiplexors Flip-Flops Module 2 asic Digital uilding locks Lecturer: Dr. Yongsheng Gao Office: Tech 3.25 Email: Web: Structure: Textbook: yongsheng.gao@griffith.edu.au maxwell.me.gu.edu.au 6 lecturers 1 tutorial 1 laboratory

More information

COSC 243. Introduction to Logic And Combinatorial Logic. Lecture 4 - Introduction to Logic and Combinatorial Logic. COSC 243 (Computer Architecture)

COSC 243. Introduction to Logic And Combinatorial Logic. Lecture 4 - Introduction to Logic and Combinatorial Logic. COSC 243 (Computer Architecture) COSC 243 Introduction to Logic And Combinatorial Logic 1 Overview This Lecture Introduction to Digital Logic Gates Boolean algebra Combinatorial Logic Source: Chapter 11 (10 th edition) Source: J.R. Gregg,

More information

Ex: Boolean expression for majority function F = A'BC + AB'C + ABC ' + ABC.

Ex: Boolean expression for majority function F = A'BC + AB'C + ABC ' + ABC. Boolean Expression Forms: Sum-of-products (SOP) Write an AND term for each input combination that produces a 1 output. Write the input variable if its value is 1; write its complement otherwise. OR the

More information

Chapter 2 Boolean Algebra and Logic Gates

Chapter 2 Boolean Algebra and Logic Gates Chapter 2 Boolean Algebra and Logic Gates The most common postulates used to formulate various algebraic structures are: 1. Closure. N={1,2,3,4 }, for any a,b N we obtain a unique c N by the operation

More information

UNIT 4 MINTERM AND MAXTERM EXPANSIONS

UNIT 4 MINTERM AND MAXTERM EXPANSIONS UNIT 4 MINTERM AND MAXTERM EXPANSIONS Spring 2 Minterm and Maxterm Expansions 2 Contents Conversion of English sentences to Boolean equations Combinational logic design using a truth table Minterm and

More information

Digital Techniques. Figure 1: Block diagram of digital computer. Processor or Arithmetic logic unit ALU. Control Unit. Storage or memory unit

Digital Techniques. Figure 1: Block diagram of digital computer. Processor or Arithmetic logic unit ALU. Control Unit. Storage or memory unit Digital Techniques 1. Binary System The digital computer is the best example of a digital system. A main characteristic of digital system is its ability to manipulate discrete elements of information.

More information

Adders, subtractors comparators, multipliers and other ALU elements

Adders, subtractors comparators, multipliers and other ALU elements CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing

More information

CSE140: Components and Design Techniques for Digital Systems. Decoders, adders, comparators, multipliers and other ALU elements. Tajana Simunic Rosing

CSE140: Components and Design Techniques for Digital Systems. Decoders, adders, comparators, multipliers and other ALU elements. Tajana Simunic Rosing CSE4: Components and Design Techniques for Digital Systems Decoders, adders, comparators, multipliers and other ALU elements Tajana Simunic Rosing Mux, Demux Encoder, Decoder 2 Transmission Gate: Mux/Tristate

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Fast Adders CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev HW5

More information

CHAPTER1: Digital Logic Circuits Combination Circuits

CHAPTER1: Digital Logic Circuits Combination Circuits CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits Combination Circuits 1 PRIMITIVE LOGIC GATES Each of our basic operations can be implemented in hardware using a primitive logic gate.

More information

Chapter 7 Logic Circuits

Chapter 7 Logic Circuits Chapter 7 Logic Circuits Goal. Advantages of digital technology compared to analog technology. 2. Terminology of Digital Circuits. 3. Convert Numbers between Decimal, Binary and Other forms. 5. Binary

More information

PG - TRB UNIT-X- DIGITAL ELECTRONICS. POLYTECHNIC-TRB MATERIALS

PG - TRB UNIT-X- DIGITAL ELECTRONICS.   POLYTECHNIC-TRB MATERIALS SRIMAAN COACHING CENTRE-PG-TRB-PHYSICS- DIGITAL ELECTRONICS-STUDY MATERIAL-CONTACT: 8072230063 SRIMAAN PG - TRB PHYSICS UNIT-X- DIGITAL ELECTRONICS POLYTECHNIC-TRB MATERIALS MATHS/COMPUTER SCIENCE/IT/ECE/EEE

More information

Combinational Logic. Review of Combinational Logic 1

Combinational Logic. Review of Combinational Logic 1 Combinational Logic! Switches -> Boolean algebra! Representation of Boolean functions! Logic circuit elements - logic gates! Regular logic structures! Timing behavior of combinational logic! HDLs and combinational

More information

XOR - XNOR Gates. The graphic symbol and truth table of XOR gate is shown in the figure.

XOR - XNOR Gates. The graphic symbol and truth table of XOR gate is shown in the figure. XOR - XNOR Gates Lesson Objectives: In addition to AND, OR, NOT, NAND and NOR gates, exclusive-or (XOR) and exclusive-nor (XNOR) gates are also used in the design of digital circuits. These have special

More information

Logic Gate Level. Part 2

Logic Gate Level. Part 2 Logic Gate Level Part 2 Constructing Boolean expression from First method: write nonparenthesized OR of ANDs Each AND is a 1 in the result column of the truth table Works best for table with relatively

More information

Chapter 2: Switching Algebra and Logic Circuits

Chapter 2: Switching Algebra and Logic Circuits Chapter 2: Switching Algebra and Logic Circuits Formal Foundation of Digital Design In 1854 George Boole published An investigation into the Laws of Thoughts Algebraic system with two values 0 and 1 Used

More information

Principles of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents

Principles of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents B-1 Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix B: Reduction of Digital Logic B-2 Chapter Contents B.1 Reduction of Combinational Logic and Sequential Logic B.2 Reduction

More information

Boolean Algebra & Logic Gates. By : Ali Mustafa

Boolean Algebra & Logic Gates. By : Ali Mustafa Boolean Algebra & Logic Gates By : Ali Mustafa Digital Logic Gates There are three fundamental logical operations, from which all other functions, no matter how complex, can be derived. These Basic functions

More information

Digital Logic (2) Boolean Algebra

Digital Logic (2) Boolean Algebra Digital Logic (2) Boolean Algebra Boolean algebra is the mathematics of digital systems. It was developed in 1850 s by George Boole. We will use Boolean algebra to minimize logic expressions. Karnaugh

More information

Digital System Design Combinational Logic. Assoc. Prof. Pradondet Nilagupta

Digital System Design Combinational Logic. Assoc. Prof. Pradondet Nilagupta Digital System Design Combinational Logic Assoc. Prof. Pradondet Nilagupta pom@ku.ac.th Acknowledgement This lecture note is modified from Engin112: Digital Design by Prof. Maciej Ciesielski, Prof. Tilman

More information