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1 Hold Time Illustrations EE213L09Sequential Logic.1 Pingqiang, ShanghaiTech, 2018
2 Hold Time Illustrations EE213L09Sequential Logic.2 Pingqiang, ShanghaiTech, 2018
3 Hold Time Illustrations EE213L09Sequential Logic.3 Pingqiang, ShanghaiTech, 2018
4 Hold Time Illustrations EE213L09Sequential Logic.4 Pingqiang, ShanghaiTech, 2018
5 Hold Time Illustrations EE213L09Sequential Logic.5 Pingqiang, ShanghaiTech, 2018
6 Outline Sequential logics and their timing metrics Storage mechanisms Static latch/register (flipflop) Dynamic latch/register Other latches/registers TSPC latch/register Pulsetriggered latch EE213L09Sequential Logic.6 Pingqiang, ShanghaiTech, 2018
7 Dynamic Register master slave D A Q T 1 I M B 1 T 2 I 2 Q master transparent slave hold C 1 C 2 t su = t hold = t cq = t pd_tx zero 2t pd_inv + t pd_tx master hold slave transparent EE213L09Sequential Logic.7 Pingqiang, ShanghaiTech, 2018
8 PseudoStatic Dynamic Latch Robustness considerations limit the use of dynamic FF s coupling between signal nets and internal storage nodes can inject significant noise and destroy the FF state leakage currents cause state to leak away with time A simple fix is to make the circuit pseudostatic Q M B C 2 Q EE213L09Sequential Logic.8 Pingqiang, ShanghaiTech, 2018
9 Dynamic FlipFlop Race Conditions master slave D Q M A T 1 I 1 T B 2 I 2 Q C 1 C overlap race condition t overlap00 < t T1 + t I1 + t T2 11 overlap race condition t overlap11 < t hold EE213L09Sequential Logic.9 Pingqiang, ShanghaiTech, 2018
10 Fix 1: Dynamic TwoPhase FlipFlop master slave 1 2 D Q T 1 I M 1 T 2 I 2 Q 1 C 1 C 2 2 master transparent slave hold 1 2 t non_overlap master hold slave transparent EE213L09Sequential Logic.10 Pingqiang, ShanghaiTech, 2018
11 Fix 2: Dynamic C 2 MOS (Clocked CMOS) FlipFlop A clockskew insensitive FF Master Slave M 2 M 6 D M 4 M 3 Q M C 1 M 8 M 7 C 2 Q M 1 M 5 EE213L09Sequential Logic.11 Pingqiang, ShanghaiTech, 2018
12 C 2 MOS FlipFlop A clockskew insensitive FF Master Slave M 2 M 6 D off off M 4 M 3 on on Q M C 1 on on M 8 M 7 off off C 2 Q M 1 M 5 master transparent slave hold master hold slave transparent EE213L09Sequential Logic.12 Pingqiang, ShanghaiTech, 2018
13 C 2 MOS FlipFlop: 00 Overlap Case Master Slave M 2 M 6 D M 4 M 3 Q M C 1 M 8 M 7 C 2 Q M 1 M 5 EE213L09Sequential Logic.13 Pingqiang, ShanghaiTech, 2018
14 C 2 MOS FlipFlop: 00 Overlap Case Clockskew insensitive as long as the rise and fall times of the clock edges are sufficiently small M 2 M 6 D 0 0 M 4 Q M C 1 M 8 C 2 Q M 1 M 5 EE213L09Sequential Logic.14 Pingqiang, ShanghaiTech, 2018
15 C 2 MOS FlipFlop: 11 Overlap Case Master Slave M 2 M 6 D M 4 M 3 Q M C 1 M 8 M 7 C 2 Q M 1 M 5 EE213L09Sequential Logic.15 Pingqiang, ShanghaiTech, 2018
16 C 2 MOS FlipFlop: 11 Overlap Case M 2 M 6 D Q M 1 1 C 1 M 3 M 7 C 2 Q M 1 M overlap constraint t overlap11 < t hold EE213L09Sequential Logic.16 Pingqiang, ShanghaiTech, 2018
17 Outline Sequential logics and their timing metrics Storage mechanisms Static latch/register (flipflop) Dynamic latch/register Other latches/registers TSPC latch/register Pulsetriggered latch EE213L09Sequential Logic.17 Pingqiang, ShanghaiTech, 2018
18 True Single Phase Clock (TSPC) Latches Positive Latch (Transparent when CLK=1) Negative Latch (Transparent when CLK=0) EE213L09Sequential Logic.18 Pingqiang, ShanghaiTech, 2018
19 Including Logic in TSPC NAND2 Latch EE213L09Sequential Logic.19 Pingqiang, ShanghaiTech, 2018
20 TSPC Register EE213L09Sequential Logic.20 Pingqiang, ShanghaiTech, 2018
21 Outline Sequential logics and their timing metrics Storage mechanisms Static latch/register (flipflop) Dynamic latch/register Other latches/registers TSPC latch/register Pulsetriggered latch EE213L09Sequential Logic.21 Pingqiang, ShanghaiTech, 2018
22 PulseTriggered Latches: An Alternative Approach Ways to design an edgetriggered sequential cell: Data MasterSlave Latches D Q D Q PulseTriggered Latch L1 L2 L Data D Q Clk Clk Clk Clk Clk EE213L09Sequential Logic.22 Pingqiang, ShanghaiTech, 2018
23 How to Generate Pulse? EE213L09Sequential Logic.23 Pingqiang, ShanghaiTech, 2018
24 Why not Route the Pulse? EE213L09Sequential Logic.24 Pingqiang, ShanghaiTech, 2018
25 Summary: Three Sequencing Methods EE213L09Sequential Logic.25 Pingqiang, ShanghaiTech, 2018
26 Choosing a Clocking Strategy Choosing the right clocking scheme affects the functionality, speed, and power of a circuit Twophase designs + robust and conceptually simple   need to generate and route two clock signals have to design to accommodate possible skew between the two clock signals Single phase designs + only need to generate and route one clock signal + supported by most automated design methodologies + don t have to worry about skew between the two clocks  have to have guaranteed slopes on the clock edges EE213L09Sequential Logic.26 Pingqiang, ShanghaiTech, 2018
27 Next Lecture and Reminders Next lecture Timing Chapter 10 Chapter 9/12 EE213L09Sequential Logic.27 Pingqiang, ShanghaiTech, 2018
28 Further Reading EE213L09Sequential Logic.28 Pingqiang, ShanghaiTech, 2018
29 More Complicated Latches: CrossCoupled NORBased SR Latch ActiveHIGH input NANDBased SR Latch EE213L09Sequential Logic.29 Pingqiang, ShanghaiTech, 2018
30 CrossCoupled Register Gated SR Latch Gated D Latch JK FlipFlop D FlipFlop Ronald J. Tocci, et al., Digital Systems Principles and Applications, 11 th ed., Prentice Hall, EE213L09Sequential Logic.30 Pingqiang, ShanghaiTech, 2018
31 NonBistable Sequential Circuits Schmitt Trigger V out V OH In O u t VTC with hysteresis Restores signal slopes V OL V M V M+ V in EE213L09Sequential Logic.31 Pingqiang, ShanghaiTech, 2018
32 Noise Suppression using Schmitt Trigger EE213L09Sequential Logic.32 Pingqiang, ShanghaiTech, 2018
33 CMOS Schmitt Trigger V DD M 2 M 4 V in X V out M 1 M 3 Moves switching threshold of the first inverter EE213L09Sequential Logic.33 Pingqiang, ShanghaiTech, 2018
34 MultiVibrator Circuits R S B i s t a b l e M u l t i v i b r a t o r f l i p  f l o p, S c h m i t t T r i g g e r T M o n o s t a b l e M u l t i v i b r a t o r o n e  s h o t A s t a b l e M u l t i v i b r a t o r o s c i l l a t o r EE213L09Sequential Logic.34 Pingqiang, ShanghaiTech, 2018
35 TransitionTriggered Monostable In D E L A Y O u t t d t d EE213L09Sequential Logic.35 Pingqiang, ShanghaiTech, 2018
36 Astable Multivibrators (Oscillators) N1 Ring Oscillator Simulated response of 5stage oscillator EE213L09Sequential Logic.36 Pingqiang, ShanghaiTech, 2018
37 Voltage Controller Oscillator (VCO) S c h m i t t T r i g g e r V D D V D D r e s t o r e s s i g n a l s l o p e s M 6 M 4 M 2 In M 1 I ref I ref V c o n t r M 5 M 3 C u r r e n t s t a r v e d i n v e r t e r 6 t p H L ( n s e c ) V c o n t r ( V ) p r o p a g a t i o n d e l a y a s a f u n c t i o n o f c o n t r o l v o l t a g e EE213L09Sequential Logic.37 Pingqiang, ShanghaiTech, 2018
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