Digital Logic and Design (Course Code: EE222) Lecture 1 5: Digital Electronics Fundamentals. Evolution of Electronic Devices

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Indian Institute of Technolog Jodhpur, Year 207 208 Digital Logic and Design (Course Code: EE222) Lecture 5: Digital Electronics Fundamentals Course Instructor: Shree Prakash Tiwari Email:

1 Indian Institute of Technolog Jodhpur, Year Digital Logic and Design (Course Code: EE222) Lecture 5: Digital Electronics Fundamentals Course Instructor: Shree Prakash Tiwari Office: 20, Phone: 296 Webpage: Course related documents will be uploaded on Note: The information provided in the slides are taken form tet books Digital Electronics (including Mano & Ciletti), and various other resources from internet, for teaching/academic use onl Evolution of Electronic Devices 2

2 Integrated Circuits 22 nm CMOS 3 Before Electronics Era 4 2

After Electronics Revolution http://www.

3 After Electronics Revolution 5 There are two wa of representing the numerical value of quantities: analog digital 3

4 Analog representation: A quantit is represented b a voltage, current or meter movement that is proportional to the value of that quantit Eample : Automobile speedometer Audio microphone Analog quantities can var over a continuous range of values Digital representation: The quantities are represented not b proportional quantities but b smbols called digits Eample :. Digital watch It provides the time of da in the form of decimal digits which represent hours and minutes (and sometimes seconds) The digital representation of the time of da changes in discrete steps 4

5 Advantages of Digital Techniques. Digital sstems are easier to design as circuits used are onl switching circuits having onl HIGH and LOW range 2. Information storage is eas. 3. Accurac and precision are greater 4. Operation can be programmed. 5. Digital circuits are less affected b noise, as the spurious fluctuation in voltage (noise) are not as critical in digital sstems became the eact value of a voltage is not important. Limitation of Digital Techniques The real world is mainl analog Digital Logic and Design Course Contents: Number sstem: binar numbers, s and 2s complement, arithmetic operations in integer and floating point sstems; ASCII, binar and gra codes; Boolean algebra: Boolean Equations, Minimization of Boolean functions; Designing i combinational Circuits it using gates and/or Multipleers l Combinational circuit: Adder, decoder, multipleers, code converters (binar, gra and BCD); Sequential circuit: Bistable, Monostable, latches and flip flops, counters (binar, ring and Johnson), shift register, timer circuits; Hardware Description Languages: Combinational Logic, Structural Modeling, Sequential Logic, More Combinational Logic, Finite State Machines, Parameterized Modules, Testbenches Digital IC families: DTL, TTL, ECL, MOS, CMOS and theirinterfacing. ADC and DAC: Sample and hold circuits, ADCs, DACs. Memories: semiconductor memories, PALs, PLAs and FPGAs; Pipelining and timing issues, PROMs; 0 5

6 Digital Logic and Design Laborator: Laborator will contain eperiments from following topics: i) Familiarization with logic gates and logic building. ii) Encoders and decoders iii) Adder circuits: half adder and full adder iv) Flip flops and counters v) Latches and memories vi) Seven segment displa vii) Arithmetic logic circuits viii) Digital to analog converters i) Analog to digital converters ) Serial communication i) AND, OR and EX_ OR gates using Nand (7400) gates; BCD to 6 3 Code converter; 6 3 to Gra Code converter; full adder circuit using AND, OR and XOR gates; a 4 Bit comparator using logic gates; Pseudo random bit generator; 4 bit ripple carr adder; Master Slave J K Flip Flop using Logic gates; Bi directional counter using J K Flip flops; Priorit encoder, multipleer and decoder; VHDL code for simulation of a 4 Bit fast look ahead carr adder; VHDL code for simulation of an 8 bit signed integer multiplier. Digital Logic and Design. M. Morris Mano, Michael D. Ciletti, "Digital Design: With an Introduction to the Verilog HDL", 5th edition, Prentice Hall of India, Ronald J. Tocci, Neal Widmer, Greg Moss, Digital Sstems: Principles and Applications, 0th edition, Pearson, D. M. Harris and S. L. Harris, Digital Design and Computer Architecture, Second Edition, Morgan Kuffmann,

7 Design Hierarch SYSTEM + MODULE GATE CIRCUIT S n+ G DEVICE D n+ 3 Digital Number Sstem Man number sstems are in use in digital technolog The most common are Decimal Binar Octal Headecimal 7

8 Numbers Ever number sstem is associated with a base or radi A positional notation is commonl used to epress numbers ( aaaaaa) r ar ar ar ar ar ar The decimal sstem has a base of 0 and uses smbols (0,,2,3,4,5,6,7,8,9) to represent numbers (2009) (23.24) An octal number sstem has a base 8 and uses smbols (0,,2,3,4,5,6,7) (2007) What decimal number does it represent? (2007) A headecimal sstem has a base of 6 Number Smbol A B 2 C 3 D 4 E 5 F (2 BC 9) 2 6 B 6 C How do we convert it into decimal number? 0 (2BC9)

9 Eample : the number Most Significant Bit (MSB) Binar Point Least Significant Bit (LSB) A Binar sstem has a base 2 and uses onl two smbols 0, to represent all the numbers 2 0 (0) Which decimal number does this correspond to? 0 (0) (K) (M)

10 Converting decimal to binar number Convert 45 to binar number (45) bb... b 0 n n 0 n 45 b 2 b 2... b 2 b n n n 0 Divide both sides b 2 45 n n b 2 n b n 2... b 2 b b 2 b 2... b 2 b 0.5 n n n 2 0 n 0 b b 2 b 2... b 2 b 0.5 b0 n n n 2 0 n 0 22 b 2 b 2... b 2 b 2 n n n 2 0 n 2 Divide both sides b n n bn bn... b2 2 b 0.5 b 0 2 b 2 b 2... b 2 b 2 n n 2 n 3 0 n b 2 b 2... b 2 0.5b b2 n n 3 n 4 0 n b 2 b 2... b 2 b 2 n n 3 n 4 0 n 4 3 0

11 5 b 2 b 2... b 2 b 2 n n 3 n 4 0 n b 2 b 2... b 2 0.5b b3 n n 4 n 5 0 n b 2 b 2... b 2 b 2 n n 4 n 5 0 n 5 4 b 2 b 2... b 2 0.5b b4 0 n n 5 n 6 0 n 5 4 b 5 (45) bbbbbb Converting decimal to binar number Method of successive division b 2 45 remainder =

12 Convert (53) 0 to octal number sstem Divide both sides b 8 (53) ( bb... b) 0 n n 0 8 (53) b 8 b 8... b8 b n n 0 n n 0 53 n n 2 0 b0 b bn8 bn 8... b b remainder = (23) 8 Converting decimal to binar number Convert (0.35) 0 to binar number (0.35) 0 0. b b 2b 3... b n b 2 b 2... b 2 n 2 2 n How do we find the b b 2 coefficients? Multipl both sides b b b 2... b 2 n b 0 2 n 0.7 b 2 b 2... b 2 n n 2

13 0.7 b 2 b 2... b 2 n n Multipl both sides b 2.4 b b 2... b 2 n n Note that ½+/4+/8+ b b 2 b 2... b 2 n n 3 b b 0 3 b 4 b n n Converting decimal to binar number 0.25 =? 0.25 = (.00) =? = (.0)

14 Binar numbers Most significant bit or MSB 0000 Least significant bit or LSB This is a 0 bit number decimal 2bit 3bit 4bit 5bit Binar digit = bit N bit binar number can represent numbers from 0 to 2 N Converting Binar to He and He to Binar ( bbbbbbbb) ( h, h) b 0 He b 2 b 2 b 2 b 2 b 2 b 2 b 2 b h6 h ( b 2 b 2 b 2 b )2 ( b 2 b 2 b 2 b ) h6 h h h0 (000) (0)(00) ( B 3) b (00) ()(00) (33) b He He Number Smbol 0(0000) 0 (000) 2(000) 2 3(00) 3 4(000) 4 5(00) 5 6(00) 6 7(0) 7 8(000) 8 9(00) 9 0(00) A (0) B 2(00) C 3(0) D 4(0) E 5() F ( EC) (0)(00) (000) He b 4

15 Binar Addition/Subtraction Complement of a number 9 s complement Decimal sstem: 0 s complement 9 s complement of n digit number is 0 n 0 s complement of n digit number is 0 n 9 s complement of 85? 's complement of 23 = 's complement of 23 = 9's complement of

16 Complement of a binar number Binar sstem: s complement 2 s complement s complement of n bit number is 2 n 2 s complement of n bit number is 2 n s complement of 0? s complement is simpl obtained b flipping a bit (changing to 0 and 0 to ) 's complement of 000 =? 's complement of 00 = 's complement of 's complement of 000 = Leave all least significant 0s 0 s as the are, leave first unchanged and then flip all subsequent bits

17 Advantages of using 2 s complement 2 Adder S CY Can we carr out Y = X X 2 using such an adder? 2, 2 : N bit numbers S Y = S if Sign = 0 Y = 2's Complement of S if Sign = Y 2 2's Complement Adder CY Sign = 0 for positive psotive numbers = for negative numbers Sign 2 N 2 ( CY, S) 2 N 2 Note that carr will be there onl if 2 is positive as 2 N is N+ bits ( followed b N zeros) Advantages of using 2 s complement, 2 : N bit numbers S Y = S if Sign = 0 Y = 2's Complement of S if Sign = Y Adder 2's Complement CY Sign 2 Sign = 0 for positive psotive numbers = for negative numbers 2 N 2 ( CY, S) 2 N 2 Note that carr will be there onl if 2 is positive as 2 N is N+ bits ( followed b N zeros) A zero carr implies a negative number whose magnitude ( 2 ) can be found as follows: S 2 N 2 N 2'scomplement of S 2 ( 2 ) N 2 2 7

18 Eample = S Y = S if Sign = 0 Y = 2's Complement of S if Sign = 000 Y 2 =00 6 2's Complement 00 Adder CY Sign Sign = 0 for positive psotive numbers = for negative numbers Eample = S Y = S if Sign = 0 Y = 2's Complement of S if Sign = 000 Y 2 =00 2's Complement 0 00 Adder CY Sign 0 Sign = 0 for positive psotive numbers = for negative numbers It makes sense to use adder as a subtractor as well provided additional circuit required for carring out 2 s complement is simple 8

19 Subtraction using 0 s complement, 2 : N digit numbers 8 2 0's Complement 3 0 3=7 Adder 5 S CY Y = S if Sign = 0 Y = 0's Complement of S if Sign = Sign = 0 for positive psotive numbers = for negative numbers 5 Y Sign 0 This wa of subtraction would make sense onl if subtracting a number 2 from 0 N is much simpler than directl subtracting it directl from Representing positive and negative binar numbers One etra bit is required to carr sign information. Sign bit = 0 represents positive number and Sign bit = represents negative number decimal Signed Magnitude decimal Signed s complement decimal Signed 2 s complement

20 If we represent numbers in 2 s complement form carring out subtraction is same as addition, 2 : N bit numbers S Y = S if Sign = 0 Y = 2's Complement of S if Sign = Y Adder 2's Complement CY Sign 2 Sign = = 00 for for positive psotive numbers = for negative numbers S Answer is in 2 s complement form 2 Adder CY, 2 : N bit numbers in 2's complement Eample S 2 Adder CY,, 2 : N bit numbers in 2's complement s complement is 00 = 3 2 s complement is 0 = 7 20

21 CODES When numbers, letters or words are represented b a special group of smbols, we sa that the are being encoded and the group of smbols is called code. Binar Coded Decimal Code (BCD) If each digit of a decimal number is represented b its binar equivalent, the result is a code called binarcoded decimal. Since a decimal digit can be as large as 9, 4 bits are required to code each digit. E. 874 = (BCD) 2

22 Gra code It belongs to a class of codes called minimum change codes, in which onl one bit in the code groups changes when going from one stage to the net. The Gra code is an unweighted code. So, this code is not suited for arithmetic operation but finds application in input/output devices and some tpes of Analog to Digital i Converters (ADCs). Binar Equivalent Gra Code

23 Alphanumeric Codes An alphanumeric code represents all of the various characters and functions that are found in a standard tpewriter (or computer) keboard. ASCII Code: The most widel used alphanumeric code, the American standard code for Information Interchange as is used in most micro computers and minicomputers and in man mainframes. The ASCII code is a 7 bit code and so it has 2 7 =28 possible code groups. Character 7- Bit ASCII He A B C Z 000 5A a, b, blank, etc. 23

24 Eample : When writing a BASIC Programme, instruction GO TO 25 G 0000 O 000 T O is added because the codes must be stored as btes (8bits). This adding of an etra bit is called padding with 0s. Boolean Algebra Algebra on Binar numbers A variable can take two values {0,} 0 False No Basic operations: AND: =. 2 Y is if and onl if both and 2 are, otherwise zero Low voltage True Yes High voltage 2 Truth Table

25 Basic operations: OR: = + 2 Y is if either and 2 is. Or = 0 if and onl if both variables are zero NOT: = 0 0 Boolean Algebra Basic Postulates P: + 0 = P2: + = + P3:.(+z) = +z.+.z P4: + = P:. = P2:. =. P3: +.z = (+).(+z)(+z) P4:. = 0 Basic Theorems T: + = T2: + = T3: ( ) = T4: + (+z) = (+)+z T5 (+) =. (DeMorgan's theorem) T6: +. = T:. = T2:. 0 = 0 T4:. (.z) = (.).z T5 (.) = + (DeMorgan's theorem) T6:.( +) = 25

26 Proving theorems P: + 0 = P2: + = + P3:.(+z) =.+.z P4: + = P:. = P2:. =. P3: +.z = (+).(+z) P4:. = 0 Prove T: + = Prove T:. = + = (+). (P). =.+ 0 (P) = (+). (+) (P4) = +. (P3) = + 0 (P4) = (P) =. +. (P4) =. (+ ) (P3) =. (P4) = (P) Proving theorems P: + 0 = P2: + = + P3:.(+z) =.+.z P4: + = P:. = P2:. =. P3: +.z = (+).(+z) P4:. = 0 Prove : + = + = +(+ ) = (+)+ = + = +. = =. +. =. (+ ) =. = +. = + = ( + ). (+ ) =. (+ ) = + DeMorgan s theorem ( ) (.....) ( )

27 Simplification of Boolean epressions (.. )? ( ) (.....) ( ) ( ). ( + ) Function of Boolean variables = Y = when is 0 and 2 is =. 2 Boolean epression 27

28 Obtaining Boolean epressions from truth Table = = = Obtaining Boolean epressions from truth Table = Instead of writing epressions as sum of terms that make equal to, we can also write epressions using terms that make equal to 0 = = 2 28

29 = = =( ).( ) 2 2 Obtaining Boolean epressions from truth Table 2 3 = Sum of Products (SOP) form =( ).( ).( ).( ) Product of Sum (POS) form 29

30 Implementing Boolean epressions Elementar Gates AND: =. 2 2 AND Wh call it a gate? AND = 0 0 Gate is closed AND = Gate is open OR: = OR NOT: = NAND: =. 2 2 AND NAND NOR: = OR NOR 30

31 XOR: = = Y is if onl one variable is and the other is zero XOR 2 XNOR: = = XNOR Y is if onl both variables are either 0 or = 2= 2 Gates with more than 2 inputs AND: = AND OR: = XOR: = = Y = onl if odd number of inputs is 3

32 Implementing Boolean epressions using gates z S C S z.. z.. z.. z.. C. z.. z z z z z z z z z z S z z C Implementing gates using Switches Voltage controlled Switch SN: SN Switch is closed if voltage is HIGH Switch is open if voltage is LOW Voltage controlled Switch SP: SP Switch is closed if voltage is LOW Switch is open if voltage is HIGH Transistors act as switches! 32

33 SN SP Switch is closed if voltage is HIGH Switch is open if voltage is LOW Switch is closed if voltage is LOW Switch is open if voltage is HIGH V DD = 5V closed SP LOW 0 SN open HIGH NOT gate NAND Gate NAND: =. 2 V DD = 5V 2 SP SP SN 2 LOW LOW HIGH LOW HIGH HIGH HIGH LOW HIGH 2 HIGH HIGH LOW SN 33

34 NOR Gate NOR: = + 2 V DD = 5V SP 2 LOW LOW HIGH 2 SP LOW HIGH HIGH HIGH LOW HIGH LOW LOW LOW 2 SN SN Design Overview a b c Full Adder S CY S z.. z.. z.. z.. C. z.. z a b c S CY V DD = 5V z z z z z z z z z S z z C 2 SP SN SN 2 SP SP SN 34

35 Digital Cont.. What net 69 35

DIGITAL LOGIC CIRCUITS

DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memor Components Integrated Circuits BASIC LOGIC BLOCK - GATE - Logic