ECE 545 Digital System Design with VHDL Lecture 1A. Digital Logic Refresher Part A Combinational Logic Building Blocks

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1 ECE 545 Digital System Design with VHDL Lecture A Digital Logic Refresher Part A Combinational Logic Building Blocks

2 Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Laws Combinational Logic Building Blocks Multiplexers Decoders, Demultiplexers Encoders, Priority Encoders Multipliers Shifters, Rotators 2

3 Textbook References Combinational Logic Review Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 3 rd or 2 nd Edition Chapter 2 Introduction to Logic Circuits ( only) Chapter 6 Combinational-Circuit Building Blocks ( only) OR your undergraduate digital logic textbook (chapters on combinational logic) 3

4 Basic Logic Review some slides modified from: S. Dandamudi, Fundamentals of Computer Organization and Design 4

5 Rules If you believe that you know a correct answer, please raise your hand I will select one or more students (independently whether an answer given by the first student is correct or incorrect) Please, identify yourself by first name and give an answer Correct answer = bonus point 5

6 Problem List all 2-input logic gates that you can recall

7 Basic Logic Gates (2-input versions) 7

8 Problem 2 How would you generalize the definitions of 2-input logic gates to N-input logic gates?

9 Basic Logic Gates Generalized Simple logic gates AND à if one or more inputs is, otherwise AND à if all inputs are, otherwise OR à if one or more inputs is, otherwise OR à if all inputs are, otherwise NAND = AND + NOT if one or more inputs is, otherwise if all inputs are, otherwise NOR = OR + NOT if one or more input is, otherwise if all inputs are, otherwise XOR à if an odd number of inputs is, otherwise XNOR à if an even number of inputs is, otherwise NAND and NOR gates require fewer transistors than AND and OR in standard CMOS 9

10 Problem 3 How many 2-input logic functions can be theoretically defined (whether they make sense or not)? How many N-input logic functions can be theoretically defined (whether they make sense or not)?

11 Number of Functions Number of functions With N logical variables, we can define 2 2N functions Some of them are useful AND, NAND, NOR, XOR, Some are not useful: Output is always Output is always Number of functions definition is useful in proving completeness property

12 Problem 4 List all -input logic gates.

13 Problem 5 What is a minimum set of gates that can be used to implement any logic function?

14 Complete Set of Gates Complete sets A set of gates is complete if we can implement any logic function using only the type of gates in the set Some example complete sets {AND, OR, NOT} {AND, NOT} {OR, NOT} {NAND} {NOR} Minimal complete set A complete set with no redundant elements. Not a minimal complete set 4

15 NAND as a Complete Set Proving NAND gate is universal 5

16 Problem 6 List four ways of expressing logic functions.

17 Logic Functions Logic functions can be expressed in several ways: Truth table Logical expressions Graphical schematic form HDL code Example: Majority function Output is one whenever majority of inputs is We use 3-input majority function 7

18 Alternative Representations of Logic Function Truth table A B C F Logical expression form F = A B + B C + A C Graphical schematic form HDL code: F <= (A AND B) OR (B AND C) OR (A AND C) ; 8

19 Boolean Algebra Boolean identities Name AND version OR version Identity x. = x x + = x Complement x. x = x + x = Commutative x. y = y. x x + y = y + x Distribution x. (y+z) = xy+xz x + (y. z) = (x+y) (x+z) Idempotent x. x = x x + x = x Null x. = x + = 9

20 Problem 7 Prove the OR version of the Boolean Distribution identity: x + (y z) = (x+y) (x+z)

22 Boolean Algebra (cont d) Boolean identities (cont d) Name AND version OR version Involution x = (x ) --- Absorption x. (x+y) = x x + (x. y) = x Associative x. (y. z) = (x. y). z x + (y + z) = (x + y) + z 22

23 Problem 8 What are the De Morgan s Laws? Write their equations and draw their schematic representation.

24 De Morgan s Laws Name AND version OR version de Morgan (x. y) = x + y (x + y) = x. y 24

25 Alternative symbols for NAND and NOR 25

26 Deriving Equivalent Expressions Using NAND gates Get an equivalent expression A B + C D = (A B + C D) Using de Morgan s law A B + C D = ( (A B). (C D) ) Can be generalized Example: Majority function A B + B C + AC = ((A B). (B C). (AC) ) 26

27 Majority Function Using AND, OR, NOT 27

28 Majority Function Using NAND 28

29 Majority Function Using NAND 29

30 Combinational Logic Building Blocks Some slides modified from: S. Dandamudi, Fundamentals of Computer Organization and Design S. Brown and Z. Vranesic, "Fundamentals of Digital Logic" 3

31 Problem 9 How many select inputs does an 8-to- MUX have? How many select inputs does an n-to- MUX have?

32 Multiplexers log 2 n selection inputs n inputs output multiplexer n binary inputs (binary input = -bit input) log 2 n binary selection inputs binary output Function: one of n inputs is placed onto output Called n-to- multiplexer 32

33 2-to- Multiplexer s s f w w f w w (a) Graphical symbol (b) Truth table w w s f s w w f (c) Sum-of-products circuit (d) Circuit with transmission gates Source: Brown and Vranesic 33

34 4-to- Multiplexer s s s s f w w w 2 w 3 f w w w 2 w 3 (a) Graphic symbol (b) Truth table s s w w f w 2 w 3 Source: Brown and Vranesic (c) Circuit 34

35 Multi-bit 4-to- Multiplexer s s s s f w w w 2 w f w w w 2 w 3 (a) Graphic symbol (b) Truth table When drawing schematics, can draw multi-bit multiplexers Example: 8-bit 4-to- multiplexer 4 inputs (each 8 bits) output (8 bits) 2 selection bits Can also have multi-bit 2-to- muxes, 6-to- muxes, etc. 35

36 8-bit 4-to- Multiplexer s s w (7) w (7) w 2 (7) w 3 (7) f(7) s s w w w 2 w 3 8 f = 8 s s w (6) w (6) w 2 (6) w 3 (6) f(6) An 8-bit 4-to- multiplexer is composed of eight [-bit] 4-to- multiplexers s s w () w () w 2 () w 3 () f() 36

37 Problem How many outputs does a decoder with two data inputs have? How many outputs does a decoder with n data inputs have?

38 Decoders n inputs w y 2 n w n- 2 n outputs Enable En y Decoder n binary inputs 2 n binary outputs Function: decode encoded information If enable=, one output is asserted high, the other outputs are asserted low If enable=, all outputs asserted low Often, enable pin is not needed (i.e. the decoder is always enabled) Called n-to-2 n decoder Can consider n binary inputs as a single n-bit input Can consider 2 n binary outputs as a single 2 n -bit output Decoders are often used for RAM/ROM addressing 38

39 2-to-4 Decoder En w w y 3 y 2 y y - - w En y 3 w y 2 y y (a) Truth table (b) Graphical symbol w y w y y 2 y 3 En Source: Brown and Vranesic (c) Logic circuit 39

40 Problem Show how to implement a decoder that recognizes the following 4 ranges of a 6-bit address A, and generates the corresponding enable signals e,e,e2,e3: For A in: C-CFFF: D-DFFF: E-EFFF: F-FFFF: Assert e e e2 e3

43 Demultiplexers log 2 n selection inputs input n outputs Demultiplexer binary input n binary outputs log 2 n binary selection inputs Function: places input onto one of n outputs, with the remaining outputs asserted low Called -to-n demultiplexer Closely related to decoder Can build -to-n demultiplexer from log 2 n-to-n decoder by using the decoder's enable signal as the demultiplexer's input signal, and using decoder's input signals as the demultiplexer's selection input signals. 43

44 -to-4 Demultiplexer 44

45 Problem 2 How many inputs does an encoder with two data outputs have? How many inputs does an encoder with n data outputs have?

46 Encoders 2 n inputs w 2 n w y y n n outputs Encoder 2 n binary inputs n binary outputs Function: encodes information into an n-bit code Called 2 n -to-n encoder Can consider 2 n binary inputs as a single 2 n -bit input Can consider n binary output as a single n-bit output Encoders only work when exactly one binary input is equal to 46

47 4-to-2 Encoder w 3 w 2 w w y y (a) Truth table w w y w 2 w 3 y (b) Circuit 47

48 Problem 3 What is a difference between encoder and priority encoder?

49 Priority Encoders 2 n inputs w 2 n w y n n outputs y z "valid" output Priority Encoder 2 n binary inputs n binary outputs binary "valid" output Function: encodes information into an n-bit code based on priority of inputs Called 2 n -to-n priority encoder Priority encoder allows for multiple inputs to have a value of '', as it encodes the input with the highest priority (e.g., MSB = highest priority, LSB = lowest priority) "valid" output indicates when priority encoder output is valid Priority encoder is more common than an encoder 49

50 5 4-to-2 MSB Priority Encoder - w y - y z w - - w 2 - w 3

51 Problem 4 Show how to implement a 4-to-2 MSB Priority Encoder using multiplexers and a minimum number of logic gates

53 Problem 5 What is the width of an output of a 4x4 unsigned multiplier? What is the width of an output of a 4x4 signed multiplier? What is the width of an output of a NxN unsigned multiplier?

54 4x4-bit Unsigned Multiplier 4 4 a * c b U 8 54

55 4x4-bit Signed Multiplier 4 4 a * c b S 8 55

56 Problem 6 What is the width of an output of a 4x8 unsigned multiplier? What is the width of an output of a 4x8 signed multiplier? What is the width of an output of a NxM unsigned multiplier?

57 Problem 7 Give an example of binary inputs to an unsigned 4x4 multiplier and a signed 4x4 multiplier that produce different results.

58 Unsigned vs. Signed Multiplication Unsigned Signed 5 - x x 5 x x

59 Problem 8 Explain the difference between logic shift right and arithmetic shift right What arithmetic operations these shifts correspond to?

60 Logical Shift Right A >> C 4 4 L A(3) A(2) A() A() A(3) A(2) A() A C 6

61 Arithmetic Shift Right A >> C 4 4 A A(3) A(2) A() A() A C A(3) A(3) A(2) A() 6

62 Fixed Rotation A 4 <<< A(3) A(2) A() A() A C 4 C A(2) A() A() A(3) 62

63 8-bit Variable Rotator Left A 8 3 B A <<< B C 8 63

64 Problem 9 Explain using simple diagrams (based on medium-scale logic components) how to efficiently perform the following operations in hardware using combinational logic only A. C = A <<< 3 B. C = A <<< B, where A and C are 6-bit variables and B is a 4-bit variable

65 Fixed rotation C = A <<< 3 a(5) a(4) a(3) a(2) a() a() a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a() a() <<< 3 a(2) a() a() a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a() a() a(5) a(4) a(3) 65

66 Variable rotation C = A <<< B

ECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks

ECE 545 Digital System Design with VHDL Lecture Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Law Combinational