04. What is the Mod number of the counter circuit shown below? Assume initially reset.

Size: px
Start display at page:

Download "04. What is the Mod number of the counter circuit shown below? Assume initially reset."

Transcription

1 . Which of the following is the state diagram for the Meale machine shown below. 4. What is the Mod number of the counter circuit shown below? Assume initiall reset. input CLK D output D D a. b. / / / / / / / a. 2 b. 3 c. 4 4.Ans: c CLK 5. The circuit shown below works as c. / / / / 2: S d. / / / / / a. Positive level triggered D Flip flop b. Negative level triggered D Flip flop c. Positive level triggered T Flip flop. Ans: a 2. Minimum number of :4 Demultipleers required to design a decoder a. 85 b. 64 c. 2 d. decoder can t be designed with DE. 2. Ans: a 3. How man k 4 ROM s are required to design a 6 k 6 ROM? a. 64 b. 6 c Ans: a 5 Ans: b 6. Minimum number of 2 input NAND gates required to implement the Boolean function A B O AB a. 23 b. 24 c Ans: 7. The simplified Boolean epression for function F(A,B,C,D) shown in the k map is C C

2 a. AB C D AB C D b. AB C D A B C D c. AB C D AB C D 7. Ans: 8. The transistor circuit shown below & are outputs of transistors & 2 respectivel. 5V 5V 2 { If (B = ) then = If (B = ) then = } If (A = ) { If (B = ) then = If (B = ) then = } The Boolean epression for is given b a. A+B b. A B A B c. AB A B. Ans: b The relation between and is a. = b. c. + = d. + = 8. Ans: d 9. f = khz T T Schmitt fout Trigger. How man TTL open collector NAND gates are required to implement Boolean f A B. C D. function a. 2 b. 3 c. 6. Ans: a 2. N inverters are connected in a Ring. 2 3 N In the above circuit, a sinusoidal input of frequenc khz is given as input to Schmitt trigger. The frequenc f out is a. 5 khz b. 2kHz c. 2.5kHz 9. Ans: c. Consider the software code implemented on a computer. It is required to design an equivalent digital Hardware for the software code. A B If (A = ) then Digital Hardware Each inverter has a propagation dela of ns. The above circuit works an a. Oscillator if N is odd & frequenc of 5 operation is MHz N b. Oscillator if N is even & frequenc of 5 operation is MHz N c. Oscillator if N is odd & frequenc of operation is MHz N 2. Ans: a

3 3. Valid Ecess code 5. J = ns S ns 4 Bit Ripple carr Adder c = K = ns R Clk = In the circuit shown above: 4bit valid Ecess 3 is given as input and the output is valid 4 bit BCD code. In order to perform such an operation value of should be a. b. c. d. 3. Ans: b Valid BCD code Propagation dela of flip flop & AND gate is ns each. In the above circuit J & K are connected to an clock input is made alwas HIGH making the circuit operate in Race around condition. What is the frequenc of oscillation at the pin? a. 5MHz b MHz c. 25MHz d MHz 5.Ans: c c i : carr s i : sum 6. A Fair die is rolled. The face value of the die in encoded into 3bit binar. For eample: {, 2, } Full Adder Adder circuit dealing with 2 s complement numbers. In the above circuit, the output V is when a. c 2 = c 3 b. c 2 c3 c. c 3 + c 2 = 4. Ans: b c 2 Full Full Adder Adder c = s 2 c 3 c 2 c s Overflow detector s V Face value of die The output of encoder is given to a full adder circuit. What is the probabilit that carr = & sum =? a..25 b..5 c..75 d. 6. Ans: b 7. +5V R encoder (t) Full adder Carr Sum C (t) (t) ns 2 ns t In the above circuit (t) is input, (t) is the output. The Fourier transform of the output (t) is

4 a. sinc function with zero crossing at f = MHz, 2MHz, 3 MHZ b. sinc function at zero crossing f = 5MHz, MHz, 5 MHZ c. Rectangle function of the above. 7. Ans: 8. Given the following k-map which one of the following represents minimal sum-of products of the map. W Z a. z b. w z c. w z d. z 8. Ans: 9. Which of the following are essential Prime Implicants in the Boolean epression AB AC BC a. AB, A C b. AB, AC, BC c. A C, BC d. AB, BC 2. Statement I: In a Meale machine the present output depends onl on the present state Statement II: In Moore machine the present outputs depends on present state as well as present input a. both S and S 2 are true b. S is true S 2 false c. S is false and S 2 is true d. Neither S nor S 2 is true 2. Ans: d 22. The minimum decimal equivalent of (23D) is a. 69 b. 67 c. 59 d Ans: c 23. Function f(a) is defined as f(a) = 2 s complement of A then f[f(f(f(a)))] = a. A b. A c. d. 23. Ans: a 24. If f(a, B,C) = [A B] C, then f C,A B,A is a. A B C b. A B C c. A C B 24. Ans: a 9. Ans: a 2. The characteristic equation of T Flip flop is given b 25. A B a. (n+) = T+ T b. n T T c. (n+) = T d. none of the above 2. Ans: C For the venn diagram shown above, the equivalent function for the shaded region is a. A B C b. A B c. A B 25. Ans:

5 26. Match the following Column - A P.. ABC Z R. Column B : 2: 2: Match column A with column B a. P 3 2 R b. P 3 R 2 c. P 2 3 R 26. Ans: The above circuit implements a. Binar to Gra code conversion b. Gra to Binar code conversion c. BCD to Ecess-3 code conversion 27. Ans: a 28. CLK 2 bit free running counter 2 4 Decoder 2 The counter is free running up counter starting at. The digital to analog converter equation is given b V VR 2 d3 2 d2 2 d 2 d. The sequence of output voltages generated b DAC is a. b. 8V 4V 2V V V 2V 4V 8V A A 3 d 3 d 2 d d V R = 6V Digital to Analog Converter V 27. The following data is stored in ROM c. V 2V 3V 4V A B C ROM Z 28. Ans: a

6 Directions: The following 29 & 3 questions consists of two statements, one labeled the Assertion A and the other labeled the Reason R. our are to eamine these two statements carefull and decide if the Assertion A and the Reason R are eplanation of the Assertion. Select our answer to these its using the codes given below and mark our answer sheet accordingl Codes : a) both A and R are true and R is the correct eplanation of A b) both A and R are true but R is not a correct eplanation of A c) A is false and R is true d) A is true and R is false 29. Assertion (A) : N bit flash ADC is faster than N bit successive approimation ADC Reason (R) : Flash ADC uses 2 n comparators in parallel. 29. Ans: 3. Assertion (A): Emitter coupled logic circuit have ver less propagation delas. Reason (R): ECL is unsaturated logic famil. 3. Ans: A

WORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of

WORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of 27 WORKBOOK Detailed Eplanations of Try Yourself Questions Electrical Engineering Digital Electronics Number Systems and Codes T : Solution Converting into decimal number system 2 + 3 + 5 + 8 2 + 4 8 +

More information

Sample Test Paper - I

Sample Test Paper - I Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:

More information

S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques

S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12]

More information

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page 1 of 13 COE 202: Digital Logic Design (3-0-3) Term 112 (Spring 2012) Final

More information

Combinational Logic. By : Ali Mustafa

Combinational Logic. By : Ali Mustafa Combinational Logic By : Ali Mustafa Contents Adder Subtractor Multiplier Comparator Decoder Encoder Multiplexer How to Analyze any combinational circuit like this? Analysis Procedure To obtain the output

More information

Lecture 7: Logic design. Combinational logic circuits

Lecture 7: Logic design. Combinational logic circuits /24/28 Lecture 7: Logic design Binary digital circuits: Two voltage levels: and (ground and supply voltage) Built from transistors used as on/off switches Analog circuits not very suitable for generic

More information

BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO

BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO UN IVERSIT Y O F CA LIFO RNI A AT BERKELEY BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO SAN TA BARBA RA S AN TA CRUZ De p a r tm en t of Ele ctr i ca l En gin e e rin g a

More information

KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE

KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE Estd-1984 KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE 641 006 QUESTION BANK UNIT I PART A ISO 9001:2000 Certified 1. Convert (100001110.010) 2 to a decimal number. 2. Find the canonical SOP for the function

More information

DIGITAL LOGIC CIRCUITS

DIGITAL LOGIC CIRCUITS DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memor Components Integrated Circuits BASIC LOGIC BLOCK - GATE - Logic

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified)

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) WINTER 17 EXAMINATION Subject Name: Digital Techniques Model Answer Subject Code: 17333 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given

More information

on candidate s understanding. 7) For programming language papers, credit may be given to any other program based on equivalent concept.

on candidate s understanding. 7) For programming language papers, credit may be given to any other program based on equivalent concept. WINTER 17 EXAMINATION Subject Name: Digital Techniques Model Answer Subject Code: 17333 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given

More information

vidyarthiplus.com vidyarthiplus.com vidyarthiplus.com ANNA UNIVERSITY- COMBATORE B.E./ B.TECH. DEGREE EXAMINATION - JUNE 2009. ELECTRICAL & ELECTONICS ENGG. - FOURTH SEMESTER DIGITAL LOGIC CIRCUITS PART-A

More information

LOGIC CIRCUITS. Basic Experiment and Design of Electronics

LOGIC CIRCUITS. Basic Experiment and Design of Electronics Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output

More information

LOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.

LOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D. Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor

More information

Final Exam. ECE 25, Spring 2008 Thursday, June 12, Problem Points Score Total 90

Final Exam. ECE 25, Spring 2008 Thursday, June 12, Problem Points Score Total 90 Final Exam ECE 25, Spring 2008 Thursday, June 12, 2008 Name: PID: Problem Points Score 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 10 Total 90 1) Number representation (10 pts) a) For each binary vector

More information

Reg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering

Reg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering Sp 6 Reg. No. Question Paper Code : 27156 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2015. Second Semester Computer Science and Engineering CS 6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN (Common

More information

Fundamentals of Digital Design

Fundamentals of Digital Design Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric

More information

Lab 3 Revisited. Zener diodes IAP 2008 Lecture 4 1

Lab 3 Revisited. Zener diodes IAP 2008 Lecture 4 1 Lab 3 Revisited Zener diodes R C 6.091 IAP 2008 Lecture 4 1 Lab 3 Revisited +15 Voltage regulators 555 timers 270 1N758 0.1uf 5K pot V+ V- 2N2222 0.1uf V o. V CC V Vin s = 5 V Vc V c Vs 1 e t = RC Threshold

More information

Digital Logic and Design (Course Code: EE222) Lecture 1 5: Digital Electronics Fundamentals. Evolution of Electronic Devices

Digital Logic and Design (Course Code: EE222) Lecture 1 5: Digital Electronics Fundamentals. Evolution of Electronic Devices Indian Institute of Technolog Jodhpur, Year 207 208 Digital Logic and Design (Course Code: EE222) Lecture 5: Digital Electronics Fundamentals Course Instructor: Shree Prakash Tiwari Email: sptiwari@iitj.ac.in

More information

CPE100: Digital Logic Design I

CPE100: Digital Logic Design I Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Final Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Tuesday Dec 12 th 13:00-15:00 (1-3pm) 2 hour

More information

SUMMER 18 EXAMINATION Subject Name: Principles of Digital Techniques Model Answer Subject Code:

SUMMER 18 EXAMINATION Subject Name: Principles of Digital Techniques Model Answer Subject Code: Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) State any two Boolean laws. (Any 2 laws 1 mark each)

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) State any two Boolean laws. (Any 2 laws 1 mark each) Subject Code: 17333 Model Answer Page 1/ 27 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model

More information

ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN VALUES

ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN VALUES EC 216(R-15) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, DECEMBER- 2016 First Semester ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN

More information

Appendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs

Appendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs Appendix B Review of Digital Logic Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Elect. & Comp. Eng. 2 DeMorgan Symbols NAND (A.B) = A +B NOR (A+B) = A.B AND A.B = A.B = (A +B ) OR

More information

CpE358/CS381. Switching Theory and Logical Design. Class 2

CpE358/CS381. Switching Theory and Logical Design. Class 2 CpE358/CS38 Switching Theor and Logical Design Class 2 CpE358/CS38 Switching Theor and Logical Design Summer- 24 Copright 24 Stevens Institute of Technolog -45 Toda s Material Fundamental concepts of digital

More information

(Boolean Algebra, combinational circuits) (Binary Codes and -arithmetics)

(Boolean Algebra, combinational circuits) (Binary Codes and -arithmetics) Task 1. Exercises: Logical Design of Digital Systems Seite: 1 Self Study (Boolean Algebra, combinational circuits) 1.1 Minimize the function f 1 a ab ab by the help of Boolean algebra and give an implementation

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC - 27001-2005 Certified) Subject Code: 12069 SUMMER 13 EXAMINATION Model Answer Important Instructions to examiners: 1) The answers should

More information

DIGITAL LOGIC CIRCUITS

DIGITAL LOGIC CIRCUITS DIGITAL LOGIC CIRCUITS Digital logic circuits BINARY NUMBER SYSTEM electronic circuits that handle information encoded in binary form (deal with signals that have only two values, and ) Digital. computers,

More information

EECS150 - Digital Design Lecture 23 - FSMs & Counters

EECS150 - Digital Design Lecture 23 - FSMs & Counters EECS150 - Digital Design Lecture 23 - FSMs & Counters April 8, 2010 John Wawrzynek Spring 2010 EECS150 - Lec22-counters Page 1 One-hot encoding of states. One FF per state. State Encoding Why one-hot encoding?

More information

Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3

Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3 Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 Basic Logic Gates XOR CMPE12 Summer 2009 02-2 Truth Table The most basic representation of a logic function Lists the output for all possible

More information

Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.

Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr. Chapter 4 Dr. Panos Nasiopoulos Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Combinational

More information

S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques

S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12] Q.1(a) (i) Derive AND gate and OR gate

More information

Chapter 4. Sequential Logic Circuits

Chapter 4. Sequential Logic Circuits Chapter 4 Sequential Logic Circuits 1 2 Chapter 4 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of

More information

MODEL ANSWER SUMMER 17 EXAMINATION Subject Title: Principles of Digital Techniques

MODEL ANSWER SUMMER 17 EXAMINATION Subject Title: Principles of Digital Techniques MODEL ANSWER SUMMER 17 EXAMINATION Subject Title: Principles of Digital Techniques Subject Code: Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word

More information

Shift Register Counters

Shift Register Counters Shift Register Counters Shift register counter: a shift register with the serial output connected back to the serial input. They are classified as counters because they give a specified sequence of states.

More information

COMBINATIONAL LOGIC FUNCTIONS

COMBINATIONAL LOGIC FUNCTIONS COMBINATIONAL LOGIC FUNCTIONS Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends only on the present

More information

DIGITAL LOGIC CIRCUITS

DIGITAL LOGIC CIRCUITS DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memory Components Integrated Circuits Digital Computers 2 LOGIC GATES

More information

Vidyalankar S.E. Sem. III [EXTC] Digital Electronics Prelim Question Paper Solution ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD = B

Vidyalankar S.E. Sem. III [EXTC] Digital Electronics Prelim Question Paper Solution ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD = B . (a). (b). (c) S.E. Sem. III [EXTC] igital Electronics Prelim Question Paper Solution ABC ABC ABC ABC ABC ABC ABC ABC = B LHS = ABC ABC ABC ABC ABC ABC ABC ABC But ( ) = = ABC( ) ABC( ) ABC( ) ABC( )

More information

EECS150 - Digital Design Lecture 18 - Counters

EECS150 - Digital Design Lecture 18 - Counters EECS150 - Digital Design Lecture 18 - Counters October 24, 2002 John Wawrzynek Fall 2002 EECS150 - Lec18-counters Page 1 Counters Special sequential circuits (FSMs) that sequence though a set outputs.

More information

EECS150 - Digital Design Lecture 18 - Counters

EECS150 - Digital Design Lecture 18 - Counters EECS50 - Digital Design Lecture 8 - Counters October 24, 2002 John Wawrzynek Fall 2002 EECS50 - Lec8-counters Page Counters Special sequential circuits (FSMs) that sequence though a set outputs. Examples:

More information

Sequential Logic Circuits

Sequential Logic Circuits Chapter 4 Sequential Logic Circuits 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of a sequential circuit,

More information

Chapter 7 Logic Circuits

Chapter 7 Logic Circuits Chapter 7 Logic Circuits Goal. Advantages of digital technology compared to analog technology. 2. Terminology of Digital Circuits. 3. Convert Numbers between Decimal, Binary and Other forms. 5. Binary

More information

Vidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution

Vidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution . (a) (i) ( B C 5) H (A 2 B D) H S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution ( B C 5) H (A 2 B D) H = (FFFF 698) H (ii) (2.3) 4 + (22.3) 4 2 2. 3 2. 3 2 3. 2 (2.3)

More information

Schedule. ECEN 301 Discussion #25 Final Review 1. Date Day Class No. 1 Dec Mon 25 Final Review. Title Chapters HW Due date. Lab Due date.

Schedule. ECEN 301 Discussion #25 Final Review 1. Date Day Class No. 1 Dec Mon 25 Final Review. Title Chapters HW Due date. Lab Due date. Schedule Date Day Class No. Dec Mon 25 Final Review 2 Dec Tue 3 Dec Wed 26 Final Review Title Chapters HW Due date Lab Due date LAB 8 Exam 4 Dec Thu 5 Dec Fri Recitation HW 6 Dec Sat 7 Dec Sun 8 Dec Mon

More information

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web:     Ph: Serial : S_CS_C_Digital Logic_588 Delhi Noida hopal Hyderabad Jaipur Lucknow Indore Pune hubaneswar Kolkata Patna Web: E-mail: info@madeeasy.in Ph: -56 CLASS TEST 8-9 COMPUTER SCIENCE & IT Subject : Digital

More information

Adders, subtractors comparators, multipliers and other ALU elements

Adders, subtractors comparators, multipliers and other ALU elements CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Adders 2 Circuit Delay Transistors have instrinsic resistance and capacitance

More information

Synchronous Sequential Circuit Design. Digital Computer Design

Synchronous Sequential Circuit Design. Digital Computer Design Synchronous Sequential Circuit Design Digital Computer Design Races and Instability Combinational logic has no cyclic paths and no races If inputs are applied to combinational logic, the outputs will always

More information

Systems I: Computer Organization and Architecture

Systems I: Computer Organization and Architecture Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept

More information

Exam for Physics 4051, October 31, 2008

Exam for Physics 4051, October 31, 2008 Exam for Physics 45, October, 8 5 points - closed book - calculators allowed - show your work Problem : (6 Points) The 4 bit shift register circuit shown in Figure has been initialized to contain the following

More information

Fundamentals of Computer Systems

Fundamentals of Computer Systems Fundamentals of Computer Systems Review for the Final Stephen A. Edwards Columbia University Summer 25 The Final 2 hours 8 problems Closed book Simple calculators are OK, but unnecessary One double-sided

More information

Adders, subtractors comparators, multipliers and other ALU elements

Adders, subtractors comparators, multipliers and other ALU elements CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing

More information

Lecture 9: Digital Electronics

Lecture 9: Digital Electronics Introduction: We can classify the building blocks of a circuit or system as being either analog or digital in nature. If we focus on voltage as the circuit parameter of interest: nalog: The voltage can

More information

DE58/DC58 LOGIC DESIGN DEC 2014

DE58/DC58 LOGIC DESIGN DEC 2014 Q.2 a. In a base-5 number system, 3 digit representations is used. Find out (i) Number of distinct quantities that can be represented.(ii) Representation of highest decimal number in base-5. Since, r=5

More information

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering TIMING ANALYSIS Overview Circuits do not respond instantaneously to input changes

More information

EECS150 - Digital Design Lecture 17 - Sequential Circuits 3 (Counters)

EECS150 - Digital Design Lecture 17 - Sequential Circuits 3 (Counters) EECS150 - Digital Design Lecture 17 - Sequential Circuits 3 (Counters) March 19&21, 2002 John Wawrzynek Spring 2002 EECS150 - Lec13-seq3 version 2 Page 1 Counters Special sequential circuits (FSMs) that

More information

University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering

University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Examination ECE 241F - Digital Systems Examiners: J. Rose and

More information

ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter. Lab 3. Lab 3 Gate Timing. Lab 3 Steps in designing a State Machine. Timing diagram of a DFF

ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter. Lab 3. Lab 3 Gate Timing. Lab 3 Steps in designing a State Machine. Timing diagram of a DFF ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter Timing diagram of a DFF Lab 3 Gate Timing difference timing for difference kind of gate, cost dependence (1) Setup Time = t2-t1 (2) Propagation

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) SUMMER 14 EXAMINATION Model Answer

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) SUMMER 14 EXAMINATION Model Answer MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC 27001 2005 Certified) SUMMER 14 EXAMINATION Model Answer Subject Code : 17320 Page No: 1/34 Important Instructions to examiners: 1)

More information

Cs302 Quiz for MID TERM Exam Solved

Cs302 Quiz for MID TERM Exam Solved Question # 1 of 10 ( Start time: 01:30:33 PM ) Total Marks: 1 Caveman used a number system that has distinct shapes: 4 5 6 7 Question # 2 of 10 ( Start time: 01:31:25 PM ) Total Marks: 1 TTL based devices

More information

Boolean Algebra. Digital Logic Appendix A. Postulates, Identities in Boolean Algebra How can I manipulate expressions?

Boolean Algebra. Digital Logic Appendix A. Postulates, Identities in Boolean Algebra How can I manipulate expressions? Digital Logic Appendix A Gates Combinatorial Circuits Sequential Circuits Other operations NAND A NAND B = NOT ( A ANDB) = AB NOR A NOR B = NOT ( A ORB) = A + B Truth tables What is the result of the operation

More information

Digital Logic Appendix A

Digital Logic Appendix A Digital Logic Appendix A Boolean Algebra Gates Combinatorial Circuits Sequential Circuits 1 Boolean Algebra George Boole ideas 1854 Claude Shannon, apply to circuit design, 1938 Describe digital circuitry

More information

Written exam with solutions IE Digital Design Friday 21/

Written exam with solutions IE Digital Design Friday 21/ Written exam with solutions IE204-5 Digital Design Friday 2/0 206 09.00-3.00 General Information Examiner: Ingo Sander. Teacher: Kista, William Sandvist tel 08-7904487, Elena Dubrova phone 08-790 4 4 Exam

More information

EECS150 - Digital Design Lecture 16 Counters. Announcements

EECS150 - Digital Design Lecture 16 Counters. Announcements EECS150 - Digital Design Lecture 16 Counters October 20, 2011 Elad Alon Electrical Engineering and Computer Sciences University of California, Berkeley http://www-inst.eecs.berkeley.edu/~cs150 Fall 2011

More information

Mealy & Moore Machines

Mealy & Moore Machines Mealy & Moore Machines Moore Machine is a finite-state machine whose output values are determined solely by its current state and can be defined as six elements (S, S 0, Σ, Λ, T, G), consisting of the

More information

Chapter 7. Sequential Circuits Registers, Counters, RAM

Chapter 7. Sequential Circuits Registers, Counters, RAM Chapter 7. Sequential Circuits Registers, Counters, RAM Register - a group of binary storage elements suitable for holding binary info A group of FFs constitutes a register Commonly used as temporary storage

More information

Digital Electronics Final Examination. Part A

Digital Electronics Final Examination. Part A Digital Electronics Final Examination Part A Spring 2009 Student Name: Date: Class Period: Total Points: /50 Converted Score: /40 Page 1 of 13 Directions: This is a CLOSED BOOK/CLOSED NOTES exam. Select

More information

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1> Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building

More information

Philadelphia University Student Name: Student Number:

Philadelphia University Student Name: Student Number: Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2017/2018 Dept. of Computer Engineering Course Title: Logic Circuits Date: 29/01/2018

More information

XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.

XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL. 2017-18 XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL HALF ADDER 1. The circuit that performs addition within the Arithmetic and Logic Unit of the CPU are called adders. 2. A unit that adds two

More information

211: Computer Architecture Summer 2016

211: Computer Architecture Summer 2016 211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Review: cache hit rate - Project3 - Digital Logic: - truth table => SOP - simplification: Boolean

More information

Written reexam with solutions for IE1204/5 Digital Design Monday 14/

Written reexam with solutions for IE1204/5 Digital Design Monday 14/ Written reexam with solutions for IE204/5 Digital Design Monday 4/3 206 4.-8. General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned

More information

Total Time = 90 Minutes, Total Marks = 100. Total /10 /25 /20 /10 /15 /20

Total Time = 90 Minutes, Total Marks = 100. Total /10 /25 /20 /10 /15 /20 University of Waterloo Department of Electrical & Computer Engineering E&CE 223 Digital Circuits and Systems Midterm Examination Instructor: M. Sachdev October 30th, 2006 Total Time = 90 Minutes, Total

More information

Show that the dual of the exclusive-or is equal to its compliment. 7

Show that the dual of the exclusive-or is equal to its compliment. 7 Darshan Institute of ngineering and Technology, Rajkot, Subject: Digital lectronics (2300) GTU Question ank Unit Group Questions Do as directed : I. Given that (6)0 = (00)x, find the value of x. II. dd

More information

Boolean Algebra. Digital Logic Appendix A. Boolean Algebra Other operations. Boolean Algebra. Postulates, Identities in Boolean Algebra

Boolean Algebra. Digital Logic Appendix A. Boolean Algebra Other operations. Boolean Algebra. Postulates, Identities in Boolean Algebra Digital Logic Appendix A Gates Combinatorial Circuits Sequential Circuits George Boole ideas 1854 Claude Shannon, apply to circuit design, 1938 (piirisuunnittelu) Describe digital circuitry function programming

More information

Fundamentals of Computer Systems

Fundamentals of Computer Systems Fundamentals of Computer Systems Review for the Midterm Stephen A. Edwards Columbia University Spring 22 The Midterm 75 minutes 4 5 problems Closed book Simple calculators are OK, but unnecessary One double-sided

More information

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18 University of Waterloo Department of Electrical & Computer Engineering E&CE 223 Digital Circuits and Systems Midterm Examination Instructor: M. Sachdev October 23rd, 2007 Total Time = 90 Minutes, Total

More information

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017 UNIVERSITY OF BOLTON TW35 SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER 2-2016/2017 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002

More information

Digital Circuits ECS 371

Digital Circuits ECS 371 Digital Circuits ECS 371 Dr. Prapun Suksompong prapun@siit.tu.ac.th Lecture 18 Office Hours: BKD 3601-7 Monday 9:00-10:30, 1:30-3:30 Tuesday 10:30-11:30 1 Announcement Reading Assignment: Chapter 7: 7-1,

More information

Logic. Combinational. inputs. outputs. the result. system can

Logic. Combinational. inputs. outputs. the result. system can Digital Electronics Combinational Logic Functions Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends

More information

Written exam for IE1204/5 Digital Design with solutions Thursday 29/

Written exam for IE1204/5 Digital Design with solutions Thursday 29/ Written exam for IE4/5 Digital Design with solutions Thursday 9/ 5 9.-. General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 8-794487 Exam text does not have to be returned when

More information

EECS 270 Midterm Exam 2 Fall 2009

EECS 270 Midterm Exam 2 Fall 2009 EECS 270 Midterm Exam 2 Fall 2009 Name: unique name: UMID: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: NOTES: Problem # Points 1&2

More information

Digital Electronics. Delay Max. FF Rate Power/Gate High Low (ns) (MHz) (mw) (V) (V) Standard TTL (7400)

Digital Electronics. Delay Max. FF Rate Power/Gate High Low (ns) (MHz) (mw) (V) (V) Standard TTL (7400) P57/67 Lec9, P Digital Electronics Introduction: In electronics we can classify the building blocks of a circuit or system as being either analog or digital in nature. If we focus on voltage as the circuit

More information

( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function

( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function Question Paper Digital Electronics (EE-204-F) MDU Examination May 2015 1. (a) represent (32)10 in (i) BCD 8421 code (ii) Excess-3 code (iii) ASCII code (b) Design half adder using only NAND gates. ( c)

More information

3. Complete the following table of equivalent values. Use binary numbers with a sign bit and 7 bits for the value

3. Complete the following table of equivalent values. Use binary numbers with a sign bit and 7 bits for the value EGC22 Digital Logic Fundamental Additional Practice Problems. Complete the following table of equivalent values. Binary. Octal 35.77 33.23.875 29.99 27 9 64 Hexadecimal B.3 D.FD B.4C 2. Calculate the following

More information

COSC 243. Introduction to Logic And Combinatorial Logic. Lecture 4 - Introduction to Logic and Combinatorial Logic. COSC 243 (Computer Architecture)

COSC 243. Introduction to Logic And Combinatorial Logic. Lecture 4 - Introduction to Logic and Combinatorial Logic. COSC 243 (Computer Architecture) COSC 243 Introduction to Logic And Combinatorial Logic 1 Overview This Lecture Introduction to Digital Logic Gates Boolean algebra Combinatorial Logic Source: Chapter 11 (10 th edition) Source: J.R. Gregg,

More information

Department of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals

Department of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals Department of Electrical and Computer Engineering Universit of Wisconsin - Madison ECE/C 352 Digital stem Fundamentals Quiz #2 olution Thursda, Octoer 26, 2000, 7:15--8:30PM 1. (15 points) (a). (5 points)

More information

Lecture 3 Review on Digital Logic (Part 2)

Lecture 3 Review on Digital Logic (Part 2) Lecture 3 Review on Digital Logic (Part 2) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ ircuit Optimization Simplest implementation ost criterion literal

More information

EECS150 - Digital Design Lecture 11 - Shifters & Counters. Register Summary

EECS150 - Digital Design Lecture 11 - Shifters & Counters. Register Summary EECS50 - Digital Design Lecture - Shifters & Counters February 24, 2003 John Wawrzynek Spring 2005 EECS50 - Lec-counters Page Register Summary All registers (this semester) based on Flip-flops: q 3 q 2

More information

Chap 2. Combinational Logic Circuits

Chap 2. Combinational Logic Circuits Overview 2 Chap 2. Combinational Logic Circuits Spring 24 Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard Forms Part 2 Circuit Optimization Two-Level Optimization

More information

Roger L. Tokheim. Chapter 8 Counters Glencoe/McGraw-Hill

Roger L. Tokheim. Chapter 8 Counters Glencoe/McGraw-Hill Digital Electronics Principles & Applications Sixth Edition Roger L. Tokheim Chapter 8 Counters 2003 Glencoe/McGraw-Hill INTRODUCTION Overview of Counters Characteristics of Counters Ripple Up Counter

More information

Digital Electronics Circuits 2017

Digital Electronics Circuits 2017 JSS SCIENCE AND TECHNOLOGY UNIVERSITY Digital Electronics Circuits (EC37L) Lab in-charge: Dr. Shankraiah Course outcomes: After the completion of laboratory the student will be able to, 1. Simplify, design

More information

ECE20B Final Exam, 200 Point Exam Closed Book, Closed Notes, Calculators Not Allowed June 12th, Name

ECE20B Final Exam, 200 Point Exam Closed Book, Closed Notes, Calculators Not Allowed June 12th, Name C20B Final xam, 200 Point xam Closed Book, Closed Notes, Calculators Not llowed June 2th, 2003 Name Guidelines: Please remember to write your name on your bluebook, and when finished, to staple your solutions

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter

More information

Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS

Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS 1) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction (a) X -Y and (b) Y - X using 2's complements. a) X = 1010100

More information

Ch 7. Finite State Machines. VII - Finite State Machines Contemporary Logic Design 1

Ch 7. Finite State Machines. VII - Finite State Machines Contemporary Logic Design 1 Ch 7. Finite State Machines VII - Finite State Machines Contemporary Logic esign 1 Finite State Machines Sequential circuits primitive sequential elements combinational logic Models for representing sequential

More information

CSE140: Components and Design Techniques for Digital Systems. Midterm Information. Instructor: Mohsen Imani. Sources: TSR, Katz, Boriello & Vahid

CSE140: Components and Design Techniques for Digital Systems. Midterm Information. Instructor: Mohsen Imani. Sources: TSR, Katz, Boriello & Vahid CSE140: Components and Design Techniques for Digital Systems Midterm Information Instructor: Mohsen Imani Midterm Topics In general: everything that was covered in homework 1 and 2 and related lectures,

More information

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.4-7.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html

More information

Different encodings generate different circuits

Different encodings generate different circuits FSM State Encoding Different encodings generate different circuits no easy way to find best encoding with fewest logic gates or shortest propagation delay. Binary encoding: K states need log 2 K bits i.e.,

More information

SIR C.R.REDDY COLLEGE OF ENGINEERING ELURU DIGITAL INTEGRATED CIRCUITS (DIC) LABORATORY MANUAL III / IV B.E. (ECE) : I - SEMESTER

SIR C.R.REDDY COLLEGE OF ENGINEERING ELURU DIGITAL INTEGRATED CIRCUITS (DIC) LABORATORY MANUAL III / IV B.E. (ECE) : I - SEMESTER SIR C.R.REDDY COLLEGE OF ENGINEERING ELURU 534 007 DIGITAL INTEGRATED CIRCUITS (DIC) LABORATORY MANUAL III / IV B.E. (ECE) : I - SEMESTER DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING DIGITAL

More information

Digital Electronics. Part A

Digital Electronics. Part A Digital Electronics Final Examination Part A Winter 2004-05 Student Name: Date: lass Period: Total Points: Multiple hoice Directions: Select the letter of the response which best completes the item or

More information