04. What is the Mod number of the counter circuit shown below? Assume initially reset.
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1 . Which of the following is the state diagram for the Meale machine shown below. 4. What is the Mod number of the counter circuit shown below? Assume initiall reset. input CLK D output D D a. b. / / / / / / / a. 2 b. 3 c. 4 4.Ans: c CLK 5. The circuit shown below works as c. / / / / 2: S d. / / / / / a. Positive level triggered D Flip flop b. Negative level triggered D Flip flop c. Positive level triggered T Flip flop. Ans: a 2. Minimum number of :4 Demultipleers required to design a decoder a. 85 b. 64 c. 2 d. decoder can t be designed with DE. 2. Ans: a 3. How man k 4 ROM s are required to design a 6 k 6 ROM? a. 64 b. 6 c Ans: a 5 Ans: b 6. Minimum number of 2 input NAND gates required to implement the Boolean function A B O AB a. 23 b. 24 c Ans: 7. The simplified Boolean epression for function F(A,B,C,D) shown in the k map is C C
2 a. AB C D AB C D b. AB C D A B C D c. AB C D AB C D 7. Ans: 8. The transistor circuit shown below & are outputs of transistors & 2 respectivel. 5V 5V 2 { If (B = ) then = If (B = ) then = } If (A = ) { If (B = ) then = If (B = ) then = } The Boolean epression for is given b a. A+B b. A B A B c. AB A B. Ans: b The relation between and is a. = b. c. + = d. + = 8. Ans: d 9. f = khz T T Schmitt fout Trigger. How man TTL open collector NAND gates are required to implement Boolean f A B. C D. function a. 2 b. 3 c. 6. Ans: a 2. N inverters are connected in a Ring. 2 3 N In the above circuit, a sinusoidal input of frequenc khz is given as input to Schmitt trigger. The frequenc f out is a. 5 khz b. 2kHz c. 2.5kHz 9. Ans: c. Consider the software code implemented on a computer. It is required to design an equivalent digital Hardware for the software code. A B If (A = ) then Digital Hardware Each inverter has a propagation dela of ns. The above circuit works an a. Oscillator if N is odd & frequenc of 5 operation is MHz N b. Oscillator if N is even & frequenc of 5 operation is MHz N c. Oscillator if N is odd & frequenc of operation is MHz N 2. Ans: a
3 3. Valid Ecess code 5. J = ns S ns 4 Bit Ripple carr Adder c = K = ns R Clk = In the circuit shown above: 4bit valid Ecess 3 is given as input and the output is valid 4 bit BCD code. In order to perform such an operation value of should be a. b. c. d. 3. Ans: b Valid BCD code Propagation dela of flip flop & AND gate is ns each. In the above circuit J & K are connected to an clock input is made alwas HIGH making the circuit operate in Race around condition. What is the frequenc of oscillation at the pin? a. 5MHz b MHz c. 25MHz d MHz 5.Ans: c c i : carr s i : sum 6. A Fair die is rolled. The face value of the die in encoded into 3bit binar. For eample: {, 2, } Full Adder Adder circuit dealing with 2 s complement numbers. In the above circuit, the output V is when a. c 2 = c 3 b. c 2 c3 c. c 3 + c 2 = 4. Ans: b c 2 Full Full Adder Adder c = s 2 c 3 c 2 c s Overflow detector s V Face value of die The output of encoder is given to a full adder circuit. What is the probabilit that carr = & sum =? a..25 b..5 c..75 d. 6. Ans: b 7. +5V R encoder (t) Full adder Carr Sum C (t) (t) ns 2 ns t In the above circuit (t) is input, (t) is the output. The Fourier transform of the output (t) is
4 a. sinc function with zero crossing at f = MHz, 2MHz, 3 MHZ b. sinc function at zero crossing f = 5MHz, MHz, 5 MHZ c. Rectangle function of the above. 7. Ans: 8. Given the following k-map which one of the following represents minimal sum-of products of the map. W Z a. z b. w z c. w z d. z 8. Ans: 9. Which of the following are essential Prime Implicants in the Boolean epression AB AC BC a. AB, A C b. AB, AC, BC c. A C, BC d. AB, BC 2. Statement I: In a Meale machine the present output depends onl on the present state Statement II: In Moore machine the present outputs depends on present state as well as present input a. both S and S 2 are true b. S is true S 2 false c. S is false and S 2 is true d. Neither S nor S 2 is true 2. Ans: d 22. The minimum decimal equivalent of (23D) is a. 69 b. 67 c. 59 d Ans: c 23. Function f(a) is defined as f(a) = 2 s complement of A then f[f(f(f(a)))] = a. A b. A c. d. 23. Ans: a 24. If f(a, B,C) = [A B] C, then f C,A B,A is a. A B C b. A B C c. A C B 24. Ans: a 9. Ans: a 2. The characteristic equation of T Flip flop is given b 25. A B a. (n+) = T+ T b. n T T c. (n+) = T d. none of the above 2. Ans: C For the venn diagram shown above, the equivalent function for the shaded region is a. A B C b. A B c. A B 25. Ans:
5 26. Match the following Column - A P.. ABC Z R. Column B : 2: 2: Match column A with column B a. P 3 2 R b. P 3 R 2 c. P 2 3 R 26. Ans: The above circuit implements a. Binar to Gra code conversion b. Gra to Binar code conversion c. BCD to Ecess-3 code conversion 27. Ans: a 28. CLK 2 bit free running counter 2 4 Decoder 2 The counter is free running up counter starting at. The digital to analog converter equation is given b V VR 2 d3 2 d2 2 d 2 d. The sequence of output voltages generated b DAC is a. b. 8V 4V 2V V V 2V 4V 8V A A 3 d 3 d 2 d d V R = 6V Digital to Analog Converter V 27. The following data is stored in ROM c. V 2V 3V 4V A B C ROM Z 28. Ans: a
6 Directions: The following 29 & 3 questions consists of two statements, one labeled the Assertion A and the other labeled the Reason R. our are to eamine these two statements carefull and decide if the Assertion A and the Reason R are eplanation of the Assertion. Select our answer to these its using the codes given below and mark our answer sheet accordingl Codes : a) both A and R are true and R is the correct eplanation of A b) both A and R are true but R is not a correct eplanation of A c) A is false and R is true d) A is true and R is false 29. Assertion (A) : N bit flash ADC is faster than N bit successive approimation ADC Reason (R) : Flash ADC uses 2 n comparators in parallel. 29. Ans: 3. Assertion (A): Emitter coupled logic circuit have ver less propagation delas. Reason (R): ECL is unsaturated logic famil. 3. Ans: A
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