EE 330 Lecture 36. Digital Circuits. Transfer Characteristics of the Inverter Pair One device sizing strategy Multipleinput gates


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1 EE 330 Lecture 36 Digital Circuits Transfer Characteristics of the Inverter Pair One device sizing strategy Multipleinput gates
2 Review from Last Time The basic logic gates It suffices to characterize the inverter of a logic family and then express the performance of other gates in that family in terms of the performance of the inverter. What characteristics are required and desirable for an inverter to form the basis for a useful logic family?
3 Review from Last Time Ask the inverter how it will interpret logic levels IN Inverter pair OUT L TRIP H When OUT =, H and L are stable operating points, TRIP is a quasistable operating point Observe: slope of IPTC is greater than 1 at TRIP and less than 1 at H and L
4 Review from Last Time Observation OUT When = for the inverter, OUT is also equal to. Thus the intersection point for = in the inverter transfer characteristics (ITC) is also an intersection point for OUT = in the inverterpair transfer characteristics (IPTC) 1 1 OUT 1 1 TRIP L TRIP H Implication: Inverter characteristics can be used directly to obtain TRIP
5 Review from Last Time Logic Family Characteristics What properties of an inverter are necessary for it to be useful for building a twolevel logic family? The inverterpair transfer characteristics must have three unique intersection points with the OUT = line What are the logic levels for a given inverter of for a given logic family? The two extreme intersection points of the inverterpair transfer characteristics with the OUT = line OUT 1 1 Can we legislate H and L for a logic family? No! What other properties of the inverter are desirable? L TRIP H Reasonable separation between H and L (enough separation so that noise does not cause circuit to interpret level incorrectly) TRIP + H 2 L (to provide adequate noise immunity and process insensitivity)
6 What are the transfer characteristics of the static CMOS inverter pair? OUT Consider first the inverter
7 M 2 M 1
8 M 2 M 1
9 Case 1 M 1 triode, M 2 cutoff W L 2 1 OUT I μ C D1 n OXn IN Tn OUT ID2 0 Equating I D1 and I D2 we obtain: 1 W L 2 1 OUT 0 μ C n OXn IN Tn OUT 1 It can be shown that setting the first product term to 0 will not verify, thus M 2 M 1 OUT 0 valid for: GS1 Tn DS1 GS1 Tn thus, valid for: IN Tn OUT IN Tn IN DD Tp GS2 Tp
10 Graphical Interpretation of these conditions: IN Tn OUT IN Tn IN DD Tp
11 Case 1 OUT 0 M 1 triode, M 2 cutoff IN Tn M 1 CO OUT IN Tn M 2 CO  Tp M 1 SAT M 1 TR IN DD Tp  Tn + Tp
12 Case 1 OUT 0 M 1 triode, M 2 cutoff IN Tn M 1 CO OUT IN Tn M 2 CO  Tp M 1 SAT M 1 TR IN DD Tp  Tn + Tp
13 Partial solution: Case 1  Tp  Tn + Tp
14 Case 2 M 1 triode, M 2 sat M 2 TR M 2 CO M 1 CO M 2 SAT  Tp M 1 SAT M 1 TR  Tn + Tp
15 Case 1 OUT 0 M 1 triode, M 2 cutoff IN Tn M 1 CO OUT IN Tn M 2 CO  Tp M 1 SAT M 1 TR IN DD Tp Tn + Tp
16 Partial solution: Case 1  Tp Tn + Tp
17 Regions of Operation for Devices in CMOS inverter M 2 M 1 M 2 TR M 2 CO M 1 CO M 2 SAT  Tp M 1 SAT M 1 TR  Tn + Tp
18 Case 2 M 1 triode, M 2 sat M 2 TR M 2 CO M 1 CO M 2 SAT  Tp M 1 SAT M 1 TR Tn + Tp
19 Case 2 M 1 triode, M 2 sat W L 2 1 μc p OXp W2 I 2 L 1 OUT I μ C D1 n OXn IN Tn OUT Equating I D1 and I D2 we obtain: 2 D2 IN DD Tp 2 μc p OXp W W OUT μ C 2 L L 2 IN DD Tp n OXn IN Tn OUT 2 1 M 2 M 1 valid for:  GS1 Tn DS1 GS1 Tn GS2 Tp DS2 GS2 T2 thus, valid for: IN Tn OUT IN Tn IN DD Tp OUT DD IN DD Tp
20 Case 2 M 1 triode, M 2 sat OUT DD IN DD Tp M 2 TR M 2 CO IN Tn M 1 CO M 2 SAT OUT IN Tn  Tp M 1 SAT M 1 TR IN DD Tp Tn + Tp
21 Case 2 M 1 triode, M 2 sat OUT DD IN DD Tp M 2 TR M 2 CO IN Tn M 1 CO M 2 SAT OUT IN Tn  Tp M 1 SAT M 1 TR IN DD Tp Tn + Tp
22 Partial solution: Case 2 Case 1  Tp Tn + Tp
23 Case 3 M 1 sat, M 2 sat M 2 TR M 2 CO M 1 CO M 2 SAT  Tp M 1 SAT M 1 TR Tn + Tp
24 Case 3 M 1 sat, M 2 sat μc W n OXn 1 I 2 D1 IN Tn 2 L1 μc p OXp W2 I 2 L 2 D2 IN DD Tp Equating I D1 and I D2 we obtain: 2 μc W μc W 2 L 2 L IN DD Tp IN Tn 2 2 p OXp 2 n OXn Which can be rewritten as: μc W μc W 2 L 2 L + DD Tp IN IN Tn p OXp 2 n OXn 1 IN 2 1 Which can be simplified to: μc W μc W 2 L 2 L p OXp + n OXn 1 2 Tn DD Tp 1 2 μc W μc W 2 L 2 L n OXn 1 p OXp M 2 M 1 This is a vertical line
25 Case 3 M 1 sat, M 2 sat IN Since IN valid for: μc W μc W 2 L 2 L p OXp + n OXn 1 2 Tn DD Tp C C =C OXn OXp OX 1 2 μc W μc W 2 L 2 L n OXn 1 p OXp 2 W L 1 2 this can be simplified to: p Tn DD Tp 1 n 2 W L μ W μ L 1 p 2 1 n 2 GS1 Tn DS1 GS1 Tn thus, valid for: μ W μ L M 2 M 1  GS2 Tp DS2 GS2 T IN Tn OUT IN Tn IN DD Tp OUT DD IN DD Tp
26 Case 3 M 1 sat, M 2 sat OUT DD IN DD Tp M 2 TR M 2 CO IN Tn M 1 CO M 2 SAT OUT IN Tn  Tp M 1 SAT M 1 TR IN DD Tp Tn + Tp
27 Case 3 M 1 sat, M 2 sat OUT DD IN DD Tp M 2 TR M 2 CO IN Tn M 1 CO M 2 SAT OUT IN Tn  Tp M 1 SAT M 1 TR IN DD Tp Tn + Tp
28 Partial solution: Case 3 Case 2 Case 1  Tp Tn + Tp
29 Case 4 M 1 sat, M 2 triode M 2 TR M 2 CO M 1 CO M 2 SAT  Tp M 1 SAT M 1 TR Tn + Tp
30 Case 4 M 1 sat, M 2 triode μc W n OXn 1 I 2 D1 IN Tn 2 L1 W2  OUT DD I μ C  L 2 D2 p OXp IN DD Tp OUT DD 2 Equating I D1 and I D2 we obtain: μ C W W L L 2 2 μ C  n OXn OUT DD IN Tn p OXp IN DD Tp OUT DD 1 2 M 2 M 1 valid for:  GS1 Tn DS1 GS1 Tn GS2 Tp DS2 GS2 T2 thus, valid for: IN Tn OUT IN Tn IN DD Tp OUT DD IN DD Tp
31 Case 4 M 1 sat, M 2 triode OUT DD IN DD Tp M 2 TR M 2 CO IN Tn M 1 CO M 2 SAT OUT IN Tn  Tp M 1 SAT M 1 TR IN DD Tp Tn + Tp
32 Case 4 M 1 sat, M 2 triode OUT DD IN DD Tp M 2 TR M 2 CO IN Tn M 1 CO M 2 SAT OUT IN Tn  Tp M 1 SAT M 1 TR IN DD Tp Tn + Tp
33 Partial solution: Case 4 Case 3 Case 2 Case 1  Tp Tn + Tp
34 Case 4 M 1 cutoff, M 2 triode M 2 TR M 2 CO M 1 CO M 2 SAT  Tp M 1 SAT M 1 TR Tn + Tp
35 Case 5 M 1 cutoff, M 2 triode ID1 0 W2  OUT DD I μ C  L 2 D2 p OXp IN DD Tp OUT DD Equating I D1 and I D2 we obtain: valid for: GS1 2 W2  OUT DD μ C p OXp  0 IN DD Tp OUT DD L Tn GS2 Tp DS2 GS2 T2 M 2 M 1 thus, valid for: IN Tn IN DD Tp OUT DD IN DD Tp
36 Case 5 M 1 cutoff, M 2 triode OUT DD IN DD Tp M 2 TR M 2 CO IN Tn M 1 CO M 2 SAT  Tp M 1 SAT M 1 TR IN DD Tp Tn + Tp
37 Case 5 M 1 cutoff, M 2 triode OUT DD IN DD Tp M 2 TR M 2 CO IN Tn M 1 CO M 2 SAT  Tp M 1 SAT M 1 TR IN DD Tp Tn + Tp
38 Case 5 Case 4 M 2 Case 3 M 1 Case 2 Case 1  Tp Tn + Tp
39  Tp Tn + Tp
40 1 1  Tp From Case 3 analysis: Tn TRIP IN Tn + DD Tp 1 μ W L μ W L p 2 1 n 1 2 μ W L μ W L p 2 1 n 1 2 DD+Tp
41 Inverter Transfer Characteristics of Inverter Pair OUT What are H and L? OUT L TRIP H Find the points on the inverter pair transfer characteristics where = and the slope is less than 1
42 Inverter Transfer Characteristics of Inverter Pair for THIS Logic Family OUT M 2 M 1 OUT DD 1 DD Tp Tp Tn TRIP DD Tn TRIP DD DD+Tp DD+Tp H = and L =0  Tp Note this is independent of device sizing for THIS logic family!! L  Tn + Tp TRIP H
43 Sizing of the Basic CMOS Inverter M 2 M 1 The characteristic that device sizes do not need to be used to establish H and L logic levels is a major advantage of this type of logic How should M 1 and M 2 be sized? How many degrees of freedom are there in the design of the inverter?
44 How should M 1 and M 2 be sized? M 2 M 1 How many degrees of freedom are there in the design of the inverter? { W 1,W 2,L 1,L 2 } 4 degrees of freedom But in basic device model and in most performance metrics, W 1 /L 1 and W 2 /L 2 appear as ratios { W 1 /L 1,W 2 /L 2 } effectively 2 degrees of freedom
45 How should M 1 and M 2 be sized? M 2 M 1 { W 1,W 2,L 1,L 2 } 4 degrees of freedom Usually pick L 1 =L 2 =L min { W 1 /L 1,W 2 /L 2 } effectively 2 degrees of freedom How are W 1 and W 2 chosen? Depends upon what performance parameters are most important for a given application!
46 How should M 1 and M 2 be sized? M 2 M 1 Usually pick L 1 =L 2 =L min { W 1 /L 1,W 2 /L 2 } 2 remaining degrees of freedom One popular sizing strategy: 1. Pick W 1 =W MIN to minimize area of M 1 2. Pick W 2 to set trippoint at /2
47 How should M 1 and M 2 be sized? pick L 1 =L 2 =L min One popular sizing strategy: 1. Pick W 1 =W MIN to minimize area of M 1 2. Pick W 2 to set trippoint at /2 M 2 M 1 Observe Case 3 provides expression for TRIP 1 Thus, at the trip point,  Tp Tn TRIP 1 = OUT IN TRIP Tn + DD Tp 1 μ W L μ W L p 2 1 n 1 2 μ W L μ W L p 2 1 n 1 2 DD+Tp
48 How should M 1 and M 2 be sized? pick L 1 =L 2 =L min One popular sizing strategy: 1. Pick W 1 =W MIN to minimize area of M 1 2. Pick W 2 to set trippoint at /2 M 2 M 1 Typically Tn =0.2, Tp =0.2 \ TRIP Tn + DD Tp 1 μ W L μ W L p 2 1 n 1 2 μ W L μ W L DD 2 μ W 1 μ W DD DD DD p 2 n 1 p 2 1 n 1 2 μ W μ W p 2 n 1 Solving this equation for W 2, obtain μ W W μ n 2 1 Other sizing strategies are used as well and will be discussed later! p
49 Extension of Basic CMOS Inverter to MultipleInput Gates A M 4 B M 1 M 2 M 3 Y A B Y Truth Table Performs as a 2input NOR Gate Can be easily extended to an ninput NOR Gate A B Y
50 Extension of Basic CMOS Inverter to MultipleInput Gates A M 3 M 4 M 1 B M 2 Y A B Y Truth Table Performs as a 2input NAND Gate Can be easily extended to an ninput NAND Gate A B Y
51 Static CMOS Logic Family M 2 M 2 Pullup Network PUN M 1 M 1 Pulldown Network PDN Observe PUN is pchannel, PDN is nchannel
52 Static CMOS Logic Family M 2 M 4 M 3 M 4 M 1 A M 3 Y A M 1 Y B M 1 M 2 B M 2 M 4 M 3 M 4 M 2 A M 3 Y Y A M 1 M 1 B M 1 M 2 B M 2 nchannel PDN and pchannel PUN H =, L =0 (same as for inverter!)
53 General Logic Family PUN PUN PDN PDN Compound Gate in CMOS Process pchannel PUN nchannel PDN H =, L =0 (same as for inverter!) Arbitrary PUN and PDN
54 Other MOS Logic Families M 2 M 2 M 2 M 1 M 1 M 1 Enhancement Load NMOS Enhancement Load PseudoNMOS Depletion Load NMOS
55 End of Lecture 36
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