Using MOS Models. C.K. Ken Yang UCLA Courtesy of MAH EE 215B


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1 Using MOS Models C.K. Ken Yang UCLA Courtesy of MAH 1
2 Overview Reading Rabaey 5.4 W&H 4.2 Background In the past two lectures we have reviewed the iv and CV curves for MOS devices, both nmos and pmos. The results are fairly interesting, and can be used to explain a number of strange results that we found with our RC models. The iv models can be used to predict how delay with change with supply voltage, and why the logical effort of gates is a smaller number then our simple RC models predict. In fact we can use these models to explain how input slope affect gate delay which is part of the logical effort dilemma. 2
3 Review: Transistor as a Switched Current I D I max V GS = V DD I mid delay=cδv/i ζ=λl min avg 1 I I + I I V = V ;V = 3 V 2 4 W 1 2 I = µc ( V V ) ( ) ( ) eff max mid ds gs dd ds dd eff * ox gs th Leff 2 * Leff = L elec 1 ( 3 ) λl V 4 V L min dd dsat elec V DD /2 V DD V DS 3
4 iv Results Model(s) allow us to answer a number of questions Performance scaling with voltage Performance scaling with technology LE of stacked transistors Input slope affect on delay Voltage gain issues Relates to noise margins Injected noise in coupling situations In the next few slides, we will focus on delay issues Delay depends on i dsat, C load, V dd Look at i dsat first 4
5 Limitation of Simple RC Model A B Delay of this Gate Impact of velocity saturated and CLM Current is not quadratic so the timedomain waveform is going to be different. Shape of IV curve is not the same when two transistors are placed in series. Input slope Delay of a gate is a function of the delay of the driver gate As gate A slows down, the delay of gate B gets larger Previous analysis ignored this effect 5
6 Peak Saturation Current We had a couple of models for i dsat Full velocity saturation model with mobility reduction Alpha power law model First, review how good these models are. Fullvelocity saturation model is physically intuitive. But it is quite complex if we account for the vertical field dependence of E c and µ eff. We can look at what happens if we ignore gate field effect Set mobility to be a constant (not function of V gs ) Use the highfield mobility for electron (NMOS) and holes (PMOS).since we are dealing with digital signals. 6
7 Equations µ e 270 cm2 V. s µ h 90 cm2 V. s ν sat cm s E ce 2. ν sat 2. ν sat E ch µ e µ h E ce = V E ch = V µm µm i dsnsat V gs, L W. ν. sat C. 2 ox V gs V th V gs V th E. ce L i dspsat V gs, L W. ν. sat C. 2 ox V gs V th V gs V th E. ch L µ e V gs 540 k 1 V gs V th t. ox V µm 1.85 cm 2 V. s A i dsnalpha V gs, L m i dsnfull V gs, L E ce V gs k. W. C ox 1. F m 2 2. ν sat µ e V gs L 1. W. ν. m sat C. 2 ox V gs V th Vdd V gs V th E ce V. gs L V gs V th, V th.. Vdd N 0.8. V gs V th 1. V
8 Current Comparison i dsn10. i, i i dsnsat V gs, 0.4 µm 20. i dsnfull V gs, 0.4 µm 20. i dsnalpha V gs, 0.4 µm i dsn10., V 3.3 i, 0 gs 8
9 Model Comparison Most of the models are quite good Alpha power and full velocity model match current well Alpha power model has a fit constant for setting the current Constant mobility model is off at low V gs Expected since it underestimates the current at low Vdd Mobility is larger at these operating conditions Use simplest model for task Often that is the alpha power model For fixed operating voltage, simple fixed mobility velocity saturation model works well 9
10 Aside: A Quick Look at Voltage Scaling Using the alpha power model Delay should scale as C*V dd /(V dd V th ) 1.25 Note that the important effect is not the 1.25 power, but rather that the scaling is V/(Vx). As V/x ratio gets smaller the circuit gets slower 4 4 V gs. 3.3 V i dsnalpha( 3.3. V, 0.4 µm) i dsnalpha V gs, 0.4 µm V gs
11 Velocity Saturation and CLM 11
12 Impacts of Velocity Saturation Changes the iv curve so impacts how transistor turns on to discharge the load When you have two transistors in series (with same width) Lateral field is smaller, since V is dropped across two transistors Changes the degree of velocity saturation of each device. Velocity saturation current model can be very intuitively useful i dsat = µ eff C ox W 2L ( Vg Vth) ( V V ) + 1 E L Saturation current is the relationship between V gs V t and E c L. With V gs V t <<E c L, the equation simplifies to the normal equation. Alpha power model would need to be refit to account for this. gs th c 2 12
13 Inverter Driving a Capacitor Assume an infinite input slope NMOS Let L=0.4µm (for a 0.35µm technology) E c =6V/µm, Vdd=3.3V V DSAT = (2.6)2.4/( ) = 1.25 < Vdd/2 So current is ~ constant for the entire transition PMOS V DSAT = (2.6)7.2/( ) = 1.91 ~ Vdd/2 Less constant current (but more so with smaller channel lengths i dsat = µ V = Wν eff dsat C ox = sat ( Vgs Vth) EcL ( Vgs Vth) + EcL ( Vg Vth) Cox ( Vgs Vth) + 2 ( Vg Vth) ( V V ) W 2L gs th E L + 1 E L c 2 c 13
14 Resistor Comparison (NMOS) 0.18µm technology CV/I an excellent approximation Especially with velocity saturation Courtesy of MG Johnson 14
15 Resistor Comparison (PMOS) 0.18µm technology Courtesy of MG Johnson 15
16 Series Stacking Logical effort and Elmore assumes that network of transistors is equivalent to network of resistors. Parallel halves the resistance, series doubles the resistance. So I DS1 = 2I DS2 R 2 C is doubled (hence twice the delay) True for quadratic model Velocity saturation causes the model to be incorrect. W/L R pdn2 W/L I DS1 R pdn1 V x W/L I DS2 R pdn2 16
17 nmos Series Stacks Can do this using the velocity saturated model ( Vg Vth) ( ) W idsat =µ effcox 2L V V elec gs th EL c 2 elec + 1 Adjust L elec = m*l min 2stack = changing L by 2x, does not ½ the current E ce is around 6V/µm for 3.3V, so EL min = 2.4 L elec = 2L min =0.8µm changes this to 4.8 Current changes from 1/5.1 to 1/7.5 Only need to make the transistors 1.5x wider! 3 Transistor stack is only ½ the current Need to make the transistors only 2x wider 17
18 pmos Series Stacks Velocity saturation is a much smaller effect here E ch is much larger 18V/µm, so E c L = V Two series devices are 10/17 Need to make devices times wider for same current Three series devices are 10/24 Need to make devices times as wide for same current In general Increase the size of an mseries stack by a factor, X(m) X(m) = ( ) + ( ) V V m*e L gs th c min V V + E L gs th c min 18
19 Accounting for CLM Replace L elec with the L eff * * Leff = L elec 1 With λ=0.05, L eff *=0.37um with L elec =L min i dsmax is about 7% higher than i dsat (w/o CLM) I dsavg = 1.037*i dsat (w/o CLM) ( 3 ) λl V 4 V L min dd dsat ( Vg Vth ) ( ) With λ=0.05, L eff *=0.78um with L elec =2*L min I dsavg = 1.015*i dsat (w/o CLM) Effect can be more with 90nm technology or beyond (~15% increase for i dsmax ) elec W idsat =µ effcox 2L V V * eff gs th EL c 2 * eff
20 Logical Effort Comparison Accounting for velsat (assume the inverter P:N = 2) 2input NAND PMOS=2, NMOS=1.48 (instead of size 2) g NAND2 = 3.48/3 = 1.16 (instead of 1.33) 3input NAND PMOS=2, NMOS=1.96 (instead of size 3) g NAND3 = 4/3 = 1.33 (instead of 1.67) The current is less than the quadratic model but improves the logical effort. Accounting for CLM Inverter s average current is slightly higher b/c of CLM 2input NAND PMOS=2, NMOS=1.51 (a factor of (1+( ) higher) 20
21 Unequal Stack Sizing Not common (due to area) Roughly compensate by calculating the correct L elec. Device closest to the output (M1) is saturated Equivalent length of a W1 device L elec = L min (1+W 1 /W 2 ) Can use the Lelec for CLM as well. Example: W 1 =1, W 2 =2 L elec = L min * W 1 /L min V x W1/L elec W 2 /L min 21
22 Input Slope Effect 22
23 Input Slope Delay of gate depends on the speed of input If input is very fast, transistor will be fully on before the output starts to change. Get the smallest delay possible If input is slow, then the transistor will have its gate at less than Vdd, and the current will be less than expected. The delay will increase Not purely dependent on input. If input is slow but output is slower, then transistor will still be fully on before output starts to change. Function of the ratio of input to output slope 23
24 Inverter Model Difference in nmos and pmos currents drive the output C. d Vout i i d t pmos i nmos Devices basically acts like a voltage controlled current source. If the input voltage is changing, we can apply the nonlinear iv equations to solve the equation. Too difficult. Make some simplifications. 24
25 Input Slope Effect Simplified Calculation Assume Gate switches when input=vdd/2 Linear current to voltage. Solve for the t phl,ramp Delay is increased by t r /4 With t r ~2t d_step (t d_step =step input delay of input gate). 25
26 Input Slope Effect  Simulation Sweep input signal slope. t d(step) = delay of inverter generating the input (from a step) t d(ramp) = delay of inverter (with sloped input) Result is less than estimated. Equation is a slight overestimate. Result is quite linear. Question our assumptions Assume i L =0 until V IN =Vdd/2 Pessimistic for delay Courtesy of MG Johnson Input signal 26
27 Inverter Drive Curves Look at a contour plot of output current vs. V in, and V out I out <0 (decreases) i out >0 (increases) inv i out =0 27
28 Different (Optimistic) Assumption Assume that i L starts to discharge/charge C L at V TH * This is optimistic Repeat the integration or do this graphically. Behavior Initial discharge ramp is quadratic. Once, i OUT =i MAX, discharge linearly Courtesy of MG Johnson 28
29 Input Slope Effect Graphical Analysis Now, assume a step input that causes the output to transition to V OUT =Vdd/2 at the same time. Step must have occurred when I out =I max /2 Occurs at (Vdd+V TH *)/2 So added delay is Δt for the input to change by V TH */2 Courtesy of MG Johnson 29
30 Input Slope Effect Discussion Simple graphical approach for intuition With input current threshold of V TH * V TN =V TP =0.7 with Vdd=3.3 and t delay = t d_step + t d_input With input current threshold of Vdd/2 t delay = t d_step + t d_input A more realistic number is somewhere between the two estimates closer to t delay = t d_step + 0.4t d_input 30
31 Input Slope Effect Modeling Use logical effort methodology instead of dealing with step inputs Input/output has same slope as the baseline for delay Note that t LE =(1+k slope )t step for equal input and output slope. 11 t t + k t t t delay douput slope dinput delay delay t + LE t + LE ( tdinput tdoutput ) K ISE ( tinp_slope tout_slope ) K ISE So g eq_slope = (1 + k slope )*g step Simulation shows very linear fitting for different input slope (and fixed output slope) Delay (noralized to τ 0 ) Output FO = 10 Output FO = 7.5 LE Model (1) Simulation Proposed Slope Correction Ma & Franzon (2) Input FanOut Courtesy of D. Markovic 31
32 Input Slope Effect in Complex Gates Which input switches matters Top transistor switches Source node rises with the input slope. Current is linearized. Very similar to inverter analysis Bottom transistor switches Top Bottom Drain is V dd V th Current saturates with lower V GS (earlier in the transition) t r is effectively smaller Less input slope dependence. 32
33 Input Slope Correction Changes for different logic gates And different inputs and Vdd. Result is consistent with our intuition 1/K is larger when V dd /V th is smaller Incorporate delay equation into LE formalism If K s are roughly similar, the result is greatly simplified. N g h g h DLE, SC = gi hi + pi i= 1 Ki g h g h DLE, SC = DLE K i i i 1 i 1 N N in driver in driver Slope correction factor, K AOI12 NAND AOI12 NOR NAND3 NAND2 NOR2 Inverter Supply Voltage, V DD (V) 33
34 Simulation/Synthesis Incorporating ISE in a chain of NAND gates buffering (LEFT) Note that increasing f is better for both power and delay than constant f. Can improve power and performance of a synthesized adder. Internal Energy (normalized) Min Delay 0.2 Simulation Original LE LE with Slope Corr Delay Increment (%) Internal power (µw) Synthesized Adder B A Simulation LE with Slope Corr Synthesis Timing Original LE Model Matlab Optimized Adders Delay (normalized to the synthesized adder) 34
35 Summary Our iv models, while simple, are quite good Gives decent intuition on design and sizing Handles several effects and extends existing methodology well Velocity saturation can be incorporated into calculating the logical effort by considering (1+V gst /E c L ) CLM can also be added by using L eff * Input slope effect can be added into the LE methodology. As a constant factor when slopes are different. We will also apply this model for a more accurate understanding of noise margin and senseamplifiers 35
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