Electronic Devices and Circuits Lecture 16 - Digital Circuits: CMOS - Outline Announcements (= I ON V DD
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1 Electronic Deices and Circuits Lecture 16 - Digital Circuits: CMOS - Outline Announcements Handout; Web posting - Lecture Outline and Summary; two readings Exam - Wednesday, No. 5, 7:30-9:30 pm, Room 10-50; closed book HSPICE - nice, but more useful when combined with insight and intuition Reiew - Inerter performance metrics Transfer characteristic: logic leels and noise margins Power: P ae, static P ae, dynamic ( I ON / f C L ) Switching speed: charge thru pull-up, discharge thru pull-down If can model load as linear C: d OUT /dt i CH ( OUT )/C L ; i DCH ( OUT )/C L If can say i CH, i DCH constant: HI-LO C L ( HI - LO )/I CH ; HI-LO C L ( HI - LO )/I DCH Fan-out, fan-in (often only 10 to 90% swings) Manufacturability CMOS Transfer characteristic Gate delay expressions Power and speed-power product Digital circuits Multiple input CMOS gates: NAND and NOR Output buffering Memory cells Lecture 16 - Slide 1
2 Transfer characteristic HI OUT Node equation: i PD i PU i PU i PU : Depends on the deice used i PD OUT LO IN M LO 1L M 1H HI IN NM L NM H Switching transients HI to LO 0 IN < T,PD PulliPD K PD ( IN - T,PD ) / IN - T,PD < OUT Up K PD ( IN - T,PD - OUT /) OUT IN - T,PD > OUT Pull- Up i PU i Charge OFF LO C L to HI ON LO to HI Pull- Up i PU idischarge HI to LO i PD C L Charging cycle: i Charge i PU Discharging cycle: i Discharge i PD i PU Lecture 16 - Slide
3 Switching transients: summary of charge/discharge currents i Charge i Discharge Resistor and E- R L GG (>> ) mode pull-up ( GG on gate) OUT OUT IN IN OUT OUT DD icharge i Discharge E-mode pull-up (DD on gate) OUT IN OUT OUT D-mode pull-up (called "n-mos") i Charge i Discharge OUT IN OUT OUT DD icharge i Discharge CMOS IN OUT OUT OUT Lecture 16 - Slide 3
4 CMOS: transfer characteristic calculation OUT Q n off GSn Tn Q n sat. DSn [ GSn - Tn ] OUT linear SDp - ] [ SGp Tp GSp Tp IN Q n OUT Q n linear Tp sat. off Q n Tn IN [ Tp - ] IN OUT GSn Tn I Tn GSp Tp Transistor operating condition SDp in each region: [ SGp - Tp ] II Region Q n I cut-off linear DSn III [ GSn - Tn ] II saturation linear III saturation saturation I I linear saturation linear cut-off IN Lecture 16 - Slide 4
5 CMOS: transfer characteristic calculation, cont. IN Q n OUT OUT GSn Tn I II III I Tn GSp Tp DSn [ GSn - Tn ] SDp - ] [ SGp Tp DD IN Region I: ( i Dn 0 and i Dp K p IN OUT ) Tp ( ) OUT i Dn i Dp OUT Region : i Dn K n IN OUT Tn i Dn i Dp OUT 0 OUT and i Dp 0 Lecture 16 - Slide 5
6 CMOS: transfer characteristic calculation, cont. OUT II IN Region III: Q n OUT Tn III I IN K p i Dn IN Tp Tp Tn K n K p i Dn i Dp IN 1 Kn K p n [ IN - Tn ] and i Dp K [ ] To achiee symmetry, make K p K n and Tp Tn With this : IN and DD - Tn OUT Tp Regions II and I: Parabolic sections connecting smoothly with straight line sections (see course text). Lecture 16 - Slide 6
7 CMOS: transfer characteristic calculation, cont. OUT Our calculation says that the transfer characteristic DD is ertical in Region III. We know it will hae some slope, but what is it? To see, calculate the small Tn / signal gain about the bias point: sp IN OUT / ( M ) gmp gsp g Begin with the small signal model: - in gn gsp sn gp gsn - - in in g mn gsn g op on IN sp dp dn - sn out Lecture 16 - Slide 7
8 CMOS: transfer characteristic calculation, cont. Redrawing the circuit, we get gn,gp dn,dp gmn in gmp in in gsn gsp gon gop out sn,sp sn,sp from which we see immediately that: OUT [g mn g mp A out ] IN Q in [g on g op ] Writing the conductances in terms of the bias point, as g mn K n I Dn, g mp K p I Dp g mn, g on ni Dn, g op pi Dp pi Dn we get our final result: OUT A K n I Dn K n IN Q [ n p ]I Dn [ n p ] I Dn Lecture 16 - Slide 8
9 CMOS: transfer characteristic calculation, cont. Returning to the transfer characteristic, we see that the slope in Region III is not infinite, but is instead: DD OUT OUT IN A Q K n [ n p ] I Dn A Final comment: A quick and dirty way to approximate the transfer cure of a CMOS gate is to simply draw the three straight line portions in Regions I, III, and : / OUT A Tn DD / DD IN DD / DD IN Lecture 16 - Slide 9
10 CMOS: switching speed; minimum cycle time The load capacitance, C L Assume to be linear Is proportional to MOSFET gate area In channel: µ e µ h so to hae K n K p we must hae W p /L p W n /L n Typically L n L p, and W n W min, so we also hae W p W min. * * * C L nw [ n L n W p L p ]C ox n[ W min W min ]C ox 3nW min C ox Charging cycle IN : Hi to Lo; Q n off, Q P on; OUT : Lo to Hi Assume charged by constant i D,sat K p n i Ch arg e i Dp [ Tp ] K [ Tn ] q Ch arg e C L q Ch arg e C L Q Ch arg e n IN OUT i Ch arg e K n [ Tn ] * 6 nw min C ox 6 nl min W min C * e ox [ Tn ] e [ Tn ] C L Lecture 16 - Slide 10
11 CMOS: switching speed; minimum cycle time, cont. Discharging cycle IN : Lo to Hi; Q n on, Q P off; OUT : Hi to Lo Assume discharged by constant i D,sat Kn i Disch arg e i Dn [ Tn ] q Disch arg e C L q Disch arg e C Q L n Disch arg e IN OUT i Disch arg e K n [ Tn ] * 6 nw min C ox 6 nl min DD W min * L min e C ox [ Tn ] e [ Tn ] Minimum cycle time IN : Lo to Hi to Lo; OUT : Hi to Lo to Hi C L 1nL min Min.Cycle Ch arg e Disch arg e e [ Tn ] Lecture 16 - Slide 11
12 CMOS: power dissipation - total and per unit area Aerage power dissipation All dynamic * P ae C L f 3nW min C ox f Aerage power at maximum data rate Maximum f will be 1/ Min Cycle * e [ Tn ] P Max. f 3 nw min C ox 1 nl 1 W min 4 L min min * 1 e C ox [ Tn ] 4 K n [ Tn ] Aerage power density at maximum data rate Assume that the area per inerter will be proportional to W min PD Max. f P Max. f µ P Max. f e C ox DD [ Tn ] Inerter area Wmin 4 L min * Lecture 16 - Slide 1
13 CMOS: design for high speed Maximum data rate Proportional to 1/ Min Cycle e [ Tn ] f max µ 1 Min.Cycle 1 nl min Teaches us to make small and/or large Note: As we reduce we must also reduce t ox, but t ox doesn't enter directly in f max so it doesn't impact us here. Aerage power density at maximum data rate Assumes area per inerter is proportional to W min P Max. f Max. f µ P Max. f e ox [ Tn ] Inerter area Wmin 4 t ox L min Teaches us PD increases ery quickly as we reduce unless we also reduce (which reduces f max ). Note: Now t ox appears so the impact of reducing, and therefore also t, is een more dramatic! ox How do we make f max larger without melting the silicon? Through CMOS scaling rules - the topic of Lecture 5. Lecture 16 - Slide 13
14 Electronic Deices and Circuits Lecture 16 - Digital Circuits: CMOS - Summary CMOS Transfer characteristic: symmetric LO 0, HI,I ON 0 N ML N MH implies K n K p, Tp Tn T L n L p, W p ( e / h )W n Gate delay expressions LO-HI HI-LO C L /K n ( - T ) Gate delay (GD) LO-HI HI-LO 4 C L /K n ( - T ) If C * L n(w n L WL p )C * n p ox 3n W n C ox (Assumes n p ) then GD 1 n L min / e ( - T ) (Shows merit of reducing ) Power and speed-power product P f C L ae@max. f µ CL /GDK (Shows merit of reducing ) P ae n ( - T ) /4 (NOTE: We will return to CMOS design trade-offs and scaling rules in Lecture 5) Digital circuits Multiple input CMOS gates: NOR: n-channels in series, p-channels in parallel NAND: p-channels in series, n-channels in parallel Output buffering (Problem 3 on PS #8) Memory cells (Check out Sec. 15.4) Lecture 16 - Slide 14
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