EECS 579: Logic and Fault Simulation. Simulation

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1 EECS 579: Logic and Fault Simulation Simulation: Use of computer software models to verify correctness Fault Simulation: Use of simulation for fault analysis and ATPG Circuit description Input data for C Simulation run commands Model C of target circuit Simulation control Host computer Output data for C Performance data for C Emulation: Hardware-assisted simulation using FPGA-based emulators John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page Simulation Uses Reduce/eliminate need to build physical prototypes Alternative design comparison Functional design verification Timing/performance design verification Fault analysis and test generation Simulation Levels Analog (continuous) ELECTRIC CIRCUIT DEVICE/ LAYOUT Level of detail Digital (discrete) SYSTEM (BEHAVIORAL) REGISTER- TRANSFER LOGIC (GATE) SWITCH Simulation cost John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 2

2 Logic Simulation Component types Gates, flip-flops, switches, macro elements Signal accuracy,, X (unknown) plus a few others Timing accuracy (delay models) Transport: unit, nominal Rise/fall delay Simulator structures Compiled-code (compiler-driven) Non-compiled event-driven John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 3 Example Logic Simulation B CLK A t t +25 t 5 ns ns t +5 t + J C K Setup time Hold time t +5 Z6 Z7 Z8 Event John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 4

3 Compiled-Code Simulation Circuit model is executable code. Circuit elements are program routines linked toreflect circuit structure Simulation steps Levelize and code circuit Compile and execute Characteristics All signals are evaluated in all time periods Fast simulation of simpler circuits Inefficient with complex signal/timing Frequent recompilation often necessary John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 5 Compiled-Code Simulation (Code to compute x) Level i- x y Level i NAND gate G z (Code to compute y) LDA x Load x from memory into CPU accumulator A AND y Compute A.y; put in A NOT Compute complement of A STA z Store A in z (To next element) John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 6

4 Compiled-Code Simulator procedure compiled_sim Read circuit description; Break feedback and levelize circuit; Generate code for gates; Initialize signal values; for each input signal vector do for each logic level do for each gate do execute gate code (simulate); end end Output desired results; end end procedure John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 7 Event-Driven Simulation Circuit model is a data structure consisting of set of linked tables specifying components, their attributes, and connections Separate simulation control program processes the circuit Characteristics Signal timing calculations are event-directed Handles complex signal/timing models Circuit models are easy to change Supports forward/backward tracing Slower for large, simple models John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 8

5 Event-Driven Simulation A B G G2 CLK J C K FF Z6 Z7 Z8 Name Type Inputs Outputs Delay Other attributes G NAND A,B FF-J, Z6,5... G2 NOT A FF-K,... FF JKFF G, CLK, G2 Z7, Z8... A PI G,G2 Z6 PO G etc. John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 9 Event-Driven Simulation Name Type Fan-in Fan-out Fan-in Fan-out Delay Other attributes list list G NAND P P2 2 2,5... G2 NOT P3 P4,... FF JKFF P5 P A PI P7 2 Z6 PO P8 etc. P P2 P3 P4 P5 A B FF- J Z6 A FF- K G CLK G2 etc. Fan-in/ fan-out table John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page

6 Example Event-Driven Simulation B CLK A t t +25 t 5 ns ns t +5 t + J C K Setup time Hold time t +5 Z6 Z7 Z8 Event John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page Event-Driven Simulator procedure table_sim Read circuit description; Construct circuit data structures (tables); Initialize signal values and event time t repeat {with set of current events} Select event and examine its fanout list; while (unevaluated fanout signals remain) do Evaluate and schedule fanout events; Output desired results; end until (no more current events) Increment t to next event time; end procedure John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 2

7 Time Simulation Time driven: simulate entire circuit at every time step Event driven: emulate active parts of circuit only when a signal change or event occurs. Event-Driven Simulation. Simulate the current event 2. Scan the circuit for implied events and schedule them 3. Advance simulation time to the next event Event scheduling methods Indexed array A[i]: Given A[current], go to A[current + T] Fast, large storage needs (static allocation) Linear list (linked list) Slow, efficient storage (dynamic allocation) Timing wheel: indexed-list that trades off speed and storage John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 3 Linked List Event Scheduling t Time Line Value Link X P P4 P Y4 X P7 - X2 Other events at t = P7 5 Y5 - - John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 4

8 Timing Wheel Time Link 2 3 Event Scheduling Event data Event data Avoids long searches but is subject to overflow John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 5 Fault Simulation Definition Simulation designed for fault analysis and ATPG Applications Evaluate effects, e.g., criticality of given faults Evaluate coverage of a given test pattern set To aid in test pattern set generation To construct fault dictionaries To estimate manufacturing yield DL = Y d DL = probability of shipping a defective IC Y = probability that a manufactured IC is OK d = defect coverage of testing approximated by fault coverage John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 6

9 Fault Simulation Fault Models Single stuck-line fault model is standard: any logic line may be stuck at or ; the logic elements are fault free Others: delay faults, short/open faults, etc. Fault Simulation Methods Serial: one fault is simulated at a time Parallel: n faults are simulated at a time Parallel method Deductive simulation Concurrent simulation etc. Statistical: fault sampling John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 7 Fault Simulation Parallel Method Each n-bit word in host computer stores m k-bit values, n > mk Exploits logical instruction set of host Relatively inflexible and usually requires multiple passes x x y To Evaluate z z z/ z/ y/ x/ Fault positions Mask I z : fault positions for z Mask S z : fault values Basic evaluation : z = x.y Fault insertion : z* = z.i z + I z.s z John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 8

10 Deductive Method Fault Simulation The signal on each simulated line is a list L of all faults causing errors on that line. All faults can be simulated in one pass L a L b L k a b k... F z L a = list of faults causing errors on line a L a = list of faults not causing errors on line a L a L b L c a b c d L d = {d/} L a L b L c John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 9 Example Deductive Fault Simulation a b d i h c e f L a = {a }; L b = {b }; L d = {d } L c = L a L b {c } = {dc } L e = L c L d {e } = {c,d,e } L f = {f }; L g = L e {g } = {c,d,e,g } L h = {h }; L i = {i }; L d = {d } L j = L e {j } = {c,d,e,j } g j l k n m p John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 2

11 Deductive Fault Simulation Example (cont d) a b d i h c e f g j L k = L i L h {k }= {i,h,k } L l = L j {l }= {c,d,e,j,l } L m = L k L l {m } = {i,h,k,m } L n = L g L f {n } = {c,d,e,g,n } L p = L m L n {p } = {c,d,e,g,n,i,h,k,m,p } l k n m p John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 2 Approach Emulation Map target design into a network of field-programmable gate array (FPGA) ICs The programmed FPGA forms a hardware prototype of the design and can run at effective clock speed of, say, 5 MHz The emulated circuit can be instrumented as a logic analyzer to capture normal or faulty behavior Drawback Limited ability to do performance measurement John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 22

12 FPGA: Xilinx 3 series Emulation Interconnection switch box Interconnections Configurable logic block (cell) (a) Logic block Programmable connections (b) John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 23 Emulation System Emulation Host computer Host interface FPGA FPGA FPGA... FPGA FPGA Config. system Programmable interconnect John P. Hayes University of Michigan EECS 579 Fall 2 Lecture 23: Page 24

Testability. Shaahin Hessabi. Sharif University of Technology. Adapted from the presentation prepared by book authors.

Testability. Shaahin Hessabi. Sharif University of Technology. Adapted from the presentation prepared by book authors. Testability Lecture 6: Logic Simulation Shaahin Hessabi Department of Computer Engineering Sharif University of Technology Adapted from the presentation prepared by book authors Slide 1 of 27 Outline What