Introduction to Digital Logic Missouri S&T University CPE 2210 PLDs

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1 Introduction to Digital Logic Missouri S&T University CPE 2210 PLDs Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and Technology 14 February 2018 rev Egemen K. Çetinkaya

2 PLDs Outline Introduction PLDs Summary 2

3 Computer Organization Overview Egemen K. Çetinkaya 3

4 Computing Resources Overview What are the computing resources? Egemen K. Çetinkaya 4

5 Computing Resources Overview Computing resources are: CPU (central processing unit) memory bandwidth power What are the computer resource constraints? 5

6 Computing Resources Overview Computing resources are: CPU memory bandwidth power Computer resource constraints are: delay cost ($) 6

7 Programmable Logic Devices Overview PLD: Programmable Logic Device Electronic component for reconfigurable digital circuit Simple PLDs: PLA: Programmable Logic Array PAL: Programmable Array Logic GAL: Generic Array Logic Complex PLDs: arrangement of multiple PLDs FPGA: Field-Programmable Gate Array FPGAs generally use lookup table 7

8 Programmable Logic Devices General Structure Egemen K. Çetinkaya PLDs consist: buffers/inverters, AND array, OR array 8

9 Programmable Logic Devices Main Components PLDs consist: buffers/inverters, AND array, OR array Buffer: output is same as input but higher current signal AND array: inputs n variables (complemented or uncomplemented) outputs p product terms, which is input to OR array OR array outputs m sum-of-products 9

10 Programmable Logic Devices Programming Each input of array gate is connected to a fuse Fuse is removed to realize corresponding function E.g. AND gate is programmed by blowing fuse Fuses can be reprogrammable connections can be set to original conditions Erasing can be accomplished via: ultraviolet light or electrical signals 10

11 Programmable Logic Devices Notation Gates are drawn with a single line A cross at the intersection denotes intact fuse Unprogrammed AND gate: Programmed AND gate: ac Unprogrammed OR gate: Programmed OR gate: a+b 11

12 Programmable Logic Devices Notations for Special Cases Gates are drawn with a single line A cross at the intersection denotes intact fuse Fuses intact AND gate: Fuses intact OR gate: AND gate with nonfusible inputs: OR gate with nonfusible inputs: 12

13 Programmable Logic Arrays (PLAs) General Structure Both AND array & OR array is programmable for PLAs 13

14 Programmable Logic Arrays (PLAs) Main Components Both AND array & OR array is programmable for PLAs PLAs characterized by three numbers: the number of input lines n the number of product terms p the number of sum-of-products m E.g. n p m a typical PLA is

15 Programmable Logic Arrays (PLAs) What are the functions for the following PLA? Example x 1 x 2 x 3 Programmable connections P1 OR plane P2 P3 P4 AND plane f1 f2 15

16 Programmable Logic Arrays (PLAs) The functions for the following PLA are: P 1 = x 1 x 2 P 2 = x 1 x 3 P 3 = x 1 x 2 x 3 Example x 1 x 2 x 3 Programmable connections P1 P2 OR plane P 4 = x 1 x 3 f 1 = P 1 + P 2 + P 3 f 1 = x 1 x 2 + x 1 x 3 + x 1 x 2 x 3 P3 P4 f 2 = P 1 + P 3 + P 4 AND plane f 2 = x 1 x 2 + x 1 x 2 x 3 + x 1 x 3 MST CPE2210 PLDs 14 February f1 f2

17 Programmable Logic Arrays (PLAs) Example (Customary Schematic) The functions for the following PLA are: P 1 = x 1 x 2 P 2 = x 1 x 3 x 1 x 2 x 3 P 1 P 2 OR plane P 3 = x 1 x 2 x 3 P 4 = x 1 x 3 P 3 f 1 = P 1 + P 2 + P 3 P 4 f 1 = x 1 x 2 + x 1 x 3 + x 1 x 2 x 3 f 2 = P 1 + P 3 + P 4 AND plane f 2 = x 1 x 2 + x 1 x 2 x 3 + x 1 x 3 MST CPE2210 PLDs 14 February f 1 f 2

18 Programmable Logic Arrays (PLAs) POS Array vs. SOP Array SOP: AND-OR planes, POS: OR-AND planes x 1 x 2 x n x 1 x 2 x n Input buffers and inverters Input buffers and inverters x 1 x 1 x n x n x 1 x 1 x n x n P 1 S 1 AND plane P k OR plane OR plane S k AND plane f 1 f m f 1 f m 18

19 Programmable Array Logic (PAL) General Structure AND array is programmable & OR array is fixed 19

20 Programmable Array Logic (PAL) Main Components Both AND array & OR array is programmable for PLAs Only AND array is programmable in PAL OR array is fixed PAL is easier to program compared to PLA PAL is easier to cheaper compared to PLA PAL is less flexible than the PLA 20

21 Programmable Array Logic (PAL) Example What are the functions for the following PLA? x 1 x 2 x 3 P 1 P 2 f 1 P 3 P 4 f 2 AND plane 21

22 Programmable Array Logic (PAL) Example The functions for the following PLA are: P 1 = x 1 x 2 x 3 x 1 x 2 x 3 P 2 = x 1 x 2 x 3 P 3 = x 1 x 2 P 4 = x 1 x 2 x 3 f 1 = P 1 + P 2 f 1 = x 1 x 2 x 3 + x 1 x 2 x 3 P 1 P 2 P 3 P 4 f 1 f 2 f 2 = P 3 + P 4 AND plane f 2 = x 1 x 2 + x 1 x 2 x 3 MST CPE2210 PLDs 14 February

23 PLD and Programmer Example Egemen K. Çetinkaya Atmel PLD and XELTEK programmer 23

24 I/O block I/O block Egemen K. Çetinkaya Complex PLDs Architectural Components PAL-like block PAL-like block I/O block Interconnection wires PAL-like block PAL-like block I/O block PAL- or PLA-like blocks interconnected 24

25 Programmable Read-Only Memory Logic Diagram Decoder functions as AND-array: n input 2 n 1 output 25

26 Programmable Read-Only Memory PLD Notation OR-array results: 2 n input m outputs 26

27 Programmable Read-Only Memory Example Implement the following functions: f 1 (x 2,x 1,x 0 ) = (0,1,2,5,7) and f 2 (x 2,x 1,x 0 ) = (1,2,4,6) 27

28 Programmable Read-Only Memory Example (Truth Table) Implement the following functions: f 1 (x 2,x 1,x 0 ) = (0,1,2,5,7) and f 2 (x 2,x 1,x 0 ) = (1,2,4,6) Inputs Outputs x 2 x 1 x 0 f 1 f

29 Programmable Read-Only Memory Example (PROM Realization) Implement the following functions: f 1 (x 2,x 1,x 0 ) = (0,1,2,5,7) and f 2 (x 2,x 1,x 0 ) = (1,2,4,6) Inputs Outputs x 2 x 1 x 0 f 1 f

30 Programmable Read-Only Memory Example (PROM Realization) What is the word stored at the address 010? Inputs Outputs x 2 x 1 x 0 f 1 f

31 Programmable Read-Only Memory Example (PROM Realization) The word stored at the address 010 is f 1 f 2 = 11 Inputs Outputs x 2 x 1 x 0 f 1 f

32 PLDs Summary Computing resources are: CPU, memory, BW, power IC types are: off-the-shelf vs. manufactured off-the-shelf ICs: logic IC, PLD, FPGA manufactured IC: full-custom vs. semi-custom Simple PLDs: PLA: Programmable Logic Array: OR-AND or AND-OR planes PAL: Programmable Array Logic 32

33 References and Further Reading [V2011] Frank Vahid, Digital Design with RTL Design, VHDL, and Verilog, 2nd edition, Wiley, [G2003] Donald D. Givone, Digital Principles and Design, McGraw-Hill, [BV2009] Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 3rd edition, McGraw-Hill, [W2006] John F. Wakerly, Digital Design Principles and Practices, 4th edition, Prentice Hall,

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Introduction to Digital Logic Missouri S&T University CPE 2210 Combinatorial Circuit Analysis and Synthesis

Introduction to Digital Logic Missouri S&T University CPE 2210 Combinatorial Circuit Analysis and Synthesis Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science