Software Engineering 2DA4. Slides 8: Multiplexors and More

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1 Software Engineering 2DA4 Slides 8: Multiplexors and More Dr. Ryan Leduc Department of Computing and Software McMaster University Material based on S. Brown and Z. Vranesic, Fundamentals of Digital Logic with Verilog Design, 3rd Ed. c R.J. Leduc, M. Lawford 1

2 Multiplexers A two input multiplexer (mux) can be built using either transmission gates or sum-of-products form. T-gate implementation uses fewer transistors. c R.J. Leduc, M. Lawford 2

3 Multiplexers - 4 Inputs For 4 inputs, need 2 select lines s 0,s 1. Can build with three 2-input muxes or using S-of-P form. If using transmission gates, then using the three muxes is preferred as requires less transistors. c R.J. Leduc, M. Lawford 3

4 Multiplexers - 16 Inputs In general, an n-input mux has 1 output and log 2 (n) select lines. Below we see a 16 input mux. c R.J. Leduc, M. Lawford 4

5 Multiplexers Synthesizing Logic Functions Consider Figure below. Have function f with inputs w 1 and w 2, thus 2 2 = 4 possible input combinations. Can implement f using a 4-to-1 mux. Set s 1 = w 1 and s 0 = w 2. Then set the four inputs of the mux to match the values of the truth table of f. ie. the first input of the mux is set to the value of f for w 1 w 2 = 00 This is approach used for FPGA lookup tables (LUT). c R.J. Leduc, M. Lawford 5

6 Multiplexers Synthesizing Logic Functions - II Can implement using only a 2-to-1 mux. Consider truth table below that has been re-arranged. We see that f = w 2 when w 1 = 0 and that f = w 2 when w 1 = 1. We can thus use w 1 as our select input as in Figure below. c R.J. Leduc, M. Lawford 6

7 Shannon s Expansion Theorem Theorem provides the formal basis for circuit decomposition using muxes. Theorem Any Boolean function f(x 1,x 2,...,x n ) can be written as (is logically equivalent to): x 1 f(0,x 2,...,x n )+x 1 f(1,x 2,...,x n ) i.e. f(x 1,x 2,...,x n ) = x 1 f(0,x 2,...,x n ) +x 1 f(1,x 2,...,x n ) Here f(0,x 2,...,x n ) denotes f with x 1 set to 0. This is sometimes abreviated as f x1 =0 or f x1. So f = x 1 f x1 =0 +x 1 f x1 =1 = x 1 f x1 +x 1 f x1 c R.J. Leduc, M. Lawford 7

8 Shannon s Expansion Theorem - II More generally, for any i {1,...n}: f(x 1,...,x n ) = x i f(x 1,...,x i 1,0,x i+1,...x n ) +x i f(x 1,...,x i 1,1,x i+1,...,x n ) = x i f xi +x i f xi c R.J. Leduc, M. Lawford 8

9 Shannon s Expansion Theorem Example Consider f(w 1,w 2,w 3 ), a 3-input majority function. The function is true iff any two inputs are both true. f(w 1,w 2,w 3 ) = w 1 w 2 +w 1 w 3 +w 2 w 3 We decide to decompose in terms of input w 1. Since we are using one variable, we can only choose between two inputs, so we will use a 2-to 1 mux to implement. f = w 1 f w1 +w 1 f w1 = w 1 (0 w 2 +0 w 3 +w 2 w 3 )+w 1 (1 w 2 +1 w 3 +w 2 w 3 ) = w 1 (w 2 w 3 )+w 1 (w 2 +w 3 +w 2 w 3 ) 5a, 6a, 6b = w 1 (w 2 w 3 )+w 1 (w 2 +w 3 ) 13a c R.J. Leduc, M. Lawford 9

10 Shannon s Expansion Theorem Example - II Using: f = w 1 (w 2 w 3 )+w 1 (w 2 +w 3 ) We now take w 1 as the select input of our 2-to-1 mux, with w 2 w 3 connected to first input, and w 2 +w 3 connected to the second input. Which variable we choose to decompose in can result in different costs. See eg. 4.4 of text. c R.J. Leduc, M. Lawford 10

11 Shannon s Expansion Theorem Example - III If we wanted to implement f(w 1,w 2,w 3 ) using a 4-to-1 mux, we d have to decompose using two variables. If we take the results from decomposing using w 1 as our starting place, we could additionally decompose using a second variable, say w 2. f = w 1 (w 2 w 3 )+w 1 (w 2 +w 3 ) = w 2 f w2 +w 2 f w2 = w 2 (w 1 (0 w 3 )+w 1 (0+w 3 )) +w 2 (w 1 (1 w 3 )+w 1 (1+w 3 )) = w 2 (w 1 (0)+w 1 (w 3 ))+w 2 (w 1 (w 3 )+w 1 (1))) 5a, 5b, 6a, 6b = w 2 w 1 (0)+w 2 w 1 (w 3 )+w 2 w 1 (w 3 )+w 2 w 1 (1) 12a = w 2 w 1 f(0,0,w 3 )+w 2 w 1 f(1,0,w 3 ) +w 2 w 1 f(0,1,w 3 )+w 2 w 1 f(1,1,w 3 ) c R.J. Leduc, M. Lawford 11

12 Shannon s Expansion Theorem Example - IV Finally, if we use all three inputs as selections, we can implement f using an 8-to-1 mux by setting the 8 inputs of the mux to match the values from truth table. c R.J. Leduc, M. Lawford 12

13 Decoders Decoders are used to decode information. Decoders are commonly used in computer memories to decode memory accesses. In general, it has n inputs, 2 n outputs, and an enable input. Each input combination (code) is mapped to a unique output. Standard mapping is to use minterms. ie. minterm 0 maps to output 0. c R.J. Leduc, M. Lawford 13

14 2-to-4 Decoder c R.J. Leduc, M. Lawford 14

15 3-to-8 Decoder Can implement a 3-to-8 decoder using two 2-to-4 decoders. c R.J. Leduc, M. Lawford 15

16 4-to-16 Decoder Higher order decoders are commonly built using decoder trees. A 4-to-16 decoder example is shown below. c R.J. Leduc, M. Lawford 16

17 Read Only Memory (ROM) The two main type of memory devices in a computer are ROM (read only memory) and RAM (random access memory). ROM is memory that you cannot write to under normal operation. Some ROMs can be configured or programmed by the user (PROMs). If they can be erased, using ultraviolet light or a high voltage, and reprogrammed, they are called EPROMs or EEPROMs (Electrically Erasable Programmable ROM), respectively. ROMs are non-volatile - their contents remain the same when the system is powered off and turned back on. c R.J. Leduc, M. Lawford 17

18 Structure of ROMs A ROM has m inputs used to select from 2 m rows of data. A decoder is used to do the mapping. The m inputs, a 0,a 1,...,a m 1, are called address lines. Each row of data has n columns, and thus the ROM has n outputs, d 0,d 1,...,d n 1, called data lines. c R.J. Leduc, M. Lawford 18

19 Structure of ROMs - II Address lines select which row of data will appear at the n data lines. Output enable for the ROM is the Read line. When Read = 1, then data driven to the output, otherwise output is high impedance. To access data, apply desired address to address lines, and then set Read = 1. c R.J. Leduc, M. Lawford 19

20 ROM Example Below, we have four 2764 EPROMs (13 adress lines and 8 data lines) mapped onto a 14 bit address bus and a 16 bit data bus. The VPP and PGM inputs are used to program the EPROM. Address lines are A 0,A 1,...,A 12 and data lines are O 0,...,O 7. Input CS is an additional selection line used (ie. the chip does nothing unless CS = 0). The line OE drives the data onto the bus (ie ouput enable). c R.J. Leduc, M. Lawford 20

21 ROM Example - II Each EPROM has 2 13 eight bit memory locations. To create 16 bit memory locations, two EPROMS are paired (ie. U3 and U2). The outputs of the first chip (ie. U2) are connected to D 7...D 0, and the outputs of the second (ie. U3) to D 15...D 8. Both are attached to address lines A 12...A 0. To make use of address line A 13 of the CPU and to double the memory, A 13 is connected to CS input of the pair U1 and U0, and A 13 to CS input of the pair U2 and U3. When A 13 = 0, U1 and U0 are selected, otherwise U2 and U3. c R.J. Leduc, M. Lawford 21

22 ROM Example - III c R.J. Leduc, M. Lawford 22

23 Random Access Memory (RAM) Random Access Memory (RAM) is similar in structure to ROM, except it contains additional logic to store data. Like a ROM, it has address lines and data lines, but now the data lines can be either inputs or outputs. c R.J. Leduc, M. Lawford 23

24 Random Access Memory (RAM) - II The RAM has an additional control input called Write. When Write = 1, then the data on d 0...d n 1 is stored in the row indicated by the address lines. As inputs Read and Write should never be active at the same time, a RAM usually has a single input labelled Read/Write. c R.J. Leduc, M. Lawford 24

25 RAM Data Sheet 1 - a The next slide contains first page of a RAM data sheet. The chip has eight data lines (I/O 0 - I/O 7 ), and 11 address lines (A 0 - A 10 ). Chip can store 2 11 = 2048 bytes of data. For timing purposes, we will examine the CY6116A-35 version which has a a maximum access time of 35ns. Chip has an CE signal that enables/disables the chip. Chip has an WE signal used while writing to RAM. Chip has an OE signal used while reading from RAM. When CE = H or WE = L, the chip s data outputs are high impedance. c R.J. Leduc, M. Lawford 25

26 RAM Data Sheet 1 - b c R.J. Leduc, M. Lawford 26

27 RAM Data Sheet 2 Sheet shows operating limits for RAM. We are focussing on the -35 version. c R.J. Leduc, M. Lawford 27

28 RAM Data Sheet 3 Sheet shows timing information needed for waveforms on next page. Parameter t rc = 35ns specifies that when we do a read cycle, we must wait a minimum of 35ns before we can use chip again. Parameter t wc = 25ns specifies that when we do a write cycle, we must wait a minimum of 25ns before we can use chip again. c R.J. Leduc, M. Lawford 28

29 RAM Data Sheet 4 - Read Cycle The next two data sheets contain waveforms for read and write cycles for the RAM. A read cycle means an external device wants data from the RAM. To do a read cycle, we need CE = L, OE = L and WE = H. During read cycle, contents of RAM location specified by address lines show up at data I/O pins. Consider read cycle No. 2, where address lines are assumed to be valid before or at same time that CE goes low. Parameter t DOE specifies the maximum time you must wait from when CE goes low till data is valid at I/O pins. Parameter t HZOE specifies the maximum time you must wait from when OE goes high till I/O pins go high impedance. Parameter t RC specifies the minimum length that CE must stay low and the adress lines must stay valid. c R.J. Leduc, M. Lawford 29

30 RAM Data Sheet 4,5 - Write Cycle A write cycle means an external device wants to store data in the RAM. Write cycle occurs when CE is low and WE is low. Data at pins I/O 0 - I/O 7 is written to location specified by address pins. During write, when either CE or WE goes high, write cycle ends. Parameter t SD specifies setup time for data relative to end of write cycle. Data must stay valid for this time frame. Parameter t HD specifies hold time for data relative to end of write cycle. Data must stay valid for this time frame. Parameter t HZWE specifies maximum time from when WE going low to when RAM data outputs go high impedance. Parameter t WC specifies the minimum length that the address lines must stay valid. c R.J. Leduc, M. Lawford 30

31 RAM Data Sheet 4 - b c R.J. Leduc, M. Lawford 31

32 RAM Data Sheet 5 - b c R.J. Leduc, M. Lawford 32

33 Encoders An encoder is the opposite of a decoder. For a binary encoder, you have 2 n inputs into n outputs. Each input maps to one of the 2 n possible output combinations represented by the n outputs. c R.J. Leduc, M. Lawford 33

34 Priority Encoders Consider a priority encoder with 3 inputs x 3 x 2 x 1 and 2 outputs f 1 f 0. It indicates the highest priority input that is asserted, and masks the others. If x 3 = 1, f 1 f 0 = 11 else if x 2 = 1, f 1 f 0 = 10 else if x 1 = 1, f 1 f 0 = 01 else f 1 f 0 = 00 x 3 x 2 x 1 f 1 f x x x 1 1 x 3 x 2 x 1 f 1 f c R.J. Leduc, M. Lawford 34

Chapter 3 Combinational Logic Design

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