Overview. Programmable logic (PLAs & PALs ) Short-hand notation. Programming the wire connections
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1 Overview Programmable logic (PLs & PLs ) Last lecture "Switching-network" logic blocks Multiplexers/selectors emultiplexers/decoders Programmable logic devices (PLs) Regular structures for 2-level logic oncept: Large array of uncommitted N/OR gates ctually NN/NOR gates You program the array by making or breaking connections Programmable block for sum-of-products logic Today PLs PLs PLs ROMs Tristates esign examples inputs N array product terms OR array outputs 2 Programming the wire connections Short-hand notation Fuse: omes connected; break unwanted connections nti-fuse: omes disconnected; make wanted connections raw multiple wires as a single wire or bus signifies a connection efore Programming fter Programming F0 = + '' F = ' + F2 = '' + F3 = ' + ' ' '' '' ' ' F0 F F2 F3 3 F0 = + '' F = ' + ' F0 F 4
2 PL example PLs versus PLs F = F2 = + + F3 = ' ' ' F4 = ' + ' + ' F5 = xor xor F6 = xnor xnor F F2 F3 F4 F5 F Think of as a memory-address decoder Memory bits F F2 F3 F4 F5 F6 ''' '' '' ' '' ' ' 5 We've been looking at PLs Fully programmable N / OR arrays an share N terms Programmable array logic (PL) Programmable N array OR array is prewired No sharing Ns heaper and faster than PLs 6 Example: to Gray code converter Example (con t): Wire a PL W X Y Z X X X X 0 X X 0 0 X X X X X X 0 X X X X X X X 0 0 X 0 K-map for W X X 0 0 K-map for Y X X X X X X K-map for X X 0 0 X X X K-map for Z Minimized functions: W = + + X = ' Y = + Z = ''' + + ' + '' 7 W X Y Z 8
3 Example: Wire a PL ompare implementations Minimized functions: W = + + X = ' Y = + Z = ''' + + ' + ' What do we do with the unused N gates? PL: No shared logic terms in this example 0 decoded functions (0 N gates) PL: Z requires 4 product terms 6 decoded functions (6 N gates) 6 unused N gates This decoder is a poor candidate for PLs/PLs 0 of 6 possible inputs are decoded No sharing among N terms etter option? Yes a ROM 9 0 Read-only memories (ROMs) ROM details Two dimensional array of stored s and 0s Input is an address ROM decodes all possible input addresses Stored row entry is called a "word" ROM output is the decoded word n address lines inputs decoder 2 n word lines memory array (2 n words by m bits) outputs Similar to a PL but with a fully decoded N array ompletely flexible OR array (unlike a PL) Extremely dense: One transistor per stored bit 2 n- 2 decoder 0 0 n- ddress +5V 0 m- Outputs Only one word line is active at any time it lines: Normally pulled high through resistor. If transistor stores a zero, then line pulls low when row is selected 2
4 Two-level combinational logic using a ROM Use a ROM to directly store a truth table No need to minimize logic Example: F0 = '' + '' + ' F = '' + '' + F2 = ''' + '' + '' F3 = ' + '' + ' F0 F F2 F ROM 8 words x 4 bits/word F 0 F F 2 F 3 address outputs You specify whether to store or 0 in each location in the ROM ROMs versus PLs/PLs ROMs enefits Quick to design, simple, dense Limitations Size doubles for each additional input an't exploit don't cares PLs/PLs enefits Logic minimization reduces size Limitations PL OR-plane has hard-wired fan-in nother answer: Field programmable gate arrays Learn about in Loose end: Tristates Tristate buffers have a control input Enabled: uffer works normally isabled: uffer output is disconnected Example: to 7-segment display controller The problem Input is a 4-bit digit (,,, ) Need signals to drive a display (7 outputs 0 6) 2: Tristate Mux module muxtri (In,In2,Sel,OUT); input In,In2,Sel; output OUT; In OUT tri OUT; bufif (OUT,In,Sel); bufif0 (OUT,In2,Sel); endmodule In2 Sel c5 c4 c0 c6 c c2 c3 c0 c c2 c3 c4 c5 c6 to 7 segment control-signal decoder 5 6
5 Formalize the problem Sum-of-products implementation Truth table Many don t cares hoose implementation target If ROM, we are done on't cares imply PL/PL may be good choice Implement design Minimize the logic Map into PL/PL unique product terms if we minimize individually 0 X 0 X 0 X 0 X X 0 X 0 X 0 X 0 0 X X 0 X X 0 X 0 = ' ' = ' ' + + ' 2 = + ' + 3 = ' ' + ' + ' + ' 4 = ' ' + ' 5 = + ' ' + ' + ' 6 = + ' + ' + ' 0 X 0 X X 0 0 X X 0 0 X X 7 8 etter SOP implementation PL implementation an do better than 5 product terms 2 Share terms among outputs only 9 unique product terms Each term not necessarily minimized 0 = '' = '' + + ' 2 = + ' + 3 = '' + ' + ' + ' 4 = '' + ' 5 = + '' + ' + ' 6 = + ' + ' + ' 2 0 = ' + + '' + ' + = ' + '' + + '' 2 = ' + ' + '' + + ' 3 = ' + ' + '' + ' 4 = '' + ' 5 = ' + '' + + ' 6 = ' + ' + ' = ' + + '' + ' + = ' + '' + + '' 2 = ' + ' + '' + + ' 3 = ' + ' + '' + ' 4 = '' + ' 5 = ' + '' + + ' 6 = ' + ' + ' ' ' ' ' '' '' ' 20
6 Example: Logical function unit Formalize the problem and solve Multipurpose functional block 3 control inputs () specify function 2 data inputs (operands) and output (same bit-width as input operands) 0 2 Function omments always logical OR 0 0 ( )' logical NN 0 xor logical xor 0 0 xnor logical xnor 0 logical N 0 ( + )' logical NOR 0 always 0 3 control inputs: 0,, 2 2 data inputs:, output: F 0 2 F Implementation choice: multiplexer with discrete gates : MUX S2 S S0 0 2 F 2 22 Pal Feature: Tri-stated outputs Pal Feature: Individually Tri-stated outputs Enable (ctive Low) Enable (ctive Low) 23 24
7 Pal Feature: Feedback terms Pal Feature: Registered outputs Pal Feature: Registers with bypass multiplexers 27
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