Unit 9. Multiplexers, Decoders, and Programmable Logic Devices
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1 Unit 9. Multiplexers, Decoders, and Prograable Logic Devices
2 Multiplexers (Data Selectors) I I I 4 to MU Z I 3 I I I 7 8 to MU Z C 4 Z I I I I 8 Z C I CI C I n Z C I n k k I k 4 CI 5 CI 3 6 CI CI 3 7 I I n - n to MU n Control inputs Z
3 Quad Multiplexer to to Select Data 3
4 4-to- MU to realize 3-variable 3 function Ex (,, C) C C ( ) C C 4
5 8-to- MU to to realize 4-variable function C C D C D CD C (DD ) C (DD ) (CC )D ( )C D ( ) CD C C D C C C D D D D D D I I I I 3 I 4 I 5 I 6 I 7 8 to MU Z C C D D C C D 5
6 6 D I D I D I D I I I D I I D C n n n I I I I I I L L L CD D C D C C CD D C CD D C C CD C C (DD ) C (DD ) (CC )D ( )C D ( ) CD
7 Three - state buffers uffers to increase the driving capability of a gate output Tri-state uffers perits gate outputs to be connected together 7
8 Truth tables Truth C Z Z Table Data selection using three-state buffers 8
9 Circuits with two three state buffers S S S Z S Z Z 9
10 pplication of of three-state buffer. us. Chip I/O
11 Decoders Generate all of the inters of inputs a b c Y Y Y Y3 Y4 Y5 Y6 Y7 a b c y a b c y a b c y7 abc 7
12 C y y y y y y 3 -to-4 decoder y y y y 3 y 7
13 3 C D D C CD input Decial Output
14 Realization of a ultiple output circuit using a decoder C D 4-to- Line Decoder to - Decoder 來 realize y DeMorgan s law 4
15 5 Encoders x x d c b a y7 y6 y5 y4 y3 y y y priority
16 6 Read Only Meory function(s) output oolean ultiple realize circuit to LSI n C 3 Inputs Outputs ROM 8words 4bits C Stored in ROM ( 3 words of 4 bits each)
17 7 General or n inputs outputs ROM n words bits L L L L L L L L n words n inputs outputs
18 w w w w 3 w w w w 3 n inputs decoder n words Meory array n words bits asic ROM structure outputs 8
19 ROM as logic devices (use decoder and diodes) C 3 C 3-to-8 decoder word line OR-Plane 9
20 (,,4,6) (,3,4,6,7) (,,,6) 3 (,3,5,6,7) Expressed with dots C 3-to-8 decoder v v v v v v v v v v v v v v v v 3 ()Use "ask" to progra ROM ()EPROM electrically progra (3)EEPROM UV light erase
21 Prograable LogicDevices Various kinds PL, PLs n realizes PL, functions with n EPLD, inputs. V PEEL, GL n -level ND rray (plane) not n OR rray (plane) SOP ipleentation ROM directly ipleent truth table C C If any of, C C GND i.e. or C not activiated, ND plane V C ZC
22 C 3 OR plane C C C Y Y Input C V V V V V C C C C 3 Output
23 Equivalent ND - OR rray C OR array C C C ND array C C C 3 C 3
24 Exaple ( ),3,5,7,8,9,,,3,5 (,3,5,6,7,,,4,5) ( 6,7,8,9,3,4,5) Miniized ultiple output expressions (using K - ap) 3 abd abd abc bc c abd bc abc abd PL table a b c d 3 4
25 5 a b c 3 d Word line Inputs Outputs PL structure d c b a 3rd rows selected, no rows are selected, (6th) (5th) (st row),5,6 rows selected, > > ieldprograable PL prograable PL Mask d c b a 3
26 PLs n realizes functions with n inputs. C special case of PL. ND array prograble OR array NOT prograble C I I 4 5 I 8 I I I I I 6
27 Soe typical available PLs Type No.* H8 H6 4H4 6H 6C C L8 L6 4L4 6L L 4L8 6L6 8L4 L 6L8 L8 L No.of Inputs No.of Outputs Gate Configuration ND - OR ND - OR ND - OR ND - OR ND - OR/NOR ND - OR/NOR ND - NOR ND - NOR ND - NOR ND - NOR ND - NOR ND - NOR ND - NOR ND - NOR ND - NOR ND - NOR ND - NOR ND - NOR No. of Inputs per OR GTE 4,,,,, ,,,,, ,,,,,,4 4,4,,,, H L C active H active L both active H and L 7
28 Internal Logic diagra 4L4 H6 Nuber of inputs to an OR gate fixed and liited. 8
29 9 Exaple Converter SC inary to Digit l Hexadecia E D C Digit Z Y W Code for Hex Digit Hex SC Input Truth table PL W Y Z Network L6 H6 or 5 output functions 4 input variables
30 Use K - ap ethod 4 4 W Y W WY 3 WY WYZ YZ WY WY YZ Y WYZ 3 W Y W Z Y WYZ WZ YZ WZ WYZ WZ WYZ WZ YZ 4 inputsndto OR H6not available 3inputsNDto OR W (Z Y) W connected back to one input H6 CD progras are available. 3
31 PLD Suary ND rray OR rray PL Prograable Prograable PL Prograable ixed ROM ixed Prograable Not Prograable ixed ixed 3
32 Coplex Prograable Logic Devices (CPLD) Integrate and interconnect any PLs and PLs on a single chip PL to for cobinational logic Macro Cell Register for Sequential Logic Pass Through for Cobinational Logic I/O Cell Three State uffer for idirectional I/O Input Latch to synchronize inputs loating Gate Prograable PL ilinx CR354L CPLD 3
33 CPLD unction block an acrocell 33
34 ield Prograable Gate rray (PG) n IC that contains an array of identical logic cells with prograable interconnections Layout of a typical PG 34
35 CL configurable logic block 35
36 Decoposition of switching functions Shannon s expansion theore (x, x, x i-, x i, x i, ) x i f x i f 36
37 Realization of 5- and 6-variables functions with function generators 37
38 Hoework of Chap.9.(a)
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