Last Name Student Number. Last Name Student Number [5] Q1. Circuit analysis. [2] (a) For the following circuit, give the truth table.

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1 Last Nae Student Nuber University of Toronto Faculty of pplied Science and Engineering Departent of Electrical and Coputer Engineering Midter Exaination ECE F - Digital Systes Tuesday October,, : : p Last Nae Student Nuber [] Q. Circuit analysis. [] (a) For the following circuit, give the truth table. Duration: 9 inutes Exainers: S Brown, J. Rose, K. Truong and B. Wang NSWER LL QUESTIONS ON THESE SHEETS, USING THE BCK SIDE IF NECESSRY.. No calculator and no cellphones are allowed.. The nuber of arks available for each question is indicated in the square brackets []; each portion of a question also shows how any arks are allocated to it.. There are two extra blank pages at the end of the test for rough work. ID LLOWED: The Course Textbook, Fundaentals of Digital Logic with Verilog Design. NSWER: (Marking schee:. arks for each row) x y f Last Nae: First Nae: Student Nuber: Lecture Section: Section (Rose) [ ] Section (Wang) [ ] Section (Brown) [ ] Section (Truong) [ ] Total vailable Marks: Question 8 Total Marks vailable Marks chieved Page of Page of

2 Last Nae Student Nuber Q, continued. [] (b) For the following circuit, give the truth table. Last Nae Student Nuber [] Q In Section. of the textbook, circuits that turn a siple light, L, on or off are used to illustrate soe basic logic functions. This questions involves soe siilar circuits with switches controlled by inputs x, y, or z. [] (a) Consider the circuit diagra shown below. You are to write logic expressions, in su-ofproducts (SOP) for, for the functions L and L where each of these functions is when the light is on and when the light is off. Higher arks will be given for deterining the siplest SOP expression possible. NSWER: (Marking schee: -. arks for each incorrect row) x y z f NSWER (it is not necessary to show the steps used to derive your answer): L =!xy!y!z L = x!z yz (. arks) (. arks) If a consensus ter is present (!x!z in L and xy in L) then -. for each consensus ter. Other accepted solutions: L = x!y!z!xyz!x!z L = x!y!z!xyz xy (. arks) (. arks) -. if the equation is not in Su of Products for. Page of Page of

3 Last Nae Student Nuber Q, continued. [] (b) ssue now that we need to ipleent a circuit that drives only light L fro part (a). Draw the siplest circuit you can with switches like those shown in part (a) that ipleents only L. Higher arks will be given for a circuit that uses as few switches as possible. NSWER (it is not necessary to show the steps used to derive your answer): Last Nae Student Nuber [9] Q. For this question you are to use algebraic anipulation to produce inial cost su-of-products (SOP) or product-of-sus (POS) expressions. You need to show your work and the steps that are being used in your solution. Higher arks will be given for solutions that apply the theores and identities of Boolean algebra in as few steps as possible. So, you are to show all of your steps, but don t use ore steps than needed. [] (a) Use Boolean algebra to iniize the following expression. Your final answer should be the inial cost su-of-products (SOP) for for this function.!x y S-----S !y!z S-----S----- L NSWER: f = yz ( x z)( x y z) f = y!z (!z (!x)(x y)) by Distribution = y!z!z!xy by Distribution, and!x x = =!z!x y by bsorption arks for correct solution using OR-based distribution (SOP) arks when diagra shown here corresponds to equation for L in part a, even if part (a) is wrong. Subtract. for any unnecessary switches, or switches with ore or fewer than terinals. arks are given when logic gates are used to represent the function, instead of switches. arks for correct solution using ND-based distribution (POS) ark for incorrect solution, but evidence of correct application of logic reduction rules is shown. if reduction akes no sense, no work is shown except for the final answer, or a K-ap is used to iniize the logic function. Page of Page of

4 Last Nae Student Nuber Q, continued. [] (b) Use Boolean algebra to iniize the following expression. Your final answer should be the inial cost su-of-products (SOP) for for this function. Last Nae Student Nuber Q, continued. [] (c) Use Boolean algebra to iniize the following expression. Your final answer should be the inial cost product-of-sus (POS) for for this function. NSWER: f = x z x y x y y z f = x!z!yz x!y xy!x!y Consensus = x(!y y)!y(x!x) x!z!yz = x!y x!z!yz = x!y arks for correct solution using logical progression of anipulations arks for alost correct solution ark for incorrect solution, but evidence of correct application of logic reduction rules is shown. if reduction akes no sense, no work is shown except for the final answer, or a K-ap is used to iniize the logic function. NSWER: f = y xz xz!f =!(y xz!x!z) =!y!(xz)!(!x!z) by demorgan =!y (!x!z)(x z) by demorgan =!y (!xz!zx) by Distrbution =!y!xz!y!zx f =!(!y!xz!y!zx) =!(!y!xz)!(!y!zx) by demorgan = (x y!z)(!x y z) by demorgan arks for correct solution using logical progression of anipulations arks for correct solution, but not inial ark for incorrect solution, but evidence of correct application of logic reduction rules is shown. Solution not in POS for if reduction akes no sense, no work is shown except for the final answer, or a K-ap is used to iniize the logic function. Page of Page 8 of

5 Last Nae Student Nuber [8] Q. Karnaugh aps. [] (a) For the Karnaugh ap shown below, derive the inial cost su-of-products (SOP) for for the logic function f (x,y,z). xy z NSWER: (Marking schee: -. arks for each issing ter) f=x y y zx zxyz [] (b) Derive the inial cost product-of-sus (POS) for for the logic function f (a,b,c,d). ab cd NSWER: (Marking schee: -. arks for each issing ter) Last Nae Student Nuber [] Q. student in ECE has been asked to wire up a single TTL LS QUD -input NND gate chip (the pin-out of which is given below) to ipleent the logic function F = B CD. Below you will see the wiring diagra that student has created. The circuit doesn t work because it has exactly three errors or oissions. Your answer, on the next page, should be the changes that need to be ade to the circuit to ake it function correctly. For exaple, a change could be connect pin to pin. Pin-out Diagra for the LS: LS/ Vcc 9 Gnd 8 Quad -input NND Below is the wiring diagra of the student s circuit; V f=(b c)(ac d )(abd)(a c d) [] (c) Derive the inial cost su-of-products (SOP) for for the logic function f (a,b,c,d,e). Note that is a don t care output. E= e= ab ab cd cd B F 9 8 C D NSWER: (Marking schee: ark for each correct ter) f=b d ac d cd e abcde b e (question continues on next page) Page 9 of Page of

6 Last Nae Student Nuber Page of Q, continued. Working space: nswers: Circuit Error #: Connect Ground to Pin [ arks] Circuit Error #: Connection fro Pin to should be Pin to Pin 8 [ arks] Circuit Error #: Connection fro D to pin 8 should be fro D to Pin [ arks] Last Nae Student Nuber Page of [8] Q. Word proble [] (a) useu has three roos, each with a otion sensor (,, and ) that outputs when otion is detected. t night, the only person in the useu is one security guard who walks (i.e. no standing still, or sitting, or sleeping) fro roo to roo. Give a truth table for the security syste that sounds an alar (by setting an output to ) if otion is ever detected in ore than one roo at a tie. (Hint: be sure to include any don t care in the output.) Marking schee: ark for x arks for the reaining entries [] (b) Now consider a useu with roos. truth table is not a good choice (it has too any rows), nor is an equation describing when the alar should sound (it has too any ters). However, the inverse of the alar function can be straightforwardly captured as a logic equation, and then the desired circuit () can be achieved by adding an inverter to the inverse function ( ). Design the -roo security syste by expressing the inverse of the alar function, (,,,,,, ). = or ) ( ) )( ( ) )( ( ) )( ( = Marking schee: arks for the correct answer -. ark for each wrong product / su ter - ark for issing the long bar in the POS for X

7 Last Nae Student Nuber [] Q. The following scheatic represents a prograable logic device that has been prograed. ssue that when two wires that cross are annotated as follows: Last Nae Student Nuber Q, continued. [] (a) Redraw the circuit in the siplest for you can. it eans that the wires are connected, while wires that cross without the X are not connected. lso, assue that gates whose inputs are not connected to anything will take those inputs as a logical. B C P B Q P arks; part arks if soething sensible. - if islabeled inputs/outputs -. for a careless istake - if unsiplified Q [] (b) What is this circuit? nswer: Set-Reset Latch (R-S) Latch ( arks) If give P = ( Q) and Q = (B P) only get ark If answer is just latch then give. arks. (question continues on next page) Page of Page of

8 Last Nae Student Nuber [] Q8. Consider the circuit shown below. ssue there are no propagation delays in the gates and in the D flip-flop. Draw the tiing diagra showing D, E, F, G and H. B C Clock D F G E D SET CLR Q Q H Clock B C D E F G H XXXXXX Marking schee: ark each for the correct D, E, F and G arks for the correct H (-. ark for issing XXXXXX) Page of