7.1. Unit 7. Minterm and Canonical Sums 2- and 3-Variable Boolean Algebra Theorems DeMorgan's Theorem Simplification using Boolean Algebra

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1 7.1 Unit 7 Minterm and Canonical Sums 2- and 3-Variable Boolean Algebra Theorems DeMorgan's Theorem Simplification using Boolean Algebra

2 CHECKERS / DECODERS 7.2

3 7.3 Gates Gates can have more than 2 inputs but the functions sta the same AND = output = 1 if ALL inputs are 1 Outputs 1 for onl 1 input combination OR = output = 1 if ANY input is 1 Outputs 0 for onl 1 input combination X Y Z F X Y Z F F F input AND 3-input OR

4 7.4 Checkers / Decoders An AND gate onl outputs 1 for 1 combination That combination can be changed b adding inverters to the inputs We can think of the AND gate as checking or decoding a specific combination and outputting a 1 when it matches. X Y Z F X Y Z F F F AND gate decoding (checking for) combination AND gate decoding (checking for) combination

5 7.5 Checkers / Decoders Place inverters at the input of the AND gates such that F produces 1 onl for input combination {,,} = {010} G produces 1 onl for input combination {,,} = {110} X Y Z F X Y Z G F G AND gate decoding (checking for) combination AND gate decoding (checking for) combination

6 7.6 Checkers / Decoders An OR gate onl outputs 0 for 1 combination That combination can be changed b adding inverters to the inputs We can think of the OR gate as checking or decoding a specific combination and outputting a 0 when it matches. OR gate decoding (checking for) combination 010 F X Y Z F OR gate decoding (checking for) combination 110 F X Y Z F

7 7.7 Decoder Eercise Compilers translate software to instructions that tell the processor to ADD, LOAD from Memor, Store to Memor, etc. These instructions are binar codes The processor must decode the instruction Create an AND gate decoder for each instruction tpe in the table that will produce '1' when that instruction is about to be eecuted Instruction Tpe 6-bit OPCODE OP[5:0] ADD LOAD STORE BRANCH ADD LOAD STORE

8 7.8 Circuit Design and Analsis There are two basic tasks as a digital design engineer Circuit Design/Snthesis: Take a set of requirements or functional descriptions and arrive at a logic circuit Circuit Analsis: Given a logic circuit, find or verif the logic function it implements Circuit Design Problem specification and requirements Truth Tables Boolean Algebra Canonical Sums/Products Karnaugh Maps CAD tools A B Circuits and Equations F Circuit Analsis C

9 7.9 Outcomes The goal of this unit is to teach ou how ou can construct a digital circuit to implement ANY combinational logic function (usuall epressed as a truth table) Eample: Given a truth table, build a circuit from ANDs and ORs that will implement the function specified b the truth table

10 SYNTHESIZING LOGIC FUNCTIONS 7.10

11 Primes between s Count of Inputs 7.11 The Problem Given a logic function, how do we arrive at a circuit to implement this combinational function? Rather than tring to solve the problem all at once we will do it in two steps: Use gates to convert raw inputs (e.g.,,) to intermediate signals; Convert the intermediate signals to produce the output (e.g. P) X Y Z P I3 I2 I1 C1 C

12 7.12 Using Decoders to Implement Functions Given an an logic function, it can be implemented with the superposition of decoders/checkers X Y Z F

13 7.13 Using Decoders to Implement Functions Given an an logic function, it can be implemented with the superposition of decoders X Y Z F A X Y Z A

14 7.14 Using Decoders to Implement Functions Given an an logic function, it can be implemented with the superposition of decoders X Y Z F A X Y Z A B B

15 7.15 Using Decoders to Implement Functions Given an an logic function, it can be implemented with the superposition of decoders X Y Z F A X Y Z A B C B C

16 7.16 Using Decoders to Implement Functions Given an an logic function, it can be implemented with the superposition of decoders X Y Z F A X Y Z A B C F B F C

17 7.17 Using Decoders to Implement Functions Given an an logic function, it can be implemented with the superposition of decoders X Y Z F A 0 X Y Z A B C F B 1 F C F(1,0,0) = 1

18 7.18 Using Decoders to Implement Functions Given an an logic function, it can be implemented with the superposition of decoders X Y Z F A 1 X Y Z A B C F B 0 F C F(0,1,0) = 1

19 7.19 Using Decoders to Implement Functions Given an an logic function, it can be implemented with the superposition of decoders X Y Z F A 0 X Y Z A B C F B 0 F C F(0,1,1) = 0

20 7.20 Defining Minterms We call an AND gate checking for one specific combination of all the inputs (one line in the truth table) a minterm Write the epression for each minterm of 3 variables:,, Minterms Row # Abbrev Minterm Epression m 0 m 1 m 2 m 3 m 4 m 5 m 6 m 7 0 m m m m m m m m

21 7.21 Checkers / Decoders The m i functions on the previous slide are just AND gate checkers That combination can be changed b adding inverters to the inputs We can think of the AND gate as checking or decoding a specific combination and outputting a 1 when it matches. X Y Z F X Y Z F m m AND gate decoding (checking for) combination AND gate decoding (checking for) combination

22 7.22 Appling Minterms to Snthesie a Function Each numbered minterm checks whether the inputs are equal to the corresponding combination. When the inputs are equal, the minterm will evaluate to 1 and thus the whole function will evaluate to 1. P use m m m m 7 P = m 2 + m 3 + m 5 + m 7 = when,, = {0,1,0} = 2 then P = = = 1 when,, = {1,0,1} = 5 then P = = = 1 when,, = {0,0,1} = 5 then P = = = 0

23 7.23 Definitions Literal: A single bit variable or its inverse Good:, ', ALARM' Bad: (+) Product Term: A single literal b itself or an AND'ing (not NAND'ing) of literals Good:,, ALARM PANIC ENABLED BAD: ( )', ALARM (PANIC+ENABLED) Minterm: A product term where all the input variables of a function appear as eactl one literal f(,,) => ++

24 7.24 Minterms Consider F(A,B) One minterm per combination of the input variables Onl one minterm can evaluate to 1 at an time m 0 m 1 m 2 m 3 A B F A B A B A B A B

25 7.25 Finding Equations/Circuits Given a function and checkers (called decoders) for each combination, we just need to OR together the checkers where F = 1 3-bit number {,,} Checker for 000 Checker for 001 Checker for 010 Checker for 011 Checker for 100 Checker for 101 Checker for 110 Checker for 111 Assume we use ANDgate decoders that output a 1 when the combination is found F X Y Z F

26 7.26 Canonical Sums Given a T.T., together all the minterms where F = _ ( = SUM or OR of all the minterms) F = m 2 +m 3 +m 5 +m 7 =(X'YZ')+(X'YZ)+ (XY'Z)+(XYZ) Canonical Sum: F = (2,3,5,7) List the minterms where F is 1. m 0 m 1 m 2 m 3 m 4 m 5 m 6 m 7 X Y Z F

27 7.27 Using OR-gate checkers AN ALTERNATIVE

28 7.28 OR-Gate Checkers / Decoders An OR gate onl outputs 0 for 1 combination That combination can be changed b adding inverters to the inputs We can think of the OR gate as checking or decoding a specific combination and outputting a 0 when it matches. OR gate decoding (checking for) combination 010 F X Y Z F OR gate decoding (checking for) combination 110 F X Y Z F

29 7.29 Finding Equations/Circuits Given a function and checkers (called decoders) for each combination, we just need to AND together the checkers where F = 0 3-bit number {,,} Checker for 000 Checker for 001 Checker for 010 Checker for 011 Checker for 100 Checker for 101 Checker for 110 Checker for 111 Assume we use ORgate decoders that output a 0 when the combination is found F X Y Z F

30 7.30 Defining Materms We call an OR gate checking for one specific combination of all the inputs (one line in the truth table) a materm Write the epression for each materm of 3 variables:,, Materms Row # Abbrev Materm Epression M 0 M 1 M 2 M 3 M 4 M 5 M 6 M 7 0 M M ' M 2 + ' M 3 + ' + ' M 4 ' M 5 ' + + ' M 6 ' + ' M 7 ' + ' + '

31 7.31 Appling Materms to Snthesie a Function Each output that should produce a '0' can be checked-for with an OR gate We refer to that OR-gate checker as a Materm of the function (M i ) We then AND together the materms P use M M M M P = M 0 M 1 M 4 M 6 = (++) (++ ) ( ++) ( + +) when,, = {0,0,1} = 1 then P = (0+0+1) (0+0+1 ) (0 +0+1) ( ) = = 0 when,, = {1,1,0} = 6 then P = (1+1+0) (1+1+0 ) (1 +1+0) ( ) = = 0 when,, = {1,1,1} = 7 then P = (1+1+1) (1+1+1 ) (1 +1+1) ( ) = = 1

32 7.32 Canonical Products Given a T.T., AND together all the materms where F = 0 F = M 0 M 1 M 4 M 6 =(X+Y+Z) (X+Y+Z') (X'+Y+Z) (X'+Y'+Z) M 0 M 1 Canonical Product: F = (0,1,4,6) List the materms where F is 0. M 2 M 3 M 4 M 5 M 6 M 7 X Y Z F

33 7.33 Definitions Literal: A single bit variable or its inverse Good:, ', ALARM' Sum Term: A single literal b itself or an OR'ing (not NOR'ing) of literals Good:, '+, ALARM+PANIC+ENABLED BAD: (+)', ALARM (PANIC+ENABLED) Materm: A sum term where each input variable of a function appears as eactl one literal f(,,) =>

34 7.34 You are onl responsible for Canonical Sums (not Products) LOGIC FUNCTION NOTATION

35 7.35 Boolean Algebra Terminolog SOP (Sum of Products) Form: An SOP epression is a logical sum (OR) of product terms Correct Eamples: [ + w + a b c], [w + + ] Incorrect Eamples: [ + w (a+b) ], [ + ( ) ] POS (Product of Sums) Form: A POS epression is a logical product (AND) of sum terms. Correct Eamples: [(+ +) (w +) (a)], [ (+) (w +)] Incorrect Eamples: [ + (+w)], [(+) (+) ] SOP equations ield 2-level circuits with AND gates in the 1 st level with OR gates in the 2 nd (aka AND-OR circuits) POS equations ield 2-level circuits with OR gates in the 1 st level with OR gates in the 2 nd (aka OR-AND circuits) AND-OR OR-AND =

36 7.36 Check Yourself Epression w ( ) + + w ++(w ) (w+ +)(w+) (w+)(w +) w + w + w++ SOP / POS / Both / Neither Neither (Can t have complements of sub-epressions onl literal) SOP (parentheses are unnecessar) POS POS (a single literal is a sum term) SOP (redundanc doesn t matter) Both (individual literals are both a product and sum term)

37 7.37 Canonical Sums & Products Canonical Sum: An SOP epression where all the product terms are minterms (i.e. have each literal in each product term) Canonical Product: A POS epression where all the sum terms are materms (i.e. each literal in each sum term) Canonical Sum: F = (2,3,5,7) F = m 2 +m 3 +m 5 +m 7 =(X'YZ )+(X'YZ)+(XY Z)+(XYZ) Canonical Product: F = (0,1,4,6) F = M 0 M 1 M 4 M 6 = (X+Y+Z) (X+Y+Z') (X'+Y+Z) (X'+Y'+Z) X Y Z F

38 7.38 Logic Functions A logic function maps input combinations to an output value ( 1 or 0 ) 3 possible representations of a function Equation (canonical form or simplified) Schematic Truth Table Can convert between representations Truth table is onl unique representation* * Canonical Sums/Products (minterm/materm) representation provides a standard equation/schematic form that is unique per function

39 7.39 Unique Representations Truth Tables along with Canonical Sums and Products specif a function uniquel Canonical => Same functions will have same representations Equations/circuit schematics are NOT inherentl canonical Truth Table P P, Canonical Sum (2,3,5,7 ), ON-Set of P (minterms) Yields SOP equation, AND-OR circuit P, Canonical Product (0,1,4,6 ), OFF-Set of P (materms) Yields POS equation, OR-AND circuit

40 7.40 Finding simplified equations and circuits 2- AND 3-VARIABLE THEOREMS

41 7.41 Wh Boolean Algebra We can alread convert an truth table that we derive into an equation and circuit b using canonical sums/products But canonical sums/products ield the LARGEST equation/circuit B starting with canonical form and then using Boolean algebra to simplif, we can arrive and smaller (even minimal) circuits

42 & 3 Variable Theorems T6 X+Y = Y+X T6' X Y = Y X Commutativit T7 (X+Y)+Z = X+(Y+Z) T7' (X Y) Z = X (Y Z) Associativit T8 XY+XZ = X(Y+Z) T8 (X+Y)(X+Z) = X+YZ Distribution & Factoring T9 X + XY = X T9 X(X+Y) = X Covering T10 XY + XY = X T10 (X+Y)(X+Y ) = X Combining T11 XY + X Z + YZ = XY + X Z T11 (X+Y)(X +Z)(Y+Z) = (X+Y)(X +Z) Consensus DM (X+Y)' = X' Y' DM' (X Y)'=X'+Y' DeMorgan's

43 7.43 Proofs Through Other Theorems T8 XY+XZ = X(Y+Z) T8 (X+Y)(X+Z) = X+YZ Prove T9: X + XY = X X(1 + Y) = X [T8] X(1) = X [T2] X = X [T1'] Prove T10: XY + XY' = X X(Y + Y') = X [T8] X(1) = X [T2] X = X [T1'] Prove T10': (X+Y)(X+Y')=X XX + XY' + XY + YY' = X [T8 / FOIL] X + XY' + XY + 0 = X [T3 and T5'] X(1 + Y' + Y) = X [T1, T8] X = X [T2, T1'] T9 X + XY = X T9 X(X+Y) = X T10 XY + XY = X T10 (X+Y)(X+Y ) = X T11 XY + X Z + YZ = XY + X Z OR X + YY' = X [T8'] X + 0 = X [T5'] X = X [T1] T11 (X+Y)(X +Z)(Y+Z) = (X+Y)(X +Z)

44 7.44 DeMorgan s Theorem Inverting output of an AND gate = inverting the inputs of an OR gate Inverting output of an OR gate = inverting the inputs of an AND gate A function s inverse is equivalent to inverting all the inputs and changing AND to OR and vice versa A B Out A B Out A B A+B A B Out A B Out A+B Analog: Turning a gate "inside-out" (like our socks). A B

45 7.45 DeMorgan s Theorem F = (X+Y) + Z (Y+W) Use DeMorgan s theorem to simplif "move" inversions (either to break-up "big bars" or join "small bars" F = (X+Y) + Z (Y+W) F = (X+Y) (Z (Y+W)) F = (X Y) (Z + (Y+W)) F = (X Y) (Z + (Y W))

46 7.46 Generalied DeMorgan s Theorem F (X 1,,X n,+, ) = F(X 1,,X n,,+) To find F, swap AND s and OR s and complement each literal. However, ou must maintain the original order of operations. Note: This parentheses doesn t matter (we are just OR ing X, Y, and the following subepression) F = (X+Y) + Z (Y+W) F = X+Y + (Z (Y+W)) Full parenthesied to show original order of ops. F = X Y (Z + (Y W)) AND s & OR s swapped Each literal is inverted

47 7.47 DeMorgan s Theorem Eample Cancel as man bubbles as ou can using DeMorgan s theorem. W X Y F Z

48 = 7.48 AND-OR / NAND-NAND Canonical Sums ield AND-OR Implementation NAND-NAND Implementation

49 = NOR-NOR Implementation 7.49 OR-AND / NOR-NOR Canonical Products ield OR-AND Implementation =

50 7.50 DeMorgan's Practice Convert the circuits mu below to use onl NAND or NOR gates? Door Opened Ke in Ignition Headlights on D K H B Warning Buer B = (K+H) D

51 7.51 Logic Snthesis Describe the function Usuall with a truth table Find the sum of minterm (or product of materm) epression In this class, ou're onl responsible for the sum of minterm approach Use Boolean Algebra (T8-T11) to find a simplified epression

52 Primes between Snthesie/Simplif Eercise 1 Snthesie this function First generate the canonical sum Then use theorems to simplif T8 XY+XZ = X(Y+Z) T8 (X+Y)(X+Z) = X+YZ T9 X + XY = X T9 X(X+Y) = X T10 XY + XY = X T10 (X+Y)(X+Y ) = X T11 XY + X Z + YZ = XY + X Z T11 (X+Y)(X +Z)(Y+Z) = (X+Y)(X +Z) P = X'YZ' + X'YZ + XY'Z + XYZ X'Y(Z' + Z) + XZ(Y'+Y) [T8] X'Y + XZ [T5, T1'] X Y Z P

53 7.53 Snthesie/Simplif Eercise 2 Snthesie each output separatel First generate the canonical sum Then use theorems to simplif T8 XY+XZ = X(Y+Z) T8 (X+Y)(X+Z) = X+YZ T9 X + XY = X T9 X(X+Y) = X T10 XY + XY = X T10 (X+Y)(X+Y ) = X T11 XY + X Z + YZ = XY + X Z T11 (X+Y)(X +Z)(Y+Z) = (X+Y)(X +Z) M1 = m2 + m3 + m4 + m5 + m6 + m7 X'YZ' + X'YZ + XY'Z' + XY'Z + XYZ' + XYZ [T3 (A = A + A) allows us to replicate m 6 and m 7 ( XYZ' + XYZ )] X'YZ' + X'YZ + XYZ' + XYZ + XY'Z' + XY'Z + XYZ' + XYZ Y(X'Z' +X'Z + XZ' + XZ) + X(Y'Z' + Y'Z + YZ' + YZ) [T8] Y(X'(Z'+Z) + X(Z'+Z) ) + X(Y'(Z+Z') + Y(Z' + Z)) [T8/T5 or T10] Y(X'+ X ) + X(Y' + Y) [T8/T5] = Y + X [Final Answer] M0 = m1 + m4 + m5 + m6 + m7 X'Y'Z + XY'Z' + XY'Z + XYZ' + XYZ X'Y'Z + XY'Z + XY'Z' + XY'Z + XYZ' + XYZ [Use T3 to replicate m 5 ] Y'Z(X' + X) + X(Y'Z' + Y'Z + YZ' + YZ) [T8] Y'Z + X [T8/T5 or T10] = Y'Z + X [Final Answer] I3 I2 I1 M1 M Encode the highest input ID (ie. 3, 2, or 1) that is ON (=1)

54 1 s Count of Inputs 7.54 Snthesie/Simplif Eercise 3 (Optional) Snthesie each output separatel First generate the canonical sum Then use theorems to simplif T8 XY+XZ = X(Y+Z) T8 (X+Y)(X+Z) = X+YZ T9 X + XY = X T9 X(X+Y) = X T10 XY + XY = X T10 (X+Y)(X+Y ) = X T11 XY + X Z + YZ = XY + X Z T11 (X+Y)(X +Z)(Y+Z) = (X+Y)(X +Z) C1 = m3 + m5 + m6 + m7 X'YZ + XY'Z + XYZ' + XYZ [Replicate m 7 twice so we can simplif the others: m3 + m7 + m5 + m7 + m6 + m7] X'YZ + XYZ + XY'Z + XYZ + XYZ' + XYZ YZ(X'+X) + XZ(Y'+Y) + XY(Z'+Z) = YZ + XZ + XY [Final Answer] C0 = m1 + m2 + m4 + m7 X'Y'Z + X'YZ' + XY'Z' + XYZ [Not much to factor that will cause simplification] X'(Y'Z + YZ') + X(Y'Z' + YZ) [But write the truth tables of Y'Z+YZ' and Y'Z'+YZ] X'(YZ) + X(YZ)' [But if we let W=YZ then we have X'W + XW' write its TT] X Y Z [Final Answer] I3 I2 I1 C1 C

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